JP4855036B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for etching an object to be processed. The present invention also relates to a method for manufacturing a semiconductor device including a structure in which a conductive layer and an insulating layer are stacked.

  A circuit for driving a light-emitting device or a liquid crystal device, or an integrated circuit having a function of performing arithmetic processing is manufactured by stacking various layers such as a conductive layer, an insulating layer, and a semiconductor layer. Therefore, a variation in surface height from the reference plane due to the difference in the laminated structure, that is, a step is generated. When the level difference becomes large, it becomes difficult to form a layer so as to cover the level difference, and defects such as disconnection of wiring may occur. In addition, in a light emitting device, a deviation of an emission spectrum extracted outside due to a step may occur.

  Therefore, in order to be able to alleviate the level difference, the surface is flattened by chemical mechanical polishing or the like, or the layer is formed using a material having self-flatness such as acrylic, polyimide, siloxane, etc. Technology has been developed.

As the development of a technique for reducing the level difference by providing a layer having a planarized surface as described above proceeds, the development of a technique for processing the formed layer is also required. For example, Patent Document 1 discloses a technique for etching an organic polysiloxane film using a processing gas composed of CF ₄ , N _2, and Ar.

JP 2001-127040 A

  An object of the present invention is to provide a technique for selectively etching a layer containing siloxane. Another object of the present invention is to provide a semiconductor device in which malfunctions caused by defects caused during etching are reduced.

  According to one method for manufacturing a semiconductor device of the present invention, an insulating layer is etched using a processing gas including a hydrogen bromide gas on an object to be processed including a structure in which a conductive layer and an insulating layer are stacked. It is characterized by processing.

  According to one method for manufacturing a semiconductor device of the present invention, a mask is formed over an object to be processed including a structure in which a conductive layer and an insulating layer are stacked, and the insulating layer is formed using a processing gas containing hydrogen bromide gas. An etching process is included.

  One method for manufacturing a semiconductor device of the present invention includes a step of forming an electrically conductive layer and an insulating layer covering the electrically conductive layer, and then etching the insulating layer so that part of the electrically conductive layer is exposed. Here, etching of the insulating layer is performed using a processing gas containing hydrogen bromide gas.

  One method for manufacturing a semiconductor device of the present invention includes a step of forming a mask on the insulating layer after forming a conductive layer electrically connected to the transistor and an insulating layer covering the conductive layer. Then, after the mask is formed, the insulating layer is etched using a processing gas containing hydrogen bromide gas.

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, a conductive layer electrically connected to a transistor and an insulating layer covering the conductive layer are formed, and then the insulating layer is etched so that a part of the conductive layer is exposed. Process. Here, etching of the insulating layer is performed using a processing gas containing hydrogen bromide gas.

  One light-emitting device of the present invention includes a light-emitting element and a semiconductor device provided to drive the light-emitting element. A semiconductor device includes a step of selectively etching an insulating layer so that a part of the conductive layer is exposed after forming a conductive layer electrically connected to the transistor and an insulating layer covering the conductive layer It was produced by the production method. Here, etching of the insulating layer is performed using a processing gas containing hydrogen bromide gas.

  By implementing the present invention, the insulating layer containing siloxane can be selectively etched, and the conductive layer stacked with the insulating layer containing siloxane can be prevented from being excessively etched. In addition, by carrying out the present invention, particularly when an insulating layer containing siloxane is etched, the conductive layer laminated with the insulating layer can be prevented from being excessively etched. Thus, a semiconductor device with reduced malfunction can be obtained.

  Hereinafter, one embodiment of the present invention will be described. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of the embodiment.

(Embodiment 1)
One embodiment of the present invention will be described with reference to FIG.

  The etching method of the present invention includes a step of etching an insulating layer containing siloxane using a processing gas containing hydrogen bromide gas (HBr gas).

  Here, siloxane is a compound that contains elements such as silicon (Si), oxygen (O), hydrogen (H), and further contains Si—O—Si bonds (siloxane bonds). Specific examples of the siloxane include compounds such as a chain siloxane represented by the following general formula (1) and a cyclic siloxane represented by the following general formula (2). Here, in the general formulas (1) and (2), hydrogen may be substituted with an aryl group such as a phenyl group in addition to an alkyl group such as a methyl group. N is a natural number.

  The insulating layer containing siloxane is a single layer or a multilayer including at least one layer formed using siloxane. Here, the method for forming the layer is not particularly limited, and a layer formed using a method such as an inkjet method in addition to the coating method may be used. Further, heat treatment may be performed after the formation of the insulating layer containing siloxane.

  With respect to an object to be processed (FIG. 1A) including a structure in which a conductive layer 301 and an insulating layer 302 containing siloxane are stacked, the insulating layer 302 is selectively etched using a processing gas containing HBr gas. This (see FIG. 1B) facilitates etching with a high selection ratio between the conductive layer 301 and the insulating layer 302. That is, the conductive layer 301 can be prevented from being excessively etched with the etching of the insulating layer 302. Note that a mask 303 is provided over a portion of the insulating layer 302 that is not particularly required to be etched. Note that the mask is shaped so that the insulating layer 302 can be processed into a desired shape. For example, a mask made of a photosensitive resin such as a resist can be used. Here, there is no particular limitation on the etching method. In addition to the inductively coupled plasma (ICP) method, a capacitively coupled plasma (CCP) method, an electron cyclotron resonance plasma (ECR). ) Method, reactive ion etching (RIE) method, or the like.

  The conductive layer 301 is preferably formed using one or more metals selected from aluminum (Al), molybdenum (Mo), and the like in addition to titanium (Ti). Thereby, the selection ratio between the conductive layer 301 and the insulating layer 302 is further increased.

In addition to the HBr gas, the processing gas is one or two selected from oxygen gas (O ₂ gas), carbon tetrafluoride gas (CF ₄ gas), sulfur hexafluoride gas (SF ₆ ), and the like. It is preferable that the above gas is contained. When carbon (C) is contained in the insulating layer 302, carbon can be exhausted as a gas such as CO or CO ₂ by containing O ₂ gas, and a decrease in etching rate caused by carbon is prevented. Can do. By containing CF ₄ gas, the selection ratio between the conductive layer 301 and the insulating layer 302 becomes higher, and it becomes easier to selectively etch the insulating layer 302. Further, the HBr gas and CF ₄ gas, it is preferable that the mixing ratio is included as a HBr / CF ₄ = 5 to 8. Thereby, the selection ratio between the conductive layer 301 and the insulating layer 302 is further increased. The pressure during etching is preferably adjusted to be less than 2 Pa, and more preferably adjusted to 1.7 Pa or less. By adjusting the pressure in this way, it is possible to suppress the generation of residues due to siloxane.

  Note that the conductive layer 301 and the insulating layer 302 may each be a single layer or multiple layers. For example, the conductive layer 301 may be a layer in which a layer made of aluminum and a layer made of titanium are stacked. The insulating layer 302 is a layer in which a layer containing siloxane and a layer made of an insulator such as silicon oxide are stacked. It may be a layer.

(Embodiment 2)
One mode of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.

  After the insulating layer 101a is formed over the substrate 100, the insulating layer 101b is further formed so as to be stacked over the insulating layer 101a. The insulating layer 101a is preferably a layer in which impurities are difficult to diffuse. For example, the insulating layer 101a is preferably a layer formed of silicon nitride, silicon nitride containing oxygen, or the like. The insulating layer 101b is preferably a layer that reduces a difference in stress generated between the insulating layer 101b and a semiconductor layer formed in a later step. For example, the insulating layer 101b is formed of silicon oxide or silicon oxide containing a small amount of nitrogen. It is preferable that Here, a method for forming the insulating layers 101a and 101b is not particularly limited, and the insulating layers 101a and 101b may be formed by a plasma CVD method, a low pressure CVD method, a sputtering method, a PVD method, or the like. The substrate 100 is not particularly limited, and a substrate made of an insulator such as glass or quartz, or a substrate made of silicon, SUS, or the like provided with an insulating layer may be used. In addition, a flexible substrate made of plastic such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN) may be used.

  Next, the semiconductor layer 102 is formed over the insulating layer 101b. There is no particular limitation on the semiconductor layer 102, and the semiconductor layer 102 may be formed using either an amorphous semiconductor or a crystalline semiconductor, or a semiconductor including both an amorphous component and a crystalline component. In addition, it may be a semi-amorphous semiconductor (SAS) also called a microcrystalline semiconductor or a microcrystal. (Fig. 2 (A))

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is the main component, the Raman spectrum shifts to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. In order to terminate dangling bonds (dangling bonds), hydrogen or halogen is contained at least 1 atomic% or more. The SAS is formed by glow discharge decomposition (plasma CVD) of a silicide gas. As the silane-based gas, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF ₄ or the like can be used. Further, F ₂ and GeF ₄ may be mixed. This silicide gas may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times, the pressure is in the range of approximately 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature is preferably 300 ° C. or lower, and can be formed even at a substrate heating temperature of 100 to 200 ° C. Here, as an impurity element mainly taken in at the time of film formation, it is desirable that impurities derived from atmospheric components such as oxygen, nitrogen, and carbon be 1 × 10 ²⁰ cm ⁻³ or less, and in particular, the oxygen concentration is 5 × 10 5. It is preferable to be ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a favorable SAS can be obtained. Further, a SAS layer formed of a hydrogen-based gas may be further stacked on a SAS layer formed of a fluorine-based gas as a semiconductor film.

  A typical example of the amorphous semiconductor is hydrogenated amorphous silicon. A typical example of the crystalline semiconductor is polysilicon. For polysilicon, a so-called high-temperature polysilicon using as a main material polysilicon formed through a process temperature of 800 ° C. or higher, or a so-called low-temperature using as a main material polysilicon formed at a process temperature of 600 ° C. or less. It includes polysilicon and polysilicon crystallized by adding an element that promotes crystallization.

  When a semiconductor layer made of a crystalline semiconductor is used as the semiconductor layer 102, there is no particular limitation on a method for forming the semiconductor layer, and a metal element that promotes crystallization such as laser crystallization, thermal crystallization, or nickel is used. The amorphous semiconductor layer can be crystallized and formed using a crystallization method appropriately selected from the thermal crystallization methods and the like. At this time, a plurality of crystallization methods may be used in combination. For example, laser crystallization may be performed after thermal crystallization. In the case where a substrate that can withstand a high heating temperature is used, the semiconductor layer 102 may be formed by a deposition method in which a crystalline semiconductor is deposited.

  There is no particular limitation on the heating method in the thermal crystallization method, and furnace, rapid thermal annealing (RTA) method or the like can be used. The RTA method may be a gas RTA method using a high-temperature gas or a lamp RTA method that irradiates intense light.

  There is no particular limitation on a method for introducing the metal element that promotes crystallization, and a layer containing a metal element that promotes crystallization is formed on the amorphous semiconductor by a sputtering method or the like. In addition to the method of providing a metal element solution containing a metal element that promotes crystallization on the amorphous semiconductor, a method of providing a layer containing the metal element that promotes crystallization on the amorphous semiconductor is used. May be. Here, nickel, palladium, or the like can be used as a metal element that promotes crystallization. Examples of the metal salt solution include an acetate solution containing nickel.

Further, there is no particular limitation on the laser crystallization method, and any one or both of a continuous wave laser and a pulsed laser may be used. Further, since there is no particular limitation on the laser medium, excimer laser, argon laser, krypton laser, He-Cd laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, Y ₂ O ₃ laser, glass laser, ruby Lasers of various laser media such as lasers and Ti: sapphire lasers can be used. Examples of the continuous wave laser include the second harmonic (532 nm) and the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm). In this way, a crystal having a large grain size can be obtained by irradiating the second harmonic wave to the fourth harmonic laser beam of the fundamental wave. Moreover, when using a pulse oscillation type laser, the oscillation frequency of the laser beam is set to 0.5 MHz or more, and a frequency band that is significantly higher than a frequency band of several tens to several hundreds Hz that is normally used is used. By performing laser crystallization, a semiconductor layer having crystal grains continuously grown in the scanning direction can be formed.

Note that in the case where the amorphous semiconductor layer contains a large amount of hydrogen, the amorphous semiconductor layer is formed in a gas having low reactivity such as nitrogen so that the hydrogen concentration is 1 × 10 ²⁰ atoms / cm ³ or less. It is preferable to perform the process for laser crystallization after performing the process which heats. This can prevent damage to the layer that may occur when using laser crystallization. In addition, by performing laser crystallization in an inert gas atmosphere such as a rare gas or nitrogen, roughness of the surface of the semiconductor layer can be reduced.

  The semiconductor layer 102 is formed as described above. Incidentally, when crystallization is performed using a metal element, it is preferable to reduce or remove the metal element contained in the semiconductor layer 102 after crystallization. A transistor having better characteristics can be obtained by reducing or removing the metal element. Such a process for reducing or removing a metal element contained in the semiconductor layer 102 is called gettering. The gettering method is not particularly limited, and can be performed by the following method. First, after an amorphous semiconductor layer is formed over the semiconductor layer 102, heat treatment is performed. The treatment temperature for the heat treatment is preferably adjusted so that the metal contained in the semiconductor layer 102 can be diffused into the amorphous semiconductor layer provided thereabove. There is no particular limitation on the heating method, and furnace, RTA, or the like can be used. However, using RTA is preferable because the heat treatment time can be shortened. The metal element moves to the amorphous semiconductor layer by heating. Note that at this time, part of the amorphous semiconductor layer may crystallize. The amorphous semiconductor layer which becomes unnecessary after heating is removed by etching. At this time, a thin oxide film is preferably provided between the semiconductor layer 102 and the amorphous semiconductor layer. This facilitates selective etching of the amorphous semiconductor layer. The thin oxide film is preferably a film that can be easily etched with high selectivity with respect to each of the semiconductor layer 102 and the amorphous semiconductor layer. For example, the semiconductor layer 102 and the amorphous semiconductor layer are both silicon. In this case, silicon oxide is preferable. The etching of the amorphous semiconductor layer and the oxide film is preferably performed by a wet process using a solution. The amorphous semiconductor layer is preferably etched using a solution of, for example, tetramethylammonium hydroxide (TMAH) or choline. The oxide film is preferably etched using a solution such as hydrofluoric acid. Thus, etching can be performed with a high selectivity.

  An impurity element for imparting conductivity, such as boron or phosphorus, may be added to the semiconductor layer 102. Thus, the threshold value of the transistor can be adjusted.

  Next, the semiconductor layer 102 is processed to form a semiconductor layer 103, a semiconductor layer 104, a semiconductor layer 105, and a semiconductor layer 106 having desired shapes. There is no particular limitation on a processing method, and for example, a method of etching an unnecessary semiconductor layer 102 after forming a resist mask over the semiconductor layer 102 may be used. Here, there is no particular limitation on the etching method, and the dry etching method or the wet etching method may be used. Also, there is no particular limitation on the method for forming the resist mask. In addition to the photolithography method, a method of forming a mask having a desired shape by drawing while controlling the timing and position of ejecting droplets, such as an inkjet method. It may be used.

  Next, the gate insulating layer 107 is formed so as to cover the semiconductor layer 103, the semiconductor layer 104, the semiconductor layer 105, and the semiconductor layer 106. The gate insulating layer 107 functions as a gate insulating layer. There is no particular limitation on the formation method of the gate insulating layer 107, and the gate insulating layer 107 may be formed by a plasma CVD method, a low pressure CVD method, a sputtering method, a PVD method, or the like. In addition, the gate insulating layer 107 may be formed by oxidizing the surfaces of the semiconductor layer 103, the semiconductor layer 104, the semiconductor layer 105, and the semiconductor layer 106. The gate insulating layer 107 may be formed using silicon oxide or silicon nitride, silicon oxide containing nitrogen, silicon nitride containing oxygen, or the like. Further, the gate insulating layer 107 may be either a single layer or a layer composed of multiple layers made of different materials.

  Next, the first conductive layer is in contact with the gate insulating layer 107 over a portion where the gate insulating layer 107 overlaps with each of the semiconductor layer 103, the semiconductor layer 104, the semiconductor layer 105, and the semiconductor layer 106. 108 is formed. Then, a second conductive layer 109 is formed so as to be stacked with the first conductive layer 108. The first conductive layer 108 and the second conductive layer 109 are preferably formed using different conductive materials. The first conductive layer 108 is preferably formed using a conductive material that has good adhesion to the gate insulating layer 107, for example, titanium nitride, tantalum nitride, titanium, tantalum, or the like. preferable. The second conductive layer 109 is preferably formed using a conductive material with low resistivity, such as tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), or It is preferable to use an alloy containing these metals as a main component or a metal compound. Examples of the alloy include an alloy of aluminum and silicon, an alloy of aluminum and neodymium, and the like. Examples of the metal compound include tungsten nitride. Here, the method for forming the first conductive layer 108 and the second conductive layer 109 is not particularly limited, and any method such as a sputtering method or an evaporation method may be used. (Fig. 2 (B))

  Next, the mask 110a, the mask 110b, the mask 110c, the mask 110d, the mask 110e, and the mask 110f are formed over the second conductive layer 109, respectively. Then, the first conductive layer 108 and the second conductive layer 109 are etched, so that the first conductive layer 121, the first conductive layer 122, the first conductive layer 123, the first conductive layer 124, the first conductive layer Conductive layer 125, first conductive layer 126, second conductive layer 111, second conductive layer 112, second conductive layer 113, second conductive layer 114, second conductive layer 115, second The conductive layers 116 are formed so that the sidewalls of the conductive layers are inclined with respect to the horizontal plane of the conductive layers (FIG. 2C).

  Next, the second conductive layer 111, the second conductive layer 112, the second conductive layer 113, and the second conductive layer 114 are provided with the mask 110a, the mask 110b, the mask 110c, the mask 110d, and the mask 110f provided. The second conductive layer 115 and the second conductive layer 116 are selectively etched, and the second conductive layer 131, the second conductive layer 132, the second conductive layer 133, the second conductive layer 134, Two conductive layers 135 and a second conductive layer 136 are formed. At this time, the second conductive layer 131, the second conductive layer 132, the second conductive layer 133, the second conductive layer 134, the second conductive layer 135, and the second conductive layer 136 are the respective conductive layers. It is preferable to perform etching and processing under conditions of high anisotropy so that the side walls of the conductive layer are perpendicular to the horizontal plane of each conductive layer. Accordingly, the inclined portions of the sidewalls of the second conductive layer 111, the second conductive layer 112, the second conductive layer 113, the second conductive layer 114, the second conductive layer 115, and the second conductive layer 116 are formed. Removed. In this manner, each of the first conductive layer 121, the first conductive layer 122, the first conductive layer 123, the first conductive layer 124, the first conductive layer 125, and the first conductive layer 126 is provided. In addition, the second conductive layer 131, the second conductive layer 132, the second conductive layer 133, the second conductive layer 134, and the second conductive layer having sidewalls on the inner side of the respective first conductive layers. 135 and an electrode formed by laminating the second conductive layer 136 and a connection portion are formed. Specifically, an electrode 117 composed of the first conductive layer 121 and the second conductive layer 131, an electrode 118 composed of the first conductive layer 122 and the second conductive layer 132, the first conductive layer 124, An electrode 127 composed of the second conductive layer 134, an electrode 128 composed of the first conductive layer 125 and the second conductive layer 135, an electrode 129 composed of the first conductive layer 126 and the second conductive layer 136, Connection portions 130 each including the first conductive layer 123 and the second conductive layer 133 are formed. The electrode 117, the electrode 118, the electrode 127, the electrode 128, and the electrode 129 each function as a gate electrode. (Fig. 2 (D))

Note that there is no particular limitation on a dry etching method applied when each conductive layer is etched, but it is preferable to perform etching using an inductively coupled plasma (ICP) method. The gas used for etching may be appropriately selected depending on the conductive material to be etched, but chlorine gas such as Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , CF ₄ , CF ₅ , SF ₆ or NF ₃ or the like. One or more selected from fluorine-based gas, O ₂ , and Ar may be used.

  In addition, the mask 110a, the mask 110b, the mask 110c, the mask 110d, and the mask 110f may be masks that are formed to have a desired shape and then thinned by performing ashing. By using such a mask, an electrode with a finer shape can be formed, and as a result, a transistor with a short channel length can be obtained. A circuit that operates at higher speed can be obtained by manufacturing a transistor with a short channel length.

  Next, an impurity element capable of imparting n-type conductivity is added using the electrode 117, the electrode 118, the electrode 127, the electrode 128, the electrode 129, and the connection portion 130 as a mask, and the first n-type impurity region 140a and the first n-type impurity region are added. The impurity region 140b, the first n-type impurity region 141a, the first n-type impurity region 141b, the first n-type impurity region 142a, the first n-type impurity region 142b, the first n-type impurity region 142c, the first One n-type impurity region 143a and a first n-type impurity region 143b are provided. There is no particular limitation on the impurity element which can impart n-type, and phosphorus, arsenic, or the like can be used. (Fig. 3 (A))

  Next, a mask 153 a that covers the semiconductor layer 103, a mask 153 d that covers the semiconductor layer 106, and a mask 153 b and mask 153 c that cover part of the semiconductor layer 105 are formed. An impurity element imparting n-type conductivity is added using the mask 153a, the mask 153b, the mask 153c, the mask 153d, and the second conductive layer 132 as a mask, and a second n-type impurity having a concentration higher than that of the first n-type impurity region is added. Along with the region 144a, the second n-type impurity region 144b, the second n-type impurity region 147a, the second n-type impurity region 147b, and the second n-type impurity region 147c, the same as the first n-type impurity region Alternatively, the third n-type impurity region 145a, the third n-type impurity region 145b, the third n-type impurity region 148a, and the third n-type impurity region having a concentration lower than that of the second n-type impurity region. 148b, a third n-type impurity region 148c, and a third n-type impurity region 148d are provided. Here, the second n-type impurity regions 147a, 147b, 147c, and 147d are regions to which an impurity element imparting n-type is further added in the first n-type impurity regions 142a, 142b, and 142c, respectively. . (Fig. 3 (B))

  Next, the mask 153a, the mask 153b, the mask 153c, and the mask 153d are removed, and a mask 155a that covers the semiconductor layer 103 and a mask 155b that covers the semiconductor layer 105 are formed. An impurity element imparting p-type conductivity is added using the mask 155a, the mask 155b, the electrode 117, and the electrode 129 as a mask, and the first p-type impurity region 160a, the first p-type impurity region 160b, and the first p-type impurity region are added. 163a, a first p-type impurity region 163b, a second p-type impurity region 161a, a second p-type impurity region 161b, a second p-type impurity region 164a, and a second p-type impurity region 164b are provided. The second p-type impurity region 161a, the second p-type impurity region 161b, the second p-type impurity region 164a, and the second p-type impurity region 164b reflect the shapes of the electrode 117 and the electrode 129, and The p-type impurity region 160a, the first p-type impurity region 160b, the first p-type impurity region 163a, and the first p-type impurity region 163b are provided in a self-aligned manner. Here, there is no particular limitation on the impurity element imparting p-type conductivity, and boron or the like can be used. (Fig. 3 (C))

  As described above, impurity regions functioning as a source or a drain are provided, and regions 146, 149a, 149b, 162, and 165 in which channels are formed are also provided.

  The second n-type impurity regions 144a, 144b, 147a, 147b, and 147c function as the source or drain of the n-channel transistor. The first p-type impurity regions 160a, 160b, 163a, and 163b function as the source or drain of the p-channel transistor. Then, by providing third n-type impurity regions 145a and 145b and second p-type impurity regions 161a, 161b, 164a and 164b between the region functioning as the drain and the channel formation region, The electric field can be relaxed and deterioration of the transistor due to hot carriers can be suppressed. In addition, by providing third n-type impurity regions 148a, 148b, 148c, and 148d between the region functioning as the drain and the channel formation region, deterioration of the transistor due to hot carriers is suppressed and off current is reduced. Can be reduced. In this manner, a transistor capable of reducing the electric field from the drain can be manufactured.

  Note that a method for manufacturing a transistor and a structure thereof are not limited to those described in this embodiment mode. For example, a transistor having an LDD structure manufactured by providing a sidewall on a sidewall of a conductive layer functioning as a gate electrode may be used. Further, a multi-gate transistor having a plurality of gate electrodes or a single-gate transistor may be used.

  After the transistor is manufactured, treatment for activating the added impurity is preferably performed. The treatment for activation is not particularly limited, and can be performed by using a furnace, rapid thermal annealing method, laser irradiation method, or the like. Further, when the impurity is activated by furnace or rapid thermal annealing, it is preferable to perform the treatment in an atmosphere of nitrogen gas or inert gas so that the gate electrode is not easily oxidized. In addition, when activation processing is performed after the first insulating layer 167 described below is provided, the first insulating layer 167 can further prevent oxidation of the gate electrode, which is preferable.

  Next, a first insulating layer 167 is formed so as to cover the transistor. There is no particular limitation on the first insulating layer 167, and it can be formed using silicon oxide, silicon nitride, or the like. Further, silicon oxide may contain nitrogen, and silicon nitride may contain oxygen.

  Next, a second insulating layer 168 is formed so as to be stacked with the first insulating layer 167. There is no particular limitation on the second insulating layer 168, and the second insulating layer 168 can be formed using silicon oxide, silicon nitride, or the like. Further, silicon oxide may contain nitrogen, and silicon nitride may contain oxygen. (Fig. 4 (A))

  Next, hydrogenation is performed by heat treatment in a hydrogen atmosphere. However, when the second insulating layer 168 is formed using silicon nitride containing hydrogen, hydrogenation treatment using hydrogen contained in the second insulating layer 168 can be performed. In this case, the heat treatment is not necessarily performed in a hydrogen atmosphere, and the heat treatment may be performed in a nitrogen gas or inert gas atmosphere. Note that silicon nitride containing hydrogen can be obtained by, for example, forming a film by a plasma CVD method using a silane-based gas, ammonia gas, and nitrous oxide gas. Moreover, it is preferable that the heat processing temperature in this process shall be 350 to 500 degreeC. By performing such heat treatment, dangling bonds contained in the semiconductor layer can be terminated with hydrogen.

  Next, an opening that penetrates the first insulating layer 167, the second insulating layer 168, and the gate insulating layer 107 to reach a region functioning as a source or drain of the semiconductor layers 103, 104, 105, and 106 is formed. The opening may be formed by selectively etching a portion where the opening is to be formed using a mask made of resist or the like. There is no particular limitation on the etching method, and any one or both of a dry etching method and a wet etching method may be used. The gas or solution used for etching is not particularly limited, and may be appropriately selected so that etching can be performed with a high selectivity.

  Next, a conductive layer is formed so as to cover the opening. After that, the conductive layer is etched to form connection portions 169a, 169b, 170a, 170b, 171a, 171b, 172a, and 172b that are electrically connected to a region functioning as a source or drain, A wiring 156 for sending a target signal is formed. Note that there is no particular limitation on a method for forming the connection portions 169a, 169b, 170a, 170b, 171a, 171b, 172a, 172b, and the wiring 156, and as described above, the conductive layer is formed and then etched. Alternatively, the conductive layer may be selectively formed at a predetermined place by adjusting the timing and position of discharging the droplet. In addition, an electroplating method, a printing method, a reflow method, a damascene method, or the like may be used. There is no particular limitation on the material used for forming the conductive layer, but it is preferable to use Al, Mo, Ti, or the like, or an alloy containing these metals, for example, aluminum containing several percent of silicon. . Specifically, in addition to a single conductive layer made of a material having low resistivity such as aluminum or molybdenum, a conductive layer formed by laminating a layer made of aluminum or molybdenum and a layer made of titanium is used. Is preferred. In addition, the wiring 156 is formed, and the connection portion 178 is formed in the external connection region 202, and the wiring 179a and the wiring 179b are formed in the wiring region 203, respectively. (Fig. 4 (B))

  Next, a third insulating layer 180 and a fourth insulating layer 181 are formed so as to cover the connection portion and the wiring. The third insulating layer 180 is preferably formed using silicon oxide. Accordingly, a short circuit between wirings or electrodes provided in different layers through the third insulating layer 180 and the fourth insulating layer 181 can be further prevented. The fourth insulating layer 181 is preferably formed using siloxane. This is because siloxane has high self-flatness (that is, a surface having a horizontal surface can be easily obtained) and has higher heat resistance than a resin material such as acrylic. Note that there is no particular limitation on the method for forming the third insulating layer 180, and the third insulating layer 180 can be formed by a coating method or the like. (Fig. 5 (A))

Next, an opening 184 that reaches the connection portion 172 a through the third insulating layer 180 and the fourth insulating layer 181, an opening 182 that reaches the wiring 156, and an opening 183 that reaches the connection portion 178 are provided. The third insulating layer 180 is etched so that the wirings 179a and 179b are exposed. At this time, a connection portion connected to the source or drain of the transistor provided in the driver circuit region 204 may be exposed. Etching is preferably performed using a processing gas containing HBr gas. By etching in this way, the third portion is selectively formed so that the selection ratio with respect to the conductive layer forming the connection portions 169a, 169b, 170a, 170b, 171a, 171b, 172a, 172b and the wiring 156 is increased. The insulating layer 180 and the fourth insulating layer 181 can be etched. Further, the opening portions 182, 183, and 184 and the drive circuit region 204 have different etching rates depending on the area or shape of the portion to be etched, and overetching occurs in any of the openings or the drive circuit region 204. However, by performing etching as in the present embodiment, defects caused by over-etching can be reduced. In addition to HBr gas, oxygen gas (O ₂ gas), carbon tetrafluoride gas (CF ₄ gas) and the like are preferably contained. As a result, the selectivity between the conductive layer and the third insulating layer 180 is increased. Among these, it is preferable that CF ₄ gas is contained. By including the CF ₄ gas, the wiring 156, the connection portion 172a, and the wirings 179a and 179b can be further prevented from being over-etched. Note that, until the fourth insulating layer 181 is etched and the third insulating layer 180 is etched, chlorine gas may be contained in addition to the HBr gas. As a result, the etching rate can be adjusted to be high, and the processing efficiency is improved. Here, the etching method is not particularly limited, and in addition to an inductively coupled plasma (ICP) method, a capacitively coupled plasma (CCP) method, an electron cyclotron resonance plasma (ECR). ) Method, reactive ion etching (RIE) method, or the like. (Fig. 5 (B))

  In this embodiment, a semiconductor device including the transistor 173 and the transistor 174 in the driver circuit region 204 and the transistor 175 and the transistor 176 in the pixel region 206 can be obtained as described above. The semiconductor device thus obtained can be used as an active matrix substrate or the like for driving a light emitting element or a liquid crystal element.

  In this embodiment, an embodiment of a light-emitting device using the semiconductor device manufactured as described above will be described below with reference to FIGS.

  Next, an electrode 185 that is electrically connected to the first p-type impurity region 163a of the transistor 176 through the connection portion 172a is formed. The electrode 185 may be formed by forming a conductive layer covering the opening 184 and then etching the conductive layer into a desired shape. (Fig. 6 (A))

  Next, a partition layer 186 having an opening is formed so that a part of the electrode 185 is exposed and the wiring 156, the connection portions 178, 170a, and 170b, and the wirings 179a and 179b are exposed. The partition layer 186 is not particularly limited and can be formed using an organic material such as acrylic, polyimide, or resist, an inorganic material such as silicon oxide, silicon nitride, aluminum nitride, or diamond like carbon (DLC), or siloxane. . (Fig. 6 (B))

  Next, a light emitting layer 188 is formed so as to be stacked with the electrode 185 exposed from the opening of the partition wall layer 186. The light emitting layer 188 contains a light emitting substance. There is no particular limitation on the light-emitting layer 188, and the light-emitting layer 188 may include only one of an organic material and an inorganic material, or may include both an organic material and an inorganic material. The light emitting layer 188 may be a single layer or a multilayer. In addition, the light-emitting substance may be a substance that emits fluorescence or a substance that emits phosphorescence.

  Next, an electrode 189 is formed so as to be stacked with the light-emitting layer 188. Here, it is preferable that one or both of the electrode 185 and the electrode 189 be formed of a conductive material that can transmit visible light. Thus, a light emitting element that can extract light emitted from one electrode or both electrodes can be obtained. Here, examples of the conductive material that can transmit visible light include indium tin oxide, indium tin oxide containing silicon, and zinc oxide. In addition to these conductive materials that can transmit visible light, visible light is difficult to transmit, but in addition to metals such as aluminum, silver, gold, tungsten, and molybdenum, alloys of these metals, such as aluminum containing lithium The electrode can also be formed using silver containing magnesium.

  Next, a protective layer 191 is formed so as to cover a light-emitting element including the light-emitting layer 188 between the electrode 185 and the electrode 189. The protective layer 191 is preferably formed using a material having low moisture permeability, and can be formed using, for example, silicon nitride. In addition, in the case where light emission is extracted from the electrode 189 side, it is preferable that the light-emitting material be formed using a material with higher light-transmitting properties. In addition, a plurality of light emitting layers 188 may be formed for each color to be emitted. For example, if you want to emit light of three colors, red, blue, and green, you can create a light emitting layer that emits red light, a light emitting layer that emits blue light, and a light emitting layer that emits green light as appropriate. Good. In addition, light emission obtained from the light emitting layer may be color-converted with a filter to obtain light emission of a desired color.

  Next, the substrate 100 and the substrate 195 are attached to each other with the sealant 192 so that the transistor and the light-emitting element are sealed inside. At this time, the inner region 193 surrounded by the substrate 100, the substrate 195, and the sealant 192 is preferably filled with nitrogen gas, an inert gas, a resin material with low moisture permeability, or the like. Thus, the light emitting element can be prevented from being deteriorated due to moisture. Here, the sealing material 192 may be provided on the wiring region 203. Further, the external connection region 202 is exposed to the outside, and the connection portion 178 and the flexible printed circuit 194 are electrically connected using a conductive adhesive or the like.

  As described above, a light-emitting device that performs active matrix driving can be manufactured.

  In the light-emitting device manufactured in this embodiment mode, transistors having a cross-sectional structure such as the transistors 175 and 176 are arranged in the row direction and the column direction in the pixel region 206. Then, the light emitting element is driven according to the current supplied from the transistor 175, and emits light of a desired color.

(Embodiment 3)
Since the semiconductor device of the present invention is manufactured using an etching method with a high selection ratio, a light-emitting device or a liquid crystal device with few defects due to etching defects is manufactured by using the semiconductor device of the present invention. can do.

  In this embodiment, a circuit configuration and a driving method included in a light-emitting device having a display function will be described with reference to FIGS. Note that the light-emitting device of this embodiment includes an active matrix driving circuit manufactured by applying the method for manufacturing a semiconductor device of the present invention as described in Embodiment Mode 1. Further, the circuit configuration and driving method of the light emitting device are not limited to those described here.

  FIG. 8 is a schematic view of a light emitting device to which the present invention is applied as viewed from above. In FIG. 8, a pixel portion 6511, a source signal line driver circuit 6512, a writing gate signal line driver circuit 6513, and an erasing gate signal line driver circuit 6514 are provided over a substrate 6500. The source signal line drive circuit 6512, the write gate signal line drive circuit 6513, and the erase gate signal line drive circuit 6514 are each an FPC (flexible printed circuit) 6503 which is an external input terminal via a wiring group. Connected. The source signal line driver circuit 6512, the writing gate signal line driver circuit 6513, and the erasing gate signal line driver circuit 6514 receive a video signal, a clock signal, a start signal, a reset signal, and the like from the FPC 6503, respectively. . A printed wiring board (PWB) 6504 is attached to the FPC 6503. Note that the driver circuit portion is not necessarily provided over the same substrate as the pixel portion 6511 as described above. For example, an IC chip mounted on an FPC on which a wiring pattern is formed (TCP) or the like is used. It may be used and provided outside the substrate.

  In the pixel portion 6511, a plurality of source signal lines extending in the column direction are arranged side by side in the row direction. In addition, current supply lines are arranged side by side in the row direction. In the pixel portion 6511, a plurality of gate signal lines extending in the row direction are arranged side by side in the column direction. In the pixel portion 6511, a plurality of sets of circuits including light-emitting elements are arranged.

  FIG. 9 is a diagram showing a circuit for operating one pixel. The circuit illustrated in FIG. 9 includes a first transistor 901, a second transistor 902, and a light-emitting element 903.

  Each of the first transistor 901 and the second transistor 902 is a three-terminal element including a gate electrode, a drain region, and a source region, and has a channel region between the drain region and the source region. Here, since the source region and the drain region vary depending on the structure and operating conditions of the transistor, it is difficult to limit which is the source region or the drain region. Therefore, in this embodiment, regions functioning as a source or a drain are referred to as a first electrode and a second electrode, respectively.

  The gate signal line 911 and the writing gate signal line driving circuit 913 are provided so as to be electrically connected or disconnected by a switch 918. The gate signal line 911 and the erasing gate signal line driver circuit 914 are provided so as to be electrically connected or disconnected by a switch 919. The source signal line 912 is provided so as to be electrically connected to either the source signal line driver circuit 915 or the power source 916 by the switch 920. The gate of the first transistor 901 is electrically connected to the gate signal line 911. The first electrode of the first transistor is electrically connected to the source signal line 912, and the second electrode is electrically connected to the gate electrode of the second transistor 902. The first electrode of the second transistor 902 is electrically connected to the current supply line 917, and the second electrode is electrically connected to one electrode included in the light-emitting element 903. Note that the switch 918 may be included in the write gate signal line driver circuit 913. The switch 919 may also be included in the erase gate signal line driver circuit 914. Further, the switch 920 may also be included in the source signal line driver circuit 915.

  There is no particular limitation on the arrangement of the transistors, light-emitting elements, and the like in the pixel portion. In FIG. 10, the first electrode of the first transistor 1001 is connected to the source signal line 1004, and the second electrode is connected to the gate electrode of the second transistor 1002. The first electrode of the second transistor is connected to the current supply line 1005, and the second electrode is connected to the electrode 1006 of the light emitting element. Part of the gate signal line 1003 functions as a gate electrode of the first transistor 1001.

  Next, a driving method will be described. FIG. 11 is a diagram for explaining the operation of a frame over time. In FIG. 11, the horizontal direction represents the passage of time, and the vertical direction represents the number of scanning stages of the gate signal line.

  When image display is performed using the light emitting device of the present invention, the screen rewriting operation and the display operation are repeatedly performed during the display period. The number of rewrites is not particularly limited, but is preferably at least about 60 times per second so that a person viewing the image does not feel flicker. Here, a period during which one screen (one frame) is rewritten and displayed is referred to as one frame period.

As shown in FIG. 11, one frame is time-divided into four subframes 501, 502, 503, and 504 including a writing period 501a, 502a, 503a, and 504a and a holding period 501b, 502b, 503b, and 504b. . A light emitting element to which a signal for emitting light is given is in a light emitting state in the holding period. The ratio of the length of the holding period in each subframe is as follows: first subframe 501: second subframe 502: third subframe 503: fourth subframe 504 = 2 ³ : 2 ² : 2 ¹ : 2 ⁰ = 8: 4: 2: 1. As a result, 4-bit gradation can be expressed. However, the number of bits and the number of gradations are not limited to those described here. For example, eight subframes may be provided so that 8-bit gradation can be performed.

  An operation in one frame will be described. First, in the subframe 501, the write operation is performed in order from the first row to the last row. Therefore, the start time of the writing period differs depending on the row. From the row in which the writing period 501a ends, the storage period 501b is started in order. In the holding period, the light-emitting element to which a signal for emitting light is given is in a light-emitting state. Further, the processing proceeds to the next subframe 502 in order from the row in which the holding period 501b ends, and the writing operation is performed in order from the first row to the last row as in the case of the subframe 501. The operation as described above is repeated until the holding period 504b of the subframe 504 ends. When the operation in the subframe 504 is completed, the process proceeds to the next frame. Thus, the accumulated time of the light emission in each subframe is the light emission time of each light emitting element in one frame. Various display colors having different brightness and chromaticity can be formed by changing the light emission time for each light emitting element and combining them in various ways within one pixel.

  When it is desired to forcibly end the holding period in the row that has already finished writing and has shifted to the holding period before the writing up to the last row is completed as in the subframe 504, after the holding period 504b. It is preferable to provide an erasing period 504c and control to forcibly enter a non-light emitting state. Then, the row that is forcibly set to the non-light-emitting state is kept in the non-light-emitting state for a certain period (this period is referred to as a non-light-emitting period 504d). Then, as soon as the writing period of the last row ends, the next (or frame) writing period starts in order from the first row. Accordingly, it is possible to prevent the writing period of the subframe 504 and the writing period of the next subframe from overlapping.

  Note that, in this embodiment, the subframes 501 to 504 are arranged in order from the one with the long retention period. However, the subframes 501 to 504 are not necessarily arranged as in the present embodiment. Alternatively, a long holding period and a short holding period may be arranged at random. In addition, the subframe may be further divided into a plurality of frames. That is, the gate signal line may be scanned a plurality of times during the period when the same video signal is applied.

  Here, the operation of the circuit shown in FIG. 9 in the writing period and the erasing period will be described.

  First, the operation in the writing period will be described. In the writing period, the gate signal line 911 in the n-th row (n is a natural number) is electrically connected to the writing gate signal line driving circuit 913 via the switch 918 and is connected to the erasing gate signal line driving circuit 914. Is disconnected. The source signal line 912 is electrically connected to the source signal line driver circuit through the switch 920. Here, a signal is input to the gate of the first transistor 901 connected to the gate signal line 911 in the n-th row (n is a natural number), and the first transistor 901 is turned on. At this time, video signals are simultaneously input to the source signal lines from the first column to the last column. Note that the video signals input from the source signal lines 912 in each column are independent from each other. A video signal input from the source signal line 912 is input to the gate electrode of the second transistor 902 through the first transistor 901 connected to each source signal line. At this time, a current value supplied from the current supply line 917 to the light-emitting element 903 is determined by a signal input to the second transistor 902. Then, depending on the current value, the light emitting element 903 determines light emission or non-light emission. For example, in the case where the second transistor 902 is a p-channel transistor, the light-emitting element 903 emits light by inputting a low level signal to the gate electrode of the second transistor 902. On the other hand, in the case where the second transistor 902 is an n-channel transistor, the light-emitting element 903 emits light when a high level signal is input to the gate electrode of the second transistor 902.

  Next, the operation in the erasing period will be described. In the erasing period, the gate signal line 911 in the n-th row (n is a natural number) is electrically connected to the erasing gate signal line driving circuit 914 via the switch 919, and is connected to the writing gate signal line driving circuit 913. Not connected. The source signal line 912 is electrically connected to the power source 916 through the switch 920. Here, a signal is input to the gate of the first transistor 901 connected to the gate signal line 911 in the n-th row, and the first transistor 901 is turned on. At this time, the erase signal is simultaneously input to the source signal lines from the first column to the last column. The erase signal input from the source signal line 912 is input to the gate electrode of the second transistor 902 through the first transistor 901 connected to each source signal line. At this time, current supplied from the current supply line 917 to the light-emitting element 903 is blocked by a signal input to the second transistor 902. Then, the light emitting element 903 is forced to emit no light. For example, in the case where the second transistor 902 is a p-channel transistor, the light-emitting element 903 does not emit light when a high level signal is input to the gate electrode of the second transistor 902. On the other hand, in the case where the second transistor 902 is an n-channel transistor, the light emitting element 903 does not emit light by inputting a low level signal to the gate electrode of the second transistor 902.

  In the erasing period, for the nth row (n is a natural number), a signal for erasing is input by the operation as described above. However, as described above, the nth row may be an erasing period and the other row (mth row (m is a natural number)) may be a writing period. In such a case, it is necessary to input a signal for erasure to the n-th row and a signal for writing to the m-th row using the source signal line in the same column. It is preferable to operate as described above.

  The gate signal line 911 and the erasing gate signal line driving circuit 914 are immediately disconnected after the light emitting element 903 in the n-th row does not emit light by the operation in the erasing period described above. The switch 920 is switched to connect the source signal line 912 and the source signal line driver circuit 915. Then, the source signal line and the source signal line driver circuit 915 are connected, and the gate signal line 911 and the writing gate signal line driver circuit 913 are connected. Then, a signal is selectively input from the writing gate signal line driving circuit 913 to the m-th signal line, the first transistor is turned on, and the source signal line driving circuit 915 receives the final signal from the first column. A signal for writing is input to the source signal lines up to the column. By this signal, the m-th row light emitting element emits light or does not emit light.

  Immediately after the writing period for the m-th row is completed as described above, the erasing period for the (n + 1) -th row is started. For this purpose, the gate signal line 911 and the writing gate signal line driving circuit 913 are disconnected, and the switch 920 is switched to connect the source signal line to the power source 916. Further, the gate signal line 911 and the writing gate signal line driving circuit 913 are disconnected, and the gate signal line 911 is connected to the erasing gate signal line driving circuit 914. Then, a signal is selectively input from the erasing gate signal line driving circuit 914 to the gate signal line of the (n + 1) th row to turn on the signal to the first transistor, and an erasing signal is input from the power supply 916. In this way, immediately after the erasing period of the (n + 1) th row is completed, the writing period of the (m + 1) th row is started. Thereafter, similarly, the erasing period and the writing period may be repeated until the erasing period of the last row is operated.

  In this embodiment, the mode in which the m-th writing period is provided between the n-th erasing period and the (n + 1) -th erasing period has been described. An m-th writing period may be provided between the period and the n-th erasing period.

  In this embodiment, when the non-light emission period 504d is provided as in the subframe 504, the erasing gate signal line driver circuit 914 and one gate signal line are disconnected from each other, and the write gate The operation of connecting the signal line driver circuit 913 and the other gate signal lines is repeated. Such an operation may be performed particularly in a frame in which a non-light emitting period is not provided.

(Embodiment 4)
Electronic devices including a semiconductor device manufactured by applying the method for manufacturing a semiconductor device of the present invention and including a light-emitting device and the like that operate using the semiconductor device will be described. Note that any of the electronic devices to which the present invention is applied has few malfunctions of the semiconductor device due to etching and can obtain a good image.

  An example of an electronic device mounted with a light emitting device to which the present invention is applied is shown in FIG.

  FIG. 12A illustrates a laptop personal computer manufactured by applying the present invention, which includes a main body 5521, a housing 5522, a display portion 5523, a keyboard 5524, and the like. A personal computer can be completed by incorporating a light-emitting device manufactured using the method for manufacturing a semiconductor device of the present invention as a display portion.

  FIG. 12B illustrates a telephone manufactured by applying the present invention. The main body 5552 includes a display portion 5551, an audio output portion 5554, an audio input portion 5555, operation switches 5556 and 5557, an antenna 5553, and the like. ing. A telephone can be completed by incorporating a light-emitting device manufactured using the method for manufacturing a semiconductor device of the present invention as a display portion.

  FIG. 12C illustrates a television set manufactured by applying the present invention, which includes a display portion 5531, a housing 5532, a speaker 5533, and the like. A television receiver can be completed by incorporating a light-emitting device manufactured using the method for manufacturing a semiconductor device of the present invention as a display portion.

  As described above, the light-emitting device of the present invention is very suitable for use as a display portion of various electronic devices.

  Note that although a personal computer is described in this embodiment mode, a light-emitting device manufactured using a method for manufacturing a semiconductor device may be mounted on a telephone, a navigation device, a lighting device, or the like.

  In this example, experimental results of experiments for examining the effects of the present invention will be described.

  As shown in FIG. 13, the sample used for the experiment includes a conductive layer 702 on a substrate 701 and an insulating layer 703 stacked on the conductive layer 702. The conductive layer 702 is made of titanium, and the insulating layer 703 is made of siloxane. The substrate 701 is made of glass. A plurality of samples having the same configuration were prepared.

  The experiment was performed as follows. First, a resist mask 704 was formed over the insulating layer 703. Next, each sample was processed under conditions such that the insulating layer 703 could be selectively etched. Etching was performed under different conditions (conditions 1 to 13) for each sample. The etching processing time was 1 minute under any conditions. Each condition is as shown in Table 1. After the insulating layer 703 was etched, the thickness of the conductive layer 702 etched together with the etching of the insulating layer 703 was determined, and the selectivity was determined. Table 1 shows the selectivity in each etching condition. The selection ratio is a value obtained by dividing the etching rate for the insulating layer 703 by the etching rate for the conductive layer 702. A larger selection ratio value indicates that the insulating layer 703 can be selectively etched, and the conductive layer 702 can be prevented from being excessively etched.

It can be seen from Table 1 that the insulating layer 703 can be selectively etched by etching under conditions containing HBr gas. Further, it can be seen that the selection ratio with respect to the insulating layer 703 is further increased by including CF ₄ gas or SF ₆ gas in addition to the HBr gas.

  Moreover, it turned out from the observation result by a scanning electron microscope that the residue resulting from siloxane can be suppressed by adjusting a pressure to become less than 2 Pa, Preferably it is 1.7 Pa or less. Note that FIG. 14 shows an image obtained by observing a sample processed under the condition 12 in Table 1 (a sample different from the sample used in the above experiment) using a scanning electron microscope. FIG. 14A is an image obtained by observing an opening provided to connect the wirings (a portion corresponding to the opening 184 in FIG. 5B). FIG. 14B is an image obtained by observing a region in which the insulating layer covering the wiring 1905 is etched so that the wiring 1905 is exposed. Note that in FIG. 14A, a wiring is exposed from an opening of an insulating layer 1902 in which a layer made of silicon oxide containing nitrogen and a layer made of siloxane are stacked (portion represented by a dotted line 1901). . The wiring is formed by sequentially laminating a layer made of titanium, a layer made of aluminum, and a layer made of titanium. In FIG. 14A, a layer made of titanium provided on the upper layer side can be confirmed. Note that a resist 1903 used as a mask can be confirmed over the insulating layer 1902. In FIG. 14B, a wiring 1905 can be confirmed over the insulating layer 1904. The wiring 1905 is formed together with the wiring exposed from the opening of the insulating layer 1902. The insulating layer 1904 is a layer provided to insulate the wiring 1905 from the wiring provided in the lower layer, and the insulating layer 1904 reflects the shape of the wiring provided in the lower layer and generates a step. Yes. 14A and 14B show that the sample etched by applying the present invention is in a good state with no residue.

4A and 4B illustrate one embodiment of the present invention. 8A and 8B illustrate one embodiment of a method for manufacturing a semiconductor device of the present invention. 8A and 8B illustrate one embodiment of a method for manufacturing a semiconductor device of the present invention. 8A and 8B illustrate one embodiment of a method for manufacturing a semiconductor device of the present invention. 8A and 8B illustrate one embodiment of a method for manufacturing a semiconductor device of the present invention. 8A and 8B illustrate one embodiment of a method for manufacturing a semiconductor device of the present invention. 8A and 8B illustrate one embodiment of a method for manufacturing a semiconductor device of the present invention. FIG. 6 illustrates one embodiment of a light-emitting device to which the present invention is applied. FIG. 6 illustrates a circuit included in a light-emitting device to which the present invention is applied. FIG. 6 is a top view illustrating one embodiment of a light-emitting device to which the present invention is applied. 8A and 8B illustrate one embodiment of a frame operation of a light-emitting device to which the present invention is applied. 6A and 6B illustrate one embodiment of an electronic device to which the present invention is applied. The figure explaining the experiment investigated about the effect of this invention. The figure which shows the image obtained by observing the sample to which this invention is applied with a scanning electron microscope.

Explanation of symbols

301 conductive layer 302 insulating layer 303 mask 100 substrate 101a insulating layer 101b insulating layer 102 semiconductor layer 103 semiconductor layer 104 semiconductor layer 105 semiconductor layer 106 semiconductor layer 107 gate insulating layer 108 first conductive layer 109 second conductive layer 110a mask 110b Mask 110c Mask 110d Mask 110e Mask 110f Mask 111 Second conductive layer 112 Second conductive layer 113 Second conductive layer 114 Second conductive layer 115 Second conductive layer 116 Second conductive layer 117 Electrode 118 Electrode 121 1st conductive layer 122 1st conductive layer 123 1st conductive layer 124 1st conductive layer 125 1st conductive layer 126 1st conductive layer 127 Electrode 128 Electrode 129 Electrode 130 Connection part 131 2nd conductive layer 132 Second conductive layer 133 Second conductive layer 134 Second conductive layer 135 Second conductive layer 136 Second conductive layer 140a First n-type impurity region 140b First n-type impurity region 141a First n-type impurity region 141b First n-type impurity region 142a First n-type impurity Region 142b First n-type impurity region 142c First n-type impurity region 143a First n-type impurity region 143b First n-type impurity region 144a Second n-type impurity region 144b Second n-type impurity region 147a Second n-type impurity region 147b Second n-type impurity region 147c Second n-type impurity region 145a Third n-type impurity region 145b Third n-type impurity region 146 Region 148a Third n-type impurity region 148b Third n-type impurity region 148c Third n-type impurity region 148d Third n-type impurity region 148a Third n-type impurity region 153a Mask 153b Mask 153c Mask 153d Mask 155a Mask 155b Mask 156 Wiring 160a First p-type impurity region 160b First p-type impurity region 161a Second p-type impurity region 161b Second p-type impurity region 163a First p-type impurity Region 163b First p-type impurity region 164a Second p-type impurity region 164b Second p-type impurity region 167 First insulating layer 168 Second insulating layer 169a Connection portion 169b Connection portion 170a Connection portion 170b Connection portion 171a Connection portion 171b Connection portion 172a Connection portion 172b Connection portion 173 Transistor 174 Transistor 175 Transistor 176 Transistor 178 Connection portion 179a Wire 179b Wire 180 Insulating layer 181 Insulating layer 182 Opening portion 183 Opening portion 184 Opening portion 185 Electrode 186 Partition wall layer 188 Light layer 189 electrode 191 protective layer 192 sealing material 195 substrate 194 flexible printed circuit 202 external connection region 203 wiring region 204 driver circuit region 206 pixel area 6500 substrate 6503 FPC
6504 Printed Wiring Board (PWB)
6511 Pixel portion 6512 Source signal line drive circuit 6513 Write gate signal line drive circuit 6514 Erase gate signal line drive circuit 901 Transistor 902 Transistor 903 Light emitting element 911 Gate signal line 912 Source signal line 913 Write gate signal line drive circuit 914 Erase gate signal line drive circuit 915 Source signal line drive circuit 916 Power supply 917 Current supply line 918 Switch 919 Switch 920 Switch 1001 Transistor 1002 Transistor 1003 Gate signal line 1004 Source signal line 1005 Current supply line 1006 Electrode 501 Subframe 502 Subframe 503 subframe 504 subframe 501a writing period 502a writing period 503a writing period 504a writing period 501b holding period 502b holding 503b Holding period 504b Holding period 504c Erasing period 504d Non-light emitting period 5521 Main body 5522 Housing 5523 Display section 5524 Keyboard 5551 Display section 5552 Main body 5553 Antenna 5554 Audio output section 5555 Audio input section 5556 Operation switch 5531 Display section 5532 Housing 5533 Speaker 701 Substrate 702 Conductive layer 703 Insulating layer 704 Mask 1901 Dotted line 1902 Insulating layer 1903 Resist 1904 Insulating layer 1905 Wiring

Claims (6)

A method for manufacturing a semiconductor device having a pixel region and a driver circuit region,
Forming an insulating layer containing silicon oxide on the first conductive layer included in the pixel region and the second conductive layer included in the drive circuit region;
Forming an insulating layer containing siloxane on the insulating layer containing silicon oxide ;
The insulating layer containing siloxane is etched using hydrogen bromide gas and chlorine gas , and the insulating layer containing silicon oxide is etched using hydrogen bromide gas and carbon tetrafluoride gas. Forming a first opening exposing a part of the conductive layer and a second opening exposing a part of the second conductive layer;
A method for manufacturing a semiconductor device, wherein the shape of the first opening and the shape of the second opening are different . A method for manufacturing a semiconductor device having a pixel region and an external connection region,
Forming an insulating layer containing silicon oxide on the first conductive layer included in the pixel region and the second conductive layer included in the external connection region;
Forming an insulating layer containing siloxane on the insulating layer containing silicon oxide;
The insulating layer containing siloxane is etched using hydrogen bromide gas and chlorine gas, and the insulating layer containing silicon oxide is etched using hydrogen bromide gas and carbon tetrafluoride gas. Forming a first opening exposing a part of the conductive layer and a second opening exposing a part of the second conductive layer;
The shape of the first opening is different from the shape of the second opening
A method for manufacturing a semiconductor device. In claim 1 or claim 2,
The area of the first opening is smaller than the area of the second opening
A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device having a pixel region, a driver circuit region, and an external connection region,
Forming an insulating layer containing silicon oxide on the first conductive layer included in the pixel region, the second conductive layer included in the drive circuit region, and the third conductive layer included in the external connection region;
Forming an insulating layer containing siloxane on the insulating layer containing silicon oxide;
The insulating layer containing siloxane is etched using hydrogen bromide gas and chlorine gas, and the insulating layer containing silicon oxide is etched using hydrogen bromide gas and carbon tetrafluoride gas. A first opening exposing a part of the conductive layer, a second opening exposing a part of the second conductive layer, and a third opening exposing a part of the third conductive layer. Form the
The shape of the first opening, the shape of the second opening, and the shape of the third opening are different from each other.
A method for manufacturing a semiconductor device. In claim 4,
The area of the first opening is smaller than the areas of the second opening and the third opening.
A method for manufacturing a semiconductor device. In claim 4 or claim 5,
The area of the second opening is larger than the area of the third opening
A method for manufacturing a semiconductor device.