JP4852524B2 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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JP4852524B2
JP4852524B2 JP2007336586A JP2007336586A JP4852524B2 JP 4852524 B2 JP4852524 B2 JP 4852524B2 JP 2007336586 A JP2007336586 A JP 2007336586A JP 2007336586 A JP2007336586 A JP 2007336586A JP 4852524 B2 JP4852524 B2 JP 4852524B2
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circuit
power supply
signal
input
circuit block
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JP2008091030A (en
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清男 伊藤
陽治 出井
真志 堀口
一彦 梶谷
靖 永島
浩正 野田
健 阪田
正和 青木
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エルピーダメモリ株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of realizing low power consumption while securing an operation margin. <P>SOLUTION: The semiconductor integrated circuit device includes a plurality of circuit blocks having power supply control elements. Two or more commands are successively entered from an external terminal, and an circuit block operated for each command is decided. During the operation of a first circuit block operated based on a first command, the power of a second block operated based on a second command is activated. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a circuit connection verification method for a semiconductor integrated circuit device, and relates to a circuit for a digital integrated circuit device such as a dynamic RAM (Random Access Memory) composed mainly of a CMOS circuit composed of a MOSFET having a low threshold voltage. The present invention relates to a technology that is effective for use in a connection verification method.

  As the MOSFET is miniaturized, the breakdown voltage decreases. For this reason, it is necessary to lower the operating voltage in a circuit constituted by miniaturized MOSFETs. In this case, since the gate voltage supplied to the gate is also lowered, it is necessary to lower the threshold voltage so that a desired current flows even with the lowered gate voltage. However, if the threshold voltage is set low, the leakage current (hereinafter referred to as subthreshold leakage current) that flows when the gate-source voltage is made equal and turned off increases exponentially, However, the current consumption when inactive increases.

  As an example of a circuit for reducing such a subthreshold leakage current, there is JP-A-6-237164. The method of reducing the leakage current in this circuit will be described by taking a CMOS inverter circuit as an example when the input during non-operation is at a high level and the output is determined at a low level. The MOSFET is off and the N-channel MOSFET is on. The leak current generated in the CMOS inverter circuit in this case is determined by the subthreshold leak current of the P-channel MOSFET in the off state.

Therefore, a P-channel power switch MOSFET is provided between the operating voltage node to which the source of the P-channel MOSFET of the CMOS inverter circuit is connected and the power line, and the power switch MOSFET in the non-operating state is turned off. It is a state. In this way, the potential of the internal power supply line in the floating state decreases due to the subthreshold leakage current, and when it decreases to some extent, a reverse bias voltage is applied between the gate and source of the P-channel MOSFET constituting the CMOS circuit. Subthreshold leakage current can be substantially eliminated.
JP-A-6-237164

  The inventor of the present application has noticed that as the circuit scale of the CMOS integrated circuit increases, the parasitic capacitance of the internal power supply line increases and a large peak current flows due to the ON state of the switch MOSFET. This peak current is composed of a current necessary for charging up the large gate capacitance of the switch MOSFET and a current for charging up the parasitic capacitance of the internal power supply line through the source-drain path of the switch MOSFET. As the CMOS circuit scale increases, it increases. Also, the application of a method for reducing the subthreshold leakage current to the dynamic RAM was examined. In this case, it has been found that various solutions must be made in order to effectively reduce the subthreshold leakage current without sacrificing the operation speed of the dynamic RAM.

  When the dynamic RAM is in the standby state, the internal power switch MOSFET is turned off to reduce the subthreshold leakage current. When the switch MOSFET is turned on during memory access, the MOSFET is turned on from the off state. When the control signal for making the state rise, or when the power supply node of the internal circuit is charged up by the ON state of the MOSFET, the large pulsed current flows. Such a pulsed current increases the peak current value of the dynamic RAM, and when the system is mounted, the current capacity of the power supply device must be made large corresponding to the peak value. In the first place, as described above, the increase in circuit functions and circuit scale of semiconductor integrated circuit devices accompanying the miniaturization of elements and the reduction of power supply voltage are mainly toward miniaturization of systems such as portable electronic devices. It is expected to use a battery as a power source. However, the increase in the peak current as described above becomes a serious problem when viewed from a power supply device of a system that requires such downsizing. Also in the semiconductor integrated circuit device, with the generation of the peak current as described above, a large noise is generated in the power supply line and the operation margin is deteriorated.

  An object of the present invention is to provide a semiconductor integrated circuit device that achieves low power consumption while ensuring an operation margin. Another object of the present invention is to provide a semiconductor integrated circuit device realizing high integration, low voltage and low power consumption without sacrificing the operation speed. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, it has a plurality of circuit blocks having power supply control elements, and two or more instructions are continuously input from the external terminal, and a circuit block determined for each instruction operates. While the first instruction is input and the first circuit block determined by the first instruction is operating, the power supply of the second circuit block determined by the second instruction is activated to prepare for operation.

  Among the internal circuits composed of CMOS circuits, the first circuit whose output signal level is low when in the non-operating state is the first internal power supply line corresponding to the power supply line to which the power supply voltage supplied from the external terminal is transmitted. A second circuit connected to a ground line to which a ground potential supplied from an external terminal is transmitted and whose output signal is at a high level is connected to the power line and a second internal power line corresponding to the semiconductor integrated circuit. In the circuit device, a potential different from the power supply line and the ground line is set for each of the first and second internal power supply lines in the computer simulator, and the potential of the output node of each circuit is calculated. By detecting that the voltage corresponds to the potential of the first and second internal power supply lines and outputting the node information, it is possible to easily find the erroneous connection location. .

  1 and 2 are block diagrams showing one embodiment of a dynamic RAM to which the present invention is applied. FIG. 1 mainly shows an input section, an X system circuit, and an array block, and FIG. 2 shows a Y system, a write circuit, and an output buffer. In the figure, in order to facilitate understanding of the present invention, the signal transmission path is not faithfully supported as in a normal circuit block, and is mainly drawn from the viewpoint of supplying an operating voltage to each circuit block. It is.

  The dynamic RAM of this embodiment is roughly divided into a circuit that is always in a power supply state, such as an input unit and an output (circuit) unit such as an output buffer, and the like, and other internal circuits. Therefore, each circuit constituting the input unit, an output circuit typified by an output buffer, and a circuit that requires a memory operation among the internal circuits are provided with a power supply line through which a power supply voltage supplied from an external terminal is transmitted. It is connected to VCC (hereinafter also referred to as a main power line or main power line) VSS and a ground line (hereinafter also referred to as a main ground line or main ground line) to which a ground potential is transmitted.

  On the other hand, in order to reduce the subthreshold leakage current, the internal circuit forms a low-level output signal in the CMOS circuit in the non-operating state, in other words, in the standby state. The side that is connected to the sub power line or the sub voltage line (first internal power line) and the one that forms the high level output signal is connected to the sub ground line (second internal power line).

  In this embodiment, for the purpose of reducing the peak current when the voltage is supplied to the internal power supply line as described above without sacrificing the substantial operation speed, the internal circuit is largely divided into an X system circuit. Divided into Y-system circuits. The reason is that each operation timing is different. The X system circuit is not particularly limited, but for the purpose of more effectively reducing the peak current, an X system circuit that forms a word line selection signal and an array block are provided in the array block. It is divided into two parts, ie, a part (circuit part) for forming a selection signal.

  Corresponding to the division of the internal blocks as described above, the sub power supply lines are divided as VCTX, VCTA, and VCTY, and the subground lines are divided as VSTX, VSTA, and VSTY. The sub power supply line is not particularly limited between VCTX and VCTA and the power supply line VCC. However, for the purpose of further reducing the peak current, a plurality of P channel type switch MOSFETs QP1, QP2 and QP3 are used. Each QP4 is provided in parallel form. A plurality of N-channel type switch MOSFETs QN1, QPN and QN3, QN4 are provided in parallel between the sub-ground lines VSTX, VSTA and the ground line (first main voltage line) VSS, although not particularly limited. It is done.

  These two divided P-channel and N-channel switch MOSFETs are supplied with control signals φXB, φX and φAB, φA, respectively. These control signals φXB, φX and φAB, φA are generated at different timings. The control signals φXB, φX are generated at a relatively early timing corresponding to each operation sequence, and the control signal φAB , ΦA is generated at a relatively late timing. As a result, the X-system circuit and the array block are shifted in the on-state timing of the switch MOSFETs. As a result, the current value of the peak current can be reduced.

  The control signal φXB is provided between the sub power supply line VCTX corresponding to the X system circuit and the power supply line (second main voltage wiring) VCC, and the gates of the P channel type switch MOSFETs QP1 and QP2 arranged in parallel. The control signal φXB is supplied to the MOSFET QP1 corresponding to the input side, and the delay signal through the delay circuit (control circuit) 17a is supplied to the MOSFET QP2 corresponding to the output side. Is done. In the figure, two switch MOSFETs QP1 and QP2 are exemplarily shown as representatives. However, the X system circuit includes an X predecoder 6, a mat selection circuit 7, an X address comparator 8 for performing redundant address comparison, and a mat control. It is composed of multi-stage logic circuits constituting the circuit 9 and the like.

  Sub power supply line VCTX for supplying an operating voltage to these logic circuits is extended along the circuit area in which it is formed. Therefore, the switch MOSFETs QP1 and QP2 are formed by arranging a number of MOSFETs in parallel between the sub power supply line VCTX and the power supply line VCC, and have a desired current supply capability by their combined conductance. . In other words, one switch MOSFET is configured with a relatively small size so that the current supply capability necessary for the operation of the X-system circuit is divided into a plurality of parts.

  The control signal φX is also supplied in common to the gates of the N-channel type switch MOSFETs QN1 and QN2 provided in parallel between the sub-ground line VSTX and the ground line VSS corresponding to the X system circuit as described above. Instead, the control signal φX is supplied to the MOSFET QN1 corresponding to the input side, and the delay signal through the delay circuit 17c is supplied to the MOSFET QN2 corresponding to the output side. Similarly to the MOSFETs QP1 and QP2, the switch MOSFETs QN1 and QN2 are configured by a plurality of MOSFETs arranged in parallel between the sub-ground line VSTX and the ground line VSS, and have a desired current capability due to their combined conductance. Have to have.

  Such division of the switch MOSFET provides the following advantages. One is that the switch MOSFETs are formed in a distributed manner between the power supply line VCC and the sub power supply line VCTX and between the subground line VSTX and the ground line VSS as described above. Can be increased. That is, this can be realized by appropriately providing a relatively small switch MOSFET in the space between the two wirings. Then, by operating these MOSFETs sequentially with a time difference like a domino effect, they can be driven directly by a relatively small inverter circuit constituting the delay circuits 7a and 7c, and the drive current supplied to the gate of the switch MOSFET is Dispersed and acts to suppress peak current.

  Similarly, the size of the switch MOSFET is reduced and the value of the current that flows when the switch MOSFET is turned on is also relatively small, and the switch MOSFETs are sequentially turned on with a time difference as in the case of the above-described dominoes, so that the X system This is because the current flowing in the internal circuit of the circuit is also dispersed in time to suppress the peak current. The order of the switch MOSFETs operated with the time difference is determined according to the signal transmission method, so that signal transmission can be efficiently performed with a small current as described later.

  P channel type switch MOSFETs QP3 and QP4 provided between the sub power line VCTA and the power line VCC provided corresponding to the array block, and an N channel type provided between the sub ground line VSTA and the ground line VSS. The switch MOSFETs QN3 and QN4 are also configured in the same manner as described above, and are sequentially switch-controlled like a domino effect by the delayed control signals φAB and φA and the delay signal formed by the delay circuits 17b and 17d.

  The array block includes an X decoder 12, a memory array 15, a word driver 13, and a sense amplifier 14. A combination of the memory array 15, the X decoder, and the sense amplifier 14 constitutes one memory mat, and a plurality of memory mats are provided as a whole. Therefore, the X decoder 15 corresponding to the memory mat selected by the mat control circuit is activated, the word line selection operation of the memory array 15 corresponding thereto is performed, and read to the bit line by the word line selection operation. The stored information is amplified by the sense amplifier 14.

  In this embodiment, in order to secure a relatively large current necessary for the amplification operation of the sense amplifier, the common source switch circuit 16 for forming the operation signal of the sense amplifier has the sub power supply line VCTA and the sub ground line as described above. It is not connected to VSTA, but is directly connected to power supply line VCC and ground line VSS. The same applies to an output buffer that requires a large output current to flow.

  A sub power supply line VCTY and a subground line VSTY are provided corresponding to the Y system and the write circuit, and there is no particular limitation between the sub power supply line VCTY and the power supply line VCC, but one P-channel type switch MOSFET QP5. Although there is no particular limitation between the sub-ground line VSTY and the ground line VSS, one N-channel type switch MOSFET QN5 is provided. Each of these switch MOSFETs QP5 and QN5 has a relatively large size so that a current required for the operation of the Y system and the write circuit flows.

  However, in order to suppress the peak current for driving and the peak current when it is turned on, the control signals φYB and φY are set so that their rises are gradual. The simplest method is to form the control signals φYB and φY with a drive circuit such as an inverter circuit having a small conductance so that the time constant between the relatively large size of the switch MOSFETs QP5 and QN5 is large. To do.

  By adopting such a configuration, the current required to change the gate voltage supplied to the gates of MOSFETs QP5 and QN5 is reduced, and each MOSFET QP5 and QN5 is gradually turned on so that the sub power supply line VCTY In addition, the peak value of the current supplied to the sub-ground line VSTY can be suppressed. When applied to a Y-system circuit in this way, there is a relatively long time from when the row address strobe signal RASB is set to the low level and the memory access is started until it operates, so that the power switch MOSFET Can be set to have a current supply capability necessary for the above operation after a lapse of a desired time with a simple configuration such as driving an inverter circuit with a small current supply capability.

  In the Y system and the write circuit, the address signal change detection circuit ATD detects a change in the Y address signal, activates the equalizing signal generation circuit 26 and the main amplifier control circuit, and performs equalization and amplification operation of the input node of the main amplifier. Take control. These circuit blocks YB1 are not connected to the sub power supply line VCTY or the subground line VSTY as described above, but are directly connected to the power supply line VCC and the ground line VSS in order to stabilize the operation.

  The other circuit blocks of the Y system and the write circuit are connected to the sub power line VCTY and the subground line VSTY. Among these circuits, 28 is a Y predecoder, 33 is a Y decoder, 29 is a Y address comparator for performing redundant address comparison, 30 is a main amplifier, 31 is a write buffer control circuit, 32 is a write buffer, 34 is a vendor test circuit, and 35 is an output buffer control circuit.

  An input (circuit) unit that receives an input signal input from the external terminal is steadily given an operating voltage by the power supply line VCC and the ground line VSS in order to ensure responsiveness to the input signal from the external terminal. In addition, the output buffer that forms the output signal is constantly supplied with an operating voltage by the power supply line VCC and the ground line VSS in the same manner as described above in order to stably output the output signal.

  The input unit includes a RAS input buffer 1 as an X system, a clock generation circuit 2 that receives an output signal of the input buffer 1 and forms a RAS clock signal, an address buffer 3 that receives an address signal, and the address signal as the RAS system Are provided with an X address latch circuit 4 that receives the clock signal R1B and a CBR counter 5 that generates an address signal for a refresh operation.

  As a Y system, a CAS input buffer 18, a clock generation circuit 19 that receives a signal output from the input buffer 18 and forms a CAS system clock signal, and a Y address signal input through the address buffer 3 is used as the CAS system clock signal. A Y address latch circuit 20 is provided. In addition, an output enable input buffer 22, a write enable input buffer 24, and a data input buffer 24 are provided in the input unit.

  FIG. 3 shows a circuit diagram of an embodiment of an X-system address input unit. The address signal IAYa is a refresh address signal formed by the counter 5 of FIG. 1, and the address signal RAaB is an X-system address signal supplied from an external terminal. Corresponding ones of these two address signals are supplied to the inputs of the clocked inverter circuits CN1 and CN2. The refresh control signal IRF is set to a high level during a refresh operation to place the clocked inverter circuit CN1 in an operating state and the clocked inverter circuit CN2 in an output high impedance state to capture the refresh address signal IAYa. When the refresh signal IRF is at the low level, the clocked inverter circuit CN1 is set to the output high impedance state, the clocked inverter circuit CN2 is set to the operating state, and the row-related address signal RAaB supplied from the external terminal is captured.

  The outputs of the two clocked inverter circuits CN1 and CN2 are shared and transmitted to the through latch circuit through the inverter circuit. The through latch circuit includes an input clocked inverter circuit CN3, an inverter circuit IV3, and a clocked inverter circuit CN4 for feedback. The timing signal XAE0 is a row-related timing signal and causes the through latch circuit to perform a latch operation. That is, the input clocked inverter circuit CN3 is set in the operating state and the feedback clocked inverter circuit CN4 is set in the output high impedance state in accordance with the low level of the timing signal XAE0, so that the address signal input from the external terminal The RAab or refresh address signal IAYa is taken in through the input clocked inverter circuit CN3.

  When the timing signal XAE0 is changed from the low level to the high level, the input clocked inverter circuit CN3 is set to the output high impedance state, and instead the feedback clocked inverter circuit CN4 is set to the operating state. The output signal of IV3 is fed back to the input side, and the fetched address signal is latched. Output signals of the through latch circuit are output as complementary internal address signals BXaB and BXaT through a NOR gate circuit and an inverter circuit. The NOR gate circuit outputs complementary internal address signals BXaB and BXaT corresponding to the latched address signal when the timing signal XAE0 is at a high level. In other words, in the standby state in which the timing signal XAE0 is set to the low level, the internal address signals BXaB and BXaT are both fixed to the high level, and the signals of the subsequent logic stages are irrelevant to the previous memory access. Means that the signal level is fixed to a predetermined level.

  FIG. 4 shows a circuit diagram of an embodiment of a predecoder that receives the internal address signal. The complementary internal address signals BX2Bi, BX2Ti to BX4Bi, BX4Ti fetched from the address input section as described above are fetched through a NAND gate circuit whose gate is controlled by a test control signal TASWTD. By combining these three bits of complementary internal address signals BX2Bi, BX2Ti to BX4Bi, BX4Ti, eight predecode outputs AX20Bi to AX27Bi are formed by the NAND gate circuit.

  The predecode output is output through two inverter circuits connected in series as output buffers. In each of the above signals, T represents non-inversion (true), and B represents inversion (bar). The test control signal TASWTD is not directly related to the present invention and will not be described. However, when it is set to the high level, the gate of the NAND gate circuit is closed and input to each NAND gate circuit constituting the predecoder. All the input signals are set to the high level regardless of the address signals BX2Bi, BX2Ti to BX4Bi, BX4Ti.

  When the dynamic RAM is in the standby state, all the internal address signals BXaB and BXaT are both fixed at the high level as described above, so that the output signal of the NAND gate circuit of the input unit is set to the low level. The NAND gate circuit constituting the decoder fixes the output signal to the high level because the input signal is set to the low level. In the two CMOS inverter circuits for output, the high level is supplied to the input of the previous stage, so that the output signal is set to the low level, and the circuit of the subsequent stage sets the output signal to the high level.

  As described above, since the signal levels of the internal logic stages are fixed as described above in the non-operating state, in order to reduce the subthreshold leakage current as described above, the first logic stages are sequentially arranged according to the signal transmission direction. The NAND gate circuit in the first stage is connected to the ground line VSS to form a low level output signal, but the power supply side is connected to the sub power supply line VCTX. In the non-operating state, the sub power supply line VCTX is turned off because the P-channel MOSFETs QP1, QP2, etc. as shown in FIG. 1 which are connected to the power supply line VCC are turned off. This acts to reduce the subthreshold leakage current flowing in the P-channel MOSFET.

  As will be described later, the P-channel MOSFET and the N-channel MOSFET of the CMOS circuit constituting the logic stage constitute the power switch while the threshold voltage is reduced for high-speed operation. The switch MOSFETs QP1, QP2, etc. are set to have relatively large threshold voltages so that the subthreshold leakage current does not substantially flow when the switch MOSFETs are in the off state.

  The second-stage NAND gate circuit is connected to the power supply line VCC to form a high-level output signal corresponding to the low-level input signal transmitted from the output of the first-stage NAND gate circuit. The side is connected to the sub-ground line VSTX. The sub-ground line VSTX is turned off when the N-channel MOSFETs QN1, QN2, etc. as shown in FIG. 1 which are connected to the ground line VSS in the non-operating state are turned off. This acts to reduce the subthreshold leakage current flowing in the N-channel MOSFET. Similarly to the above, the switch MOSFETs QN1, QN2, etc. constituting the power switch are set to have a relatively large threshold voltage so that the subthreshold leakage current does not substantially flow when it is in the OFF state.

  Hereinafter, the third-stage CMOS inverter circuit is operated by VCTX and VSS in the same manner as the first-stage NAND gate circuit, and the fourth-stage CMOS inverter circuit is the same as the second-stage NAND gate circuit. Similarly, by operating with VCC and VSTX, the subthreshold leakage current in the non-operating state can be reduced.

  FIG. 5 shows a specific circuit diagram of an embodiment of the X decoder and a latch circuit and a word driver provided therein. Although not particularly limited, AX20 to 27 are signals formed by predecoding 3-bit address signals A2 to A4 by the predecoder as described above, and AX50 to 57 are 3-bit address signals A5. A signal formed by predecoding .about.A7 by a predecoder similar to the above. Of the predecode signals AX20-A27, one MOSFET Q3 supplied to the gate and one of the predecode signals AX50-57 MOSFETQ4 supplied to the gate are directly connected to form the X decoder. And a selection timing signal XDGB is supplied.

  This X decoder is composed of a dynamic logic circuit, and is composed of a P-channel precharge MOSFET Q1 that is switch-controlled by a precharge signal XDP, and the MOSFETs Q3 and Q4 constituting the logic block connected in series. . That is, a select / non-select decode signal is formed depending on whether the node precharged to the high level by the precharge MOSFET Q1 is discharged by the low level of the timing signal XDGB through the MOSFETs Q2, Q3 and Q4.

  The latch circuit includes an inverter circuit IV1 and a P-channel MOSFET Q2 provided between the input of the inverter circuit IV1 and the power supply terminal VCC and controlled by the output signal XDGE of the inverter circuit IV1. The MOSFET Q2 constitutes a positive feedback circuit in response to a low level non-selection level. When the MOSFETs Q3 and Q4 are turned off, the level of the node is inverted by a leak current, and the non-selected word Prevent lines from being selected.

  The output signal XDGE of the inverter circuit IV1 is a selection signal corresponding to the four word lines WL0 to WL3, although not particularly limited. One of the four word lines WL0 to WL3 is decoded, and the address signals A0 and A1 of the lower bits are decoded and one of the timings specified by the four word line selection timing signals X0MB to X3MB added with the selection timing signal. A word line is selected.

  That is, when the output signal XDGE of the latch circuit is at the high level selection level, the MOSFET Q5 is in the on state, and when the one word line selection timing signal X3MB changes from the high level to the low level, it operates with the boost voltage VCH. A low level input signal is supplied to the word driver composed of the P channel type MOSFET Q6 and the N channel type MOSFET Q7, and the word line WL3 connected to the output terminal is raised from the low level to the high level corresponding to the boost voltage VCH.

  When the output signal XDGE of the latch circuit is at the high level selection level, the MOSFET Q5 and other MOSFETs are also turned on, but the word line selection timing signals X0MB to X2MB remain at the high level. The N-channel MOSFET of the word driver is turned on, and the word lines WL0 to WL2 are left in the low level non-selected state. The P-channel type MOSFET Q8 is a non-selection level latching MOSFET, and is turned on when the word line WL3 is at the non-selection low level. The input terminal of the word driver is set to the boost voltage VCH, and the P-channel type MOSFET Q6. Is turned off. The P-channel MOSFET Q9 is a precharge MOSFET, and is turned on by the low level of the precharge signal WPH to precharge the input terminal of the word driver to VCH.

  When the output signal XDGE of the latch circuit is at the low level non-selection level, the MOSFET represented by the MOSFET Q5 is in the OFF state. Therefore, even if any one of the word line selection timing signals X0MB to X3MB changes from the high level to the low level, the P channel MOSFET Q8 is not responded to the low level of the word lines WL0 to WL3 corresponding to the precharge level. Is turned on, and a latch that feeds back a high level corresponding to VCH is applied to the input terminal of the word driver, and the non-selected state of the word lines WL0 to WL3 and the like is maintained.

  As in the circuit of this embodiment, a word driver such as MOSFETs Q6 to Q9 operating at a boosted voltage VCH corresponding to the selection level of the word line has a large signal amplitude input thereto, so that the threshold voltage is supplied from the power supply. The switch MOSFETs QP1 and QN1 are made relatively large. Therefore, since the subthreshold leakage current in the off state can be substantially eliminated, it is directly connected to the ground line VSS in order to stabilize the selection / non-selection level of the word line. However, the inverter circuit IV1 has a signal amplitude as small as the predecoder, and when it is not selected, the input signal is fixed to a high level from the precharge signal XDP and a low level output may be formed. It may be connected to the power supply line VCTA.

The redundant word line RWL0 is also provided with the same word driver, latching MOSFET and precharge MOSFET as described above. The redundant word line RWL0 is a redundant word formed by a redundant circuit including the timing signal XDGB, a fuse circuit for storing a defective address (not shown), and an address comparing circuit for comparing the defective address with the inputted X address. Selection is performed in synchronization with the line selection signal XR0B. At this time, the predecoders AX20 to 27 and AX50 to 57 or the word line selection timing signals X0MB to X3MB, which are normal circuits, are set to the non-selection level by the defective address comparison coincidence signal, so that the selection operation for the defective word line is performed. Absent.

  Although not particularly limited, the memory array of this embodiment is divided into a plurality of memory mats as will be described later. A sense amplifier SA, a precharge circuit PC, and input / output lines are provided on both sides of the memory mat MAT. Although not particularly limited, in order to match the pitch of the complementary bit lines arranged orthogonal to the word lines WL0 to WL3 and the like and the pitch of the sense amplifier and the precharge circuit, the odd-numbered complementary bit lines and the even-numbered bit lines are matched. The sense amplifiers corresponding to the complementary bit lines are distributed to the left and right. With such an arrangement of the sense amplifiers SA, one sense amplifier can be arranged at a pitch twice that of the complementary bit line.

  In this embodiment, although not particularly limited, the sense amplifier is a shared sense amplifier system, and the signals SHL and SHR are shared selection signals. In the figure, the left and right sides are reversed at first glance. However, when the sense amplifier SA is viewed from the center, the memory mat shown in the figure is arranged on the left side when viewed from the right sense amplifier SA. Since the signal is supplied and the memory mat shown in the figure is arranged on the right side when viewed from the left sense amplifier SA, a selection signal such as SHR is supplied.

  FIG. 6 shows a circuit diagram of an embodiment of the mat control circuit. By decoding the upper address signal, mat selection signals MS000, MS001, MS002, etc. are formed. The memory mat MAT shown in FIG. 4 is selected by MS001. The mat selection signal MS001 is supplied to four NAND gate circuits via two columnar inverter circuits. These four NAND gate circuits are supplied with timing signals x0 to x3, which are obtained by decoding the address signals A0 and A1 and a word line selection timing signal, via an inverter circuit. . As a result, the word line selection timing signals X0MB to A3MB are formed from the outputs of the NAND gate circuits. This means that the predecode signals AX20 to 27, AX50 to 57 and the timing signals x0 to x3 are commonly used for the plurality of memory mats.

  By combining the mat selection signal MS001 with the X-system timing signals R1 and R2, the precharge signals XDP and WPH and the row decoder operation timing signal XDGB are formed. Since the precharge signal WPH is a signal supplied to the gate of the P-channel type MOSFET that is operated by the boosted voltage VCH as described above, an inverter circuit that is level-converted by the level conversion circuit and operates at the boosted voltage VCH. Is output via. The mat selection signals MS000 and MS002 having a signal amplitude such as the power supply voltage VCC are level-converted to a signal amplitude corresponding to the boost voltage VCH by the level conversion circuit, and the shared selection signals SHR and SHL are formed.

  Also in this mat control circuit, as described above, the input signals R1, R2, MS001 to MS002, etc. are fixed at a low level during non-operation and form a high level output signal. The sub ground line VCTX is operated. On the other hand, the second-stage CMOS inverter circuit receives a high level input signal and forms a low level output signal on the basis of such an input signal. Therefore, the sub power supply line VCTX and the ground line VSS are used. Connected to. Hereinafter, similarly, the third-stage NAND gate circuit is operated by the power supply line VCC and the sub-ground line VCTX. Since the signals x0 to x3 are fixed at a high level when not in operation, the signals are operated by VCTX and VSS according to the above method, and the NAND gate circuit receiving the output signal is operated by VCC and VSTX.

  FIG. 7 is a timing chart for explaining an example of the operation of the dynamic RAM shown in FIGS. The row address strobe signal RASB changes from the high level to the low level, and the memory access is started. When the output signal R0B of the RAS input buffer 1 changes from the high level to the low level, the RAS clock generation circuit 2 receives this and changes the representative row related timing signal R1B from the high level to the low level. Due to the low level change of the timing signal R1B, the address signal Ai input from the address buffer 3 is taken into the X address latch circuit 4 as an X address signal.

  Due to the low level of the timing signal R0B, the control signal φX of the power switch changes from the low level to the high level, and φXB changes from the high level to the low level. As a result, supply of the power supply voltage VCC to the sub power supply line VCTX is started by the on state of the switch MOSFET QP1, and the switch MOSFET QN1 is turned on to start the supply of the ground potential VSS to the sub ground line VSTX. That is, the voltage supply operation to the sub power supply line VCTX and the sub ground line VSTX is performed simultaneously with the operations of the RAS clock generation circuit 2 and the X address latch circuit 4.

  Therefore, when the internal address signal X0 is generated corresponding to the latch operation of the X address latch circuit 4, each of the predecoder 6, the mat select circuit 7 and the X address comparator 8 is at least in its input stage logic circuit. The power supply voltage VCC when the switch MOSFET QP1 is turned on and the ground potential VSS when the switch MOSFET QN1 is turned on are almost supplied to the sub-ground line VSTX. Form. Corresponding to the signal transmission in the logic stage in the predecoder 6 and the mat select circuit 7, the sub power supply line VCTX and the sub ground line VSTX are operated by switch MOSFETs that operate sequentially in the signal transmission direction as if dominoing. Are sequentially supplied with potentials necessary for operation, and predecode signals X1 and X2 and a mat selection signal X3 are formed.

  The control signals φA and φAB are changed to a high level and a low level after the control signals φX and φXB, respectively, and supply of the power supply voltage VCC and the ground potential VSS to the sub power supply line VCTA and the subground line VSTA of the array block is started. To do. At the timing when the predecode signal X1 formed by the X-system circuit as described above and the output signal X4 of the mat control circuit 9 are output, there is a time margin, so the sub power supply line VCTA and the subground line of the array block. Each VSTA is set to a desired potential.

  Thus, in the array block, one word line WORD is raised from the low level to the high level in response to the selection signal X5 formed by the X decoder 12. Thereafter, the common source switch 16 is turned on by the change of the activation signal S0 of the sense amplifier to the low level, and the common sources SP and SN of the sense amplifier are changed to the high level and the low level, respectively. The micro signal amplification operation is started after reading.

  The column address strobe signal CASB changes from the high level to the low level, and the Y-system address signal is taken in. In other words, when the output signal of the CAS input buffer 18 changes from the high level to the low level, the CAS clock generation circuit 19 receives the address signal Ai input from the address buffer 3 by generating a timing signal for taking in the address. It is taken into the Y address latch circuit 20 as a Y address signal.

  The address signal Y1 taken into the Y address latch circuit is supplied to the predecoder 28 and the Y address comparator 29, and Y0 is supplied to the address change detection circuit 25 to generate an address change detection signal C0. In response to this signal C0, the equalizing pulse generating circuit 26 generates an equalizing pulse C1 to equalize the input signal supplied to the input terminal of the main amplifier 30. In response to the signal C0 and the timing signal from the CAS clock generation circuit, the main amplifier control circuit 27 generates a main amplifier control signal C2.

  In response to the predecode signal Y2, the Y decoder 33 generates a Y selection signal. Therefore, the read signal D0 is transmitted to the input terminal of the main amplifier 30, and the amplified signal D1 is input to the output buffer 37 through the data selector. As reported. The output buffer 37 is activated by the timing signal C3 from the data output buffer control circuit 36 and sends out output data DATA.

  In the write mode, the write clock generation circuit 21 determines that the output signal of the write enable input buffer 23 is at low level, the write buffer 32 is activated, and the data input from the data input buffer 24 is selected by the Y selection. The signal is transmitted to the complementary bit line of the memory array selected by the signal.

  The control signals φY and φYB corresponding to the Y system and the write circuit are gradually changed to a high level and a low level at an appropriate timing during the X system selection operation. For this reason, the switch MOSFETs QP5 and QN5 provided in the sub power supply line VCTY and the subground line VSTY corresponding to the Y-system and the write circuit have a gentle output current in response to the gradual change in the gate voltage. The Y-system circuit is made to have a desired current supply capability at the timing when the operation starts.

  As described above, the sub power supply lines VCTX, VCTA, and VCTY divided into three and the sub ground lines VSTX, VSTA, and VSTY are substantially in a floating state when not in operation, and the subthreshold leakage in the logic circuit is performed. When the memory is accessed while the current is suppressed, the control signals φX and φXB, φA and φAB, and φY and φYB are sequentially generated. A drive current for changing the gate voltage of the switch MOSFET controlled by the control signals φX and φXB, φA and φAB, and φY and φYB, the sub power lines VCTX, VCTA, and VCTY, and the sub ground lines VSTX, Since the supply current for changing the voltages of VSTA and VSTY to a desired voltage also gradually increases with time, the generation of peak current can be suppressed and the operation speed of each circuit block can be substantially prevented. .

  8 and 9 are block diagrams showing an embodiment of a dynamic RAM to which the present invention is applied. FIG. 8 shows a memory array and its peripheral selection circuit, and FIG. 9 shows an input / output interface unit such as an address buffer and an input / output buffer, and a timing control circuit.

  In FIG. 8, a sense amplifier SA01 is provided between two memory mats MAT0 and MAT1. That is, the sense amplifier SA01 is a shared sense amplifier that is selectively used for the two memory mats MAT0 and MAT1. The input / output section of the sense amplifier SA01 is provided with a selection switch (not shown), and is connected to a complementary bit line (or sometimes referred to as a complementary data line or a complementary digit line) of the memory mat MAT0 or MAT1.

  The other memory mats MAT2, MAT3, MAT4, MAT5 and MAT6, MAT7 are also paired, and the sense amplifiers SA23, SA45 and SA67 are provided in common. A total of eight memory mats MAT0 to MAT7 and four sense amplifiers SA01 to SA67 as described above constitute one memory array MARY0. A Y decoder YDEC is provided for this memory array MARY0. A memory array MARY1 is provided symmetrically across the Y decoder YDEC. The memory array MARY1 has the same configuration as the memory array MARY0 although the internal configuration is omitted.

  In each of the memory mats MAT0 to MAT7, decoders XD0 to XD7 are provided. These decoders XD0 to XD7 decode the output signal AXi of the predecoder circuit XPD to form four word line selection signals. Word drivers WD0 to WD7 for forming word line selection signals are provided by the decoders XD0 to XD7 and output signals of mat control circuits MATCTRL01 to MATCTRL67 described below. This word driver includes a word driver corresponding to a spare word line for defect relief.

  A mat control circuit MATCTL01 is provided corresponding to the pair of memory mats MAT0 and MAT1. Similar mat control circuits MATCTRL23, MATCTRL45, and MATCTRL67 are provided for the other memory mats MAT2, MAT3 to MAT6, and MAT7. The mat control circuits MATCTRL01 to MATCTRL67 receive the mat selection signal MSi, the signal XE, the sense operation timing signal φSA, and the decoding signal of the low-order 2 bits address signal in one mat control circuit for the selected memory mat. A selection signal XiB or the like for selecting one of the four word lines is output.

  In addition, the mat control circuits MATCTRL01 to MATCTRL67 leave the bit line selection switch corresponding to one of the left and right memory mats corresponding to the selected memory mat, and correspond to the non-selected memory mat. A selection signal for turning off the bit line selection switch and a timing signal for starting the amplification operation of the sense amplifier are output. Further, at the time of standby in a refresh operation as described later, there is provided a function of controlling one or both of the sense amplifier and the bit line selection switch to bring the bit line into a floating state.

  When the defective word line is accessed, the selection signal XiB and the like are inhibited from being output by the low level of the signal XE, so that the defective word line selection operation is stopped. Instead, the selection signal XRiB on the redundant circuit side is formed, so that the spare word line is selected.

  In FIG. 9, the timing control circuit TG receives the row address strobe signal / RAS, the column address strobe signal / CAS, the write enable signal / WE, and the output enable signal / OE supplied from the external terminals, and determines the operation mode. Correspondingly, various timing signals necessary for the operation of the internal circuit are formed. In the figure, / is used to mean that the low level is the active level.

  Signals R1 and R3 are row-related internal timing signals and are used for a row-related selection operation as described later. The timing signal φXL is a signal that fetches and holds a row address, and is supplied to the row address buffer RAB. That is, the row address buffer RAB takes in the addresses input from the address terminals A0 to Ai by the timing signal φXL and holds them in the latch circuit.

  The timing signal φYL is a signal for fetching and holding the column address, and is supplied to the column address buffer CAB. That is, the column address buffer RAB takes in the addresses inputted from the address terminals A0 to Ai by the timing signal φYL and holds them in the latch circuit.

  The signal φREF is a signal generated in the refresh mode, and is supplied to the multiplexer AMX provided in the input portion of the row address buffer, and the refresh address formed by the refresh address counter circuit RFC in the refresh mode. Control to switch to signal. The refresh address counter circuit RFC counts the refresh step pulse φRC formed by the timing control circuit TG and generates a refresh address signal. In this embodiment, auto refresh and self refresh as will be described later are provided.

  The timing signal φX is a word line selection timing signal, which is supplied to the decoder XIB to form four word line selection timing signals XiB based on the decoded signal of the lower 2 bits of the address signal. The timing signal φY is a column selection timing signal and is supplied to the column predecoder YPD to output column selection signals AYix, AYjx, AYkx.

  The timing signal φW is a control signal for instructing a write operation, and the timing signal φR is a control signal for instructing a read operation. These timing signals φW and φR are supplied to the input / output circuit I / O, and during the write operation, the input buffer included in the input / output circuit I / O is activated to bring the output buffer into an output high impedance state. On the other hand, in the read operation, the output buffer is activated and the input buffer is set to the output high impedance state.

  The timing signal φMS is a signal for instructing a mat selection operation, is supplied to the row address buffer RAB, and the mat selection signal MSi is output in synchronization with this timing. Timing signal φSA is a signal for instructing the operation of the sense amplifier. Based on this timing signal φSA, in addition to the formation of an activation pulse for the sense amplifier, a control signal for the operation of completing the precharge of the complementary bit line and the operation of disconnecting the bit line on the non-selected memory mat side is formed. Also used for.

  In this embodiment, a row redundant circuit X-RDE is exemplarily shown as a representative. That is, the circuit X-RED includes a storage circuit that stores a defective address and an address comparison circuit. The stored defective address is compared with the internal address signal BXi output from the row address buffer RAB, and if they do not match, the signal XE is set to high level and the signal XEB is set to low level to validate the operation of the normal circuit. When the input internal address signal BXi matches the stored defective address, the signal XE is set to low level to inhibit the defective word line selection operation of the normal circuit, and the signal XEB is set to high level to provide one spare A selection signal XRiB for selecting a word line is output.

  Although not shown in FIG. 9, a circuit similar to the row circuit is also provided in the column system, and when a memory access to the defective bit line is detected thereby, the column decoder YD selects the defective bit line. Instead, a selection signal for selecting a spare bit line is formed.

  FIG. 10 is a circuit diagram showing the principal part of an embodiment of the memory array section of the dynamic RAM according to the present invention. In the drawing, four word lines of memory mat MAT0, two pairs of complementary bit lines, a sense amplifier and a precharge circuit related thereto are shown as representatives, and memory mat MAT1 is shown as a black box. Has been. Further, a circuit symbol is added as a representative to MOSFETs constituting each circuit corresponding to the pair of complementary bit lines BLL and / BLL.

  The dynamic memory cell includes an address selection MOSFET Qm and an information storage capacitor Cs. The gate of address selection MOSFET Qm is connected to word line WLi, the drain of MOSFET Qm is connected to bit line / BLL, and information storage capacitor Cs is connected to the source. The other electrode of the information storage capacitor Cs is made common to receive a plate voltage VPL.

  The bit lines BLL and / BLL are arranged in parallel as shown in the figure, and are appropriately crossed as necessary in order to balance the capacity of the bit lines. The complementary bit lines BLL and / BLL are connected to the input / output node of the sense amplifier by switch MOSFETs Q1 and Q2. The sense amplifier is composed of N-channel MOSFETs Q5 and Q6 and P-channel MOSFETs Q7 and Q8 whose gates and drains are cross-connected to form a latch. The sources of N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of P-channel MOSFETs Q7 and Q8 are connected to a common source line CSP. As exemplarily shown in the common source line CSP, a power switch MOSFET Q14 of a P-channel type MOSFET is provided. When the timing signal φSAP is set to a low level, the MOSFET Q14 is turned on, and the sense amplifier operates. Supply the necessary voltage. The common source line CSN corresponding to the N channel type MOSFETs Q5 and Q6 is provided with an N channel type MOSFET (not shown) and supplies the circuit ground potential at the operation timing of the line.

  At the input / output node of the sense amplifier, a precharge circuit comprising a MOSFET Q11 for short-circuiting a complementary bit line and switch MOSFETs Q9 and Q11 for supplying a half precharge voltage HVC to the complementary bit line is provided. The gates of these MOSFETs Q9 to Q11 are commonly supplied with a precharge signal PCB. MOSFETs Q12 and Q13 constitute a column switch that is switch-controlled by a column selection signal YS. In this embodiment, four pairs of bit lines can be selected by one column selection signal YS. Therefore, the column selection signal YS is provided at the input / output nodes of four sense amplifiers corresponding to the two pairs of bit lines exemplarily shown in the figure and the remaining two pairs of bit lines (not shown). Commonly supplied to the gates of the MOSFETs constituting the column switch, and the four pairs of bit lines and the four pairs of input / output lines I / O are connected via the switch MOSFETs.

  FIG. 11 is a sectional view of an element structure of one embodiment for explaining a dynamic RAM according to the present invention. In this embodiment, the element structure of the memory array portion and the peripheral portion as described above is exemplarily shown as a representative. The storage capacitor of the memory cell uses the second polysilicon layer SG as a storage node and is connected to one source and drain of the address selection MOSFET. The second polysilicon layer has a fin structure and is composed of a plate electrode made of the third polysilicon layer TG with a thin gate insulating film interposed therebetween. The gate of the address selection MOSFET is composed of a first polysilicon layer FG. The other source and drain of the address selection MOSFET are connected to the first metal wiring layer M1 such as aluminum with the FG, SG and TG interposed therebetween. This wiring layer M1 constitutes a bit line.

  Two N-channel MOSFETs are formed in the peripheral portion. The first wiring layer M1 is connected to the source and drain of the MOSFET by a contact LCNT. Alternatively, the first-layer polysilicon FG is connected by a contact FCNT. The first wiring layer M1 and the second wiring layer M2 are connected via a first through hole TH1, and the second wiring layer M2 and the third wiring layer M3 are connected to each other. Two through-holes TH2 are connected. When an input signal is supplied to the gate electrode of the MOSFET through the second wiring layer M2, it is dropped to the first wiring layer M1 as a dummy via the first through hole TH1 as described above. The first wiring layer M1 and the contact LCNT are connected to the first layer polysilicon FG as the gate electrode.

  The third wiring layer M3 that supplies the input signal is connected to the second wiring layer M2 through the second through hole TH2. For example, when an output signal is supplied to the next stage circuit, the first wiring layer M1 is connected to the second wiring layer M2 as a dummy via the first through hole TH1, and this wiring layer M2 is interposed and led to the third wiring layer M3 through the second through hole TH2.

  Since the complementary bit line is half precharged in the non-operating state, a half precharge voltage is applied as a reverse bias between the gate and the source, so that no subthreshold leakage current occurs in the address selection MOSFET. However, when the word line is not selected and the complementary bit line is set to VSS by the amplification operation of the sense amplifier, it is considered that the information charge stored at the high level is lost due to the subthreshold leakage current.

  If such a subthreshold leakage current in the address selection MOSFET is a problem, the channel length is increased and the threshold voltage is increased. Alternatively, a well region where such a memory cell is formed is separated and a negative substrate back bias voltage is supplied thereto to increase the effective threshold voltage. Thus, in order to isolate only the well region where the memory cell is formed and supply the substrate back bias voltage, the semiconductor substrate has a known triple well structure. In other words, the N-channel type MOSFET constituting the peripheral circuit such as the decoder needs to have a low threshold voltage as described above in order to increase the operation speed. Biased to ground potential VSS.

  When only one set of sub power supply line and sub ground line is provided in a large circuit block, it is necessary to provide a switch MOSFET having a large gate width so as to cover the current supply to the circuit block and to lower the on-resistance of the switch MOSFET. This is because the threshold voltage of the P-channel type MOSFET constituting the circuit block is equivalently increased when there is a voltage effect on the sub power supply line, and the decrease in speedup due to the use of the MOSFET having a low threshold voltage is offset. Because it will be done. This also applies to the relationship between the threshold voltage of the N-channel MOSFET and the on-resistance of the switch MOSFET provided on the sub-ground line.

  Therefore, in order to maintain the effect of speeding up the operation, it is necessary to suppress the voltage drop to a maximum of several tens of mV with respect to the average operating current of the circuit block. For example, in the example of the dynamic RAM of the above embodiment, a switch MOSFET having a gate width of 5000 to 20000 μm is required. As a result, when the switch MOSFET is turned on, it is necessary to charge and discharge a gate capacitance having a large gate width.

  In order to reduce current consumption during non-operation of the circuit as a whole, it is desirable to use sub power supply lines and sub ground lines in as many circuit blocks as possible. However, for this purpose, it is necessary to turn on the power switch MOSFET as described above at the earliest possible timing after the input of the signal RASB. For example, the total gate width of the MOSFETs connected to the power supply line VCC and the ground line VSS at the input unit is about 10000 μm, whereas the X prerecorder and the mat selection circuit are connected to the sub power supply line and the subground line. The total gate width of the MOSFETs is about 15000 μm, and whether or not to connect the sub power line or sub ground line to the X predecoder and the mat selection circuit depends on the leakage current during non-operation (when inactive). It will change to half. Therefore, it is important to turn on the switch MOSFET before the X predecoder and the mat selection circuit are activated (for example, around 5 n seconds after the RASB input).

  Since it is necessary to charge and discharge the gate capacitance as described above in a short time, the sub-power supply line and the sub-ground line are combined into one set as a whole, and each of the P-channel type switch MOSFET and the N-channel type switch MOSFET When one switch is configured, a peak current as large as 0.5 to 1.0 A flows when the switch MOSFET is turned on. If such a large peak current is superimposed on the operating current of the internal circuit, it becomes a serious problem in terms of long-term reliability such as disconnection due to noise or concentrated current.

  In this embodiment, as described above, the sub power supply line VCT and the sub ground line VST are divided into three as described above, and the activation timing and the operation timing of the divided switch MOSFETs are also sequentially turned on. By providing such a time difference, the current concentration at the time of switch control of the switch MOSFET is dispersed over time. However, the sub power supply line VCT and the sub ground line VST can be shared by several blocks, respectively, and the peak current can be suppressed only by using a plurality of switch MOSFETs and setting the start timing difference. In that case, the layout becomes easier as compared with the case where the sub power line VCT and the sub ground line VST are finely divided between the blocks. Further, since the parasitic capacitances of the sub power supply line VCT and the subground line VST are also increased, there is an advantage that voltage fluctuations of the sub power supply line VCT and the subground line VST are reduced by an instantaneous large current.

  FIG. 12 is a block diagram for explaining an embodiment of the present invention. The figure shows a power supply line VCC, a sub power supply line VCT, a corresponding switch MOSFET and an inverter circuit constituting a delay circuit for forming a control signal thereof, and a circuit block to which an operating voltage is supplied thereby. Yes. Since the sub-ground line and the ground line of each circuit block of this embodiment and the corresponding switch MOSFET and the like are the same as those on the power supply voltage VCC side, they are omitted.

  In this embodiment, switch MOSFETs for connecting the sub power supply line VCT and the power supply line VCC are provided corresponding to the circuit blocks 1 to 4 as MOSFETs QP1 to QP4, respectively. Each of the switch MOSFETs QP1 to QP4 is set to a value such that the total gate width is within the allowable voltage fluctuation range of the sub power supply line VCT due to the on-resistance of the switch MOSFET. The control signal φ supplied to the gates of the switch MOSFETs QP1 to QP4 is transmitted signals sequentially delayed by the inverter circuits IV1 to IV7 corresponding to the signal propagation order sequentially transmitted to the circuit blocks 1 to 4.

  When the sub power supply line VCT is shared by the plurality of circuit blocks 1 to 4 as described above, for example, in the example of the dynamic RAM, the X system circuit, the array block, the Y system, and the write circuit are included in each circuit block. Corresponding. In this embodiment, the circuit block is supplied with an operating voltage from the switch MOSFET QP1 and performs a logic operation corresponding to the input signal IN. At this time, in the circuits far from the input signal side as in the other circuits 2 to 4, the voltage VCC supplied from the MOSFET QP1 is not sufficiently transmitted due to the distributed resistance of the sub power supply line VCT. Since a meaningful circuit operation is performed in response to the output signal of the circuit, no substantial problem occurs. That is, when a meaningful output signal corresponding to the input signal IN is transmitted to the circuit block 2 at the next stage, the switch MOSFET QP2 is turned on, and the voltage VCC for performing the corresponding logical operation is applied. In this manner, since the signal delay in the logic stage and the voltage supply to the sub power supply line VCT are performed substantially in synchronism, the operation speed is not substantially reduced.

  The signal delay time in the logic circuit does not necessarily match the operation of the switch MOSFET. This is because, if the power supply is delayed, the high-level output operation is correspondingly delayed, so that a practical logic output is actually formed depending on the voltage of the sub power supply line VCT supplied by the switch MOSFET. . Therefore, if the switch control of the switch MOSFET is extremely slow, the operation speed of the logic circuit is slowed down. Therefore, the time difference between the switch MOSFETs is set so that the peak current as described above is less than the allowable value. The voltage supply is sequentially performed as if it is tilted down.

  FIG. 13 is a block diagram for explaining another embodiment of the present invention. In the figure, an example is shown in which the sub power supply line and the subground line are divided into a plurality for each circuit block. In this example, the gate width of each switch MOSFET determined from the allowable voltage fluctuation value of each sub power supply line and subground line due to the on-resistance of the switch MOSFET can be made smaller than in the case of sharing as shown in FIG. .

  As a result, the charge / discharge currents of the gates of the switch MOSFETs QP10 to QP40 and the like are reduced, and one set of the sub power supply line and the sub ground line are sequentially used for each circuit block activated at almost the same timing. By starting the switch MOSFET, the peak current can be reduced. At the same time, since the gate width of the switch MOSFET is smaller than when the sub power supply line is not divided, the switch MOSFET can be started up quickly. Further, when there is a circuit block that does not perform a circuit operation, such as a Y system and a write circuit at the time of a refresh operation in a dynamic RAM, the switch MOSFET for the circuit block can be kept off, Current consumption can be reduced.

  FIG. 14 is a circuit diagram showing one embodiment of an X-system input portion in the dynamic RAM according to the present invention. In the same figure, the switch MOS control unit which has been omitted in the above embodiment and the X-system input portion related thereto are shown together.

  The switch MOS control unit receives the clock signal generated at the earliest time after receiving the input signal of RASB, and forms the activation signal SWC of the switch MOS. Therefore, the first stage portion of the RAS clock generation circuit, the X address buffer, and the switch MOS control portion that are activated before the switch MOSFET is turned on are not connected to the sub power line and the sub ground line. A gate and an inverter circuit, which are connected to the sub power supply line VCT and the subground line VST at the subsequent stage of the X predecoder and the RAS clock generation circuit and whose output signal when inactive is low (L), are as described above. A gate and an inverter circuit connected to the sub power supply line VCT and having an output signal at a high level (H) are connected to the sub ground line VST as described above. As a result, as described above, the switch MOSFET is turned off when it is inactive to reduce the subthreshold leakage current in the gate and inverter circuit, thereby suppressing current consumption during standby.

  A plurality of switch MOSFETs are connected in parallel, and delayed signals are supplied to the respective gates, so that the switch MOSFETs are sequentially turned on like a domino, while suppressing the peak current due to the drive and on state, VCC and VSS are supplied to the sub power line VCT and the sub ground line VST, respectively. A signal SET input to the switch MOS control circuit is an initialization signal for generating a switch MOS activation signal SWC when the circuit is turned on, and for turning on the switch MOSFET to raise the voltage of the sub power supply line VCT. Is. The signal TEST is a test signal for generating a start signal from the outside and forcibly turning on the switch MOSFET. It is pulled down to the ground via the resistance of this input node and is normally fixed at a low level.

  The switch MOSFET is turned off by a signal φτ obtained by delaying the RAS reset signal by time τ (˜5 n seconds) so that the switch MOSFET is not immediately turned off even when the signal RASB becomes high level. . This is because the circuit is precharged after the level of RASB goes high, so that the switch MOSFET is kept on during that time.

  When the dynamic RAM enters the self-refresh mode (CBR refresh), the self-refresh signal SELF is generated at timing A by the input of CBR (CAS before RAS) as shown in the timing chart of FIG. In this self-refresh mode, control is also possible with the internal signal IRASB in order to reduce the subthreshold leakage current by turning off the switch MOSFET except when the refresh operation is actually performed.

  In the refresh operation, the refresh operation is performed more intensively than the distributed refresh in which the one-time operation in which all the memory cells are refreshed once is uniformly distributed corresponding to the holding time. If the centralized refreshing is performed so that the inactive state is maintained until the refreshing, the number of times the switch MOSFET is controlled can be reduced. The multiplexer MPX provided in the X address buffer switches between the address signal ADi and the refresh address signal RADi input from the external terminal in response to the refresh control signal SELF and fetches them inside.

  The SET signal is for generating a switch MOSFET activation signal SWC when the circuit is turned on to turn on the switch MOSFET and raise the voltage of the sub power supply line VCT. Instead of such a signal SET, a MOSFET connected in a diode between the power supply line VCC and the sub power supply line VCT may be used. In this case, it is not necessary to turn on the switch MOSFET when the power is turned on. If the node of the internal circuit at the time of power-on is set to the inactive potential by the SET signal, all the current supply to the internal circuit at the time of power-on is performed from the power line VCC and the sub power line Since supply from the VCT is not performed, increasing the voltage of the sub power supply line VCT can be handled by a diode having a small current supply capability.

  If the switch MOSFET is turned on when the power is turned on, the sub-threshold leakage current flows because the internal circuit is in an active state. When the diode is used, the potential of the sub power supply line VCT does not rise to VCC, so that generation of a subthreshold leakage current can be prevented. This is even more effective when a MOSFET that applies a substrate bias using a substrate back bias voltage generation circuit is used. This is because in the MOSFET for applying the substrate bias, the substrate back bias voltage generation circuit does not generate a sufficient substrate bias voltage until the power is turned on, and thus the threshold voltage is lowered and a large subthreshold leakage current flows.

  A circuit that is not connected to the sub power line or sub ground line, such as the address buffer, and the switch MOSFET, a high threshold voltage MOSFET is used to reduce the subthreshold leakage current when the switch MOSFET is turned off. It is done. In the present invention, as a method for forming a MOSFET having such a high threshold voltage, a MOSFET having a long channel length is used by utilizing the gate length dependency of the threshold voltage of the MOSFET. In order to realize the gate length dependency of a desired threshold voltage, counter doping as described later is used.

  Realizing two or more threshold voltages by utilizing the gate length dependency of the threshold voltage of the MOSFET, realizing two or more threshold voltages by ion implantation using a conventional photomask. Compared with the method, at least two masks (for P channel and N channel) can be reduced, and the number of manufacturing steps can be reduced.

  FIG. 16 is a schematic cross-sectional view of an embodiment of a MOSFET used in the semiconductor integrated circuit device according to the present invention. FIG. 2A shows a normal MOSFET, and FIG. 2B shows a MOSFET using a counter-doping technique. The counter-doping technique is a technique for realizing a low threshold voltage MOSFET having excellent short channel characteristics by introducing impurities of the same conductivity type as those contained in the source and drain into the surface of the channel at a low concentration. Compared to a normal MOSFET as in FIG. 5A, the impurity concentration distribution is steeper in the direction perpendicular to the substrate surface of the channel portion, so that the threshold voltage can be lowered while suppressing the short channel effect. This is because the impurity concentration in the channel surface portion that determines the threshold voltage of the transistor is reduced by counter doping, but the impurity concentration in the deeper portion of the channel portion that determines the short channel characteristics is kept high. . Impurity introduction methods include low energy ion implantation, thermal diffusion from an oxide film, and instantaneous gas phase diffusion.

  FIG. 17 is a characteristic diagram showing the relationship between the gate length of N-channel MOSFET and the threshold voltage. In the figure, ◯ represents a conventional MOSFET as in the above (A), and ● represents a typical value of a counter-doped transistor, and these values vary, for example, between upper and lower broken lines or solid lines due to process variations.

  As described above, the allowable minimum threshold voltage of the MOSFET having a short gate length constituting the internal circuit connected to the sub power supply line and the sub ground line is the subthreshold leakage of the internal circuit when the switch MOSFET is in the ON state. In the example of the dynamic RAM shown in FIG. 1 and FIG. 2, the total gate width of the MOSFET is about 700,000 μm, and is about 0 V at room temperature. When the worst value of the threshold voltage due to process variations is set to 0 V, when a MOSFET having a conventional structure is used, for example, a gate length of 0.45 μm, a threshold voltage of 0.29 V (both typical values), and a counter-doped MOSFET When used, the gate length is 0.45 μm and the threshold voltage is 0.2 V (both typical values).

  At this time, due to process variations, the threshold voltage varies in the thick line frame B of FIG. 17 in the case of the MOSFET having the conventional structure, and in the thick line frame A in the case of the counter-doped MOSFET. As a result of suppressing the short channel effect by counter-doping, the variation in threshold voltage due to the variation in gate length is reduced, so that the typical threshold voltage can be lowered, and a logic circuit or the like is designed using a higher-speed MOSFET. be able to.

  The minimum value of the threshold voltage of the MOSFET having a long gate length constituting the circuit not connected to the sub power supply line VCT and the sub ground line VST is also determined by the subthreshold leakage current, and is the dynamic type shown in FIG. 1 and FIG. In RAM, it is set to about 0.2 V at room temperature. Therefore, in the same manner as described above, when a conventional MOSFET is used, the gate length is 0.53 μm, the threshold voltage is 0.42 V (both typical values), and when a counter-doped MOSFET is used, the gate length is 0. At 55 μm, the threshold voltage is 0.30 V (both typical values). The threshold voltage as described above varies due to process variations within the thick line frame D and C shown in FIG. 17, and it is possible to use a high-speed MOSFET having a low threshold voltage due to counter doping.

  In the switch MOSFET that connects the sub power line and the power line and the sub ground line and the ground line, when the threshold voltage varies, the sub-threshold leakage current in the off state greatly fluctuates. Therefore, these switch MOSFETs use MOSFETs having a long gate length with as little threshold voltage variation as possible due to process variations. This can be dealt with by setting the gate length dependence curve of the threshold voltage to be substantially flat, that is, 0.7 to 0.8 μm or more in FIG.

  Here, when the gate length of the switch MOSFET is increased, it is necessary to increase the gate width in order to reduce the on-resistance value. As a result, it must be noted that the peak current when the switch MOSFET is turned on also increases. That is, if the gate length dependency of the threshold voltage is small, the shorter the gate length of the switch MOSFET, the better. Therefore, in the present embodiment, when a MOSFET having a conventional structure is used, the gate length is 0.8 μm, the threshold voltage is 0.5 V (both typical values), and when a counter-doped MOSFET is used, the gate length is 0. The threshold voltage becomes 0.35 V (both typical values) at .7 μm, and variations occur in the ranges of the thick line frames F and E, respectively.

  In terms of reducing leakage current, using a MOSFET with a conventional structure is effective because the threshold voltage is higher, but the leakage current of a switch MOSFET is equivalent to the leakage current of a circuit that is not connected to the sub power line and sub ground line. This effect is negligible because it is small enough. Rather, the short channel effect is suppressed by counter-doping, so that a MOSFET with a short channel and high threshold voltage drive capability can be used as a switch MOSFET. Therefore, the gate width is smaller when a conventional MOSFET is used. And the peak current can be reduced.

  FIG. 18 is a characteristic diagram for explaining the present invention. In the figure, the vertical axis represents the increase in peak current and RAS access time tRAS, and the horizontal axis represents the time difference per step of the control signal of the switch MOSFET. The result of computer simulation is shown using an actual dynamic RAM circuit. A time difference of 0 per switch MOSFET control signal indicates that all switch MOSFETs are turned on simultaneously.

  The switch MOSFET is divided into five, and the gate width is 3000 μm for the P-channel type MOSFET and 900 μm for the N-channel type MOSFET as shown in the figure. From the figure, it can be seen that, for example, in order to suppress the peak current to 300 mA or less, the switch MOSFET is divided into a plurality of parts and a time difference of 250 psec is provided in the control signal. It can be seen that the delay in circuit operation at this time (that is, increase in tRAS) can be suppressed to 200 psec. Since the tRAS is 40 to 50 ns, the delay of the circuit operation due to the use of a plurality of switch MOSFETs and the rise of the time difference is only 0.5%. Therefore, it will be understood that the present invention can suppress the peak current while maintaining the high-speed circuit operation.

  FIG. 19 is a circuit diagram showing another embodiment of the present invention. In the figure, the internal circuit is shown as an example in which inverter circuits are connected in cascade. Then, the low-level input signal is supplied to the first-stage inverter circuit when it is inactive, the output of the inverter circuit is set to high level (H), and thereafter the output of each inverter circuit is sequentially low level (L), high level, low level. To be done. Therefore, the inverter circuit corresponding to the output high level is connected to the sub-ground line VST, and the inverter circuit corresponding to the output low level is connected to the sub-power supply line VCT.

  A P-channel switch MOSFET MC is provided between the sub power supply line VCT and the power supply line VCC, and is switch-controlled by a control signal φB. An N-channel switch MOSFET MS is provided between the sub-ground line VST and the ground line VSS, and is switch-controlled by a control signal φT. In this embodiment, an N-channel MOSFET MT for short-circuiting is provided between the sub power supply line VCT and the sub ground line VST. This MOSFET MT is switch-controlled by a control signal PT.

  FIG. 20 is a timing chart for explaining the operation of the above embodiment. When the internal circuit changes from the active state to the inactive state, the signal φB changes from the low level to the high level, the signal φT changes from the high level to the low level, and the switch MOSFETs MC and MS are changed from the on state to the off state. In synchronization with this, the control signal PT is temporarily set to the high level, the switch MOSFET MT is turned on, the sub power supply line VCT and the sub ground line VST are short-circuited to an intermediate potential, and power consumption can be reduced. become.

  When there is no short-circuit MOSFET MT as described above, when the sub power line VCT and the sub ground line VST transition from the active voltage to the inactive voltage, the charge charged in the parasitic capacitance of the sub power line VCT is When inactive, the output is discharged through the N-channel MOSFET in which the low-level inverter circuit is turned on. On the contrary, the parasitic capacitance of the sub-ground line VST is charged through a P-channel type MOSFET in which an inactive output is in an ON state. These discharging current and charging current are consumed. On the other hand, when the short-circuit MOSFET is provided as described above, the sub-power supply line VCT and the sub-ground line VST are connected to each other by the charge share between the respective parasitic capacitances, in other words, without performing special current consumption. The sub-threshold leakage current can be changed to a predetermined potential necessary for reducing the sub-threshold leakage current.

  The pulse width of the control signal PT for performing the switch control of the short-circuit MOSFET MT as described above is set so that the voltages of the sub power supply line VCT and the sub ground line VST are just the inactive voltages. Specifically, when the parasitic capacitance is 200 pF, the pulse width may be 100 nsec and the gate width of the switch MOSFET may be 10 μm.

  When there is no short-circuit MOSFET as described above, voltage transition between the sub power supply line VCT and the sub ground line VST takes 100 μs because charging / discharging due to the subthreshold leakage current occurs. On the other hand, when the short-circuit MOSFET MT is used, the voltage transition can be completed in 100 nsec.

  FIG. 21 shows a circuit diagram of another embodiment of the present invention. This embodiment differs from the conventional subthreshold current reduction circuit in that a P-channel type MOSFET (MOS diode) DP1 diode-connected between the power supply line VCC and the sub power supply line VCT is provided, and the ground line VSS is provided. And an N-channel MOSFET (MOS diode) DN1 diode-connected between the sub-ground line VST and the sub-ground line VST. Thereby, it is possible to improve the resistance of the subthreshold current reduction circuit against the voltage fluctuation (so-called power bump) of the power supply line VCC or the ground line VSS caused by the power supply voltage fluctuation of the device. That is, the diode-connected MOSFET is provided for the purpose of improving the resistance of the subthreshold current reduction circuit to the power bump.

  The circuit response to the power bump when the MOS diodes DP1 and DN1 are not provided will be described. Consider a case where a power bump occurs when the circuit is in an inactive state and the potential of the power line VCC rises. At this time, since the switching MOSFET QMC is in the OFF state, the potential of the sub power supply line VCT does not follow this, and the potential difference ΔVCT between VCC and VCT increases from the voltage value in the steady state by the increase in the potential of VCC. The potential difference ΔVCT gradually recovers to a steady-state voltage value because the sub power supply line VCT is charged by the subthreshold current flowing through the switching MOSFET QMC, but its speed is very slow.

  The inventors of the present application have noticed that the following problem occurs when the circuit is returned from the inactive state to the active state with the voltage difference ΔVCT as described above being large. One problem is that it takes a longer time than usual because a larger amount of charge must be charged in the sub power supply line VCCT in order to follow the increased power supply voltage VCC. If the logic circuit is operated before the potential of the sub power supply line VCT reaches the power supply line VCC, a reverse bias is applied between the gate and the source of the P-channel MOSFETs QP1, QP3, etc. The delay time increases. In order to avoid this, it is necessary to set a large margin in the time from the input of the activation signal to the addition of the input signal, which also increases the delay time of the circuit.

  Another problem is that the transient power supply current that flows when switching from the inactive state to the active state increases. As described above, since a large number of MOSFETs are connected to the sub power supply line VCT, the parasitic capacitance is large, and a transient current flows from the power supply line VCC in order to charge this when switching. If the voltage difference ΔVCT is larger than the steady-state voltage value, this current increases, so that the potential of the power supply line VCC fluctuates greatly, which may cause malfunction of the circuit.

  On the other hand, when the MOS diode DP1 is provided as in this embodiment, the potential difference ΔVCT is always less than or equal to the threshold voltage VT of the MOS diode DP1 even if the potential of the power supply line VCC is increased by the power supply bump. Kept. For this reason, it is possible to prevent an increase in delay time and potential fluctuation of the power supply line VCC due to a transient current. The above has described the case where the potential of the power supply line VCC increases, but conversely, the same applies when the potential of the ground line VSS decreases, and the provision of the MOS diode DN1 increases the potential difference ΔVST between VSS and VST. Can be prevented.

  FIG. 22 is a characteristic diagram for explaining the case where the present invention is applied to a peripheral circuit of a dynamic RAM of about 64 Mbits. The vertical axis in the figure shows the peak value of the power supply current that flows when the power supply line VCC rises from 2.9 V to 3.7 V in the inactive state and immediately after that (after 10 μs) transitions to the active state. As the gate width of the MOS diode DP1 is increased, the recovery speed of the voltage difference ΔVCT is increased and the peak value of the power supply current is decreased. However, since the gate and source of the MOS diode DP1 are forward-biased in the inactive state, the leakage current flowing through the MOS diode DP1 increases when the gate width is increased. In the peripheral circuit of the dynamic RAM, the leakage current needs to be suppressed to about 100 nA or less, so that the gate width of the MOS diode DP1 needs to be set to 100 μm or less from FIG. In this case, the peak value of the power supply current is about 360 mA. This is about 60% of the peak current (570 mA) when the MOS transistor DP1 is not provided, and can be reduced to about the same as the peak current value (350 mA) when no power bump is generated.

  The switch MOSFET QMC and the like are divided and divided into a plurality of switch MOSFETs so as to be sequentially turned on with a time difference in the signal transmission direction as in the above embodiment, and these are sequentially turned on as described above. When in the state, the peak value of the power supply current can be lowered as a whole. As described above, the configuration in which the MOS diode as described above is provided can be used for either the case where the switch MOSFET is formed as a single unit or the case where the switch is divided and sequentially controlled like the above-described domino effect. However, an effect as a countermeasure against power supply bumps can be obtained.

  FIG. 23 shows a circuit diagram of another embodiment of the present invention. Capacitors are used in place of MOS diodes as means for causing the potential of the sub power supply line VCT (subground line VST) to follow the power supply line VCC (ground line VSS). The capacitor CTC is also provided for the purpose of improving the resistance of the subthreshold current reduction circuit with respect to the power supply bump as described above. Capacitances CTC and CSC in the figure are coupling capacitors, and are formed by using, for example, MOSFET gate capacitances. When the parasitic capacitance of the sub power supply line VCT is CT, the potential fluctuation of the sub power supply line VCT when the potential of the power supply line VCC fluctuates by ΔV is given by ΔV / (1 + CT / CTC). As the coupling capacitance CTC is made larger than the parasitic capacitance CT, the followability of the sub power supply line VCT to the potential fluctuation of the power supply line VCC is improved. In a design example in which a peripheral circuit of a dynamic RAM of about 64 Mbit is applied to the present invention, the parasitic capacitance CT is about 200 pF, and the coupling capacitance CTC is 400 pF. In this case, if the potential of the power supply line VCC rises by, for example, 0.8V, the potential of the sub power supply line VCCT also rises by 0.53V. Therefore, the fluctuation (increase) in the potential difference ΔVCT can be suppressed to 0.27V.

  The means for preventing the increase in the potential difference ΔVCT (or ΔVST) caused by the power supply bump has been described above. However, the present inventors have noticed that the increase in the potential difference ΔVCT or ΔVST can occur for other reasons, that is, when the input level of the circuit is switched despite the inactive state. That is, when the level of the input signal is switched in the inactive state, a part of the circuit performs a logic operation accordingly. The operating current in this case is supplied from the sub power line VCT and sub ground line VST in the floating state. That is, since the switch MOSFET connected to the power supply line VCC and the ground line VSS is in the OFF state in the inactive state as described above, the potential of the sub power supply line VCT is lowered by the discharge current due to the logic operation current, The potential of the ground line VST rises due to the charging current.

  FIG. 24 shows a circuit diagram of another embodiment of the present invention. In this embodiment, in order to prevent an increase in potential change of the sub power supply line VCT and the subground line VST due to an undesired change in the level of the input signal as described above, a two-input NAND ( NAND) gate circuit N1 is provided. The input signal IN is applied to the logic circuit via this gate N1. An active / inactive switching control signal φ is applied to the other input of the gate circuit N1 through the inverter circuit INV1. The control signal φ is applied to the gate of the switching N-channel MOSFET QMS via the inverter circuit INV1, and is applied to the gate of the switching P-channel MOSFET QMC via the inverter circuits INV1 and INV2.

  In the inactive state, the control signal φ is at a high level, turning off the switching P-channel MOSFET QMC and the switching N-channel MOSFET QMS and fixing the output signal of the gate circuit N1 to a high level. For this reason, even if the level of the input signal IN fluctuates due to noise or the like, the logic circuit does not operate in response thereto. When switched to the active state, the control signal φ becomes low level, and a signal corresponding to the level of the input signal IN is input, so that the logic circuit operates as usual.

  In order for the circuit of the embodiment described above to operate normally, the power supply and the ground of all the logic gates constituting the circuit are appropriately selected from VCC / VCC and VSS / VST according to the output level when inactive. Must be connected to the side. That is, in the logic gate whose output when inactive is high, the source of the P-channel MOSFET is connected to the power supply line VCC, and the source of the N-channel MOSFET is connected to the sub-ground line VST. In the logic gate whose output when inactive is low level, the source of the P-channel MOSFET is connected to the sub power supply line VCT, and the source of the N-channel MOSFET is connected to the ground line VSS. However, in a circuit composed of a large number of gates, it is problematic not only for man-hours but also for reliability to verify this manually. This is a major problem in applying the present invention to a large-scale integrated circuit such as a large-capacity dynamic RAM or a microprocessor.

  FIG. 25 is a circuit diagram for explaining the principle of the method for verifying the power connection of each gate in the logic circuit for reducing the subthreshold leakage current according to the present invention. In the example of the figure, the connection of the power supply line and the ground line of the second-stage inverter circuit INV2 and the third-stage inverter circuit INV3 is incorrect. That is, since the output (node N2) of the inverter circuit INV2 is at a low level in the inactive state, it should be connected to the ground line VSS, but erroneously connected to the sub-ground line VST. Since the output (node N3) of the inverter circuit INV3 is at a high level, it should be connected to the power supply line VCC, but is erroneously connected to the sub power supply line VCT.

  In this case, the output of the inverter circuit INV2 (node N2) becomes the same potential as that of the sub-ground line VST via the N-channel MOSFE in the on state, and the output (node N3) of the inverter circuit INV3 is the P-channel type in the on state. The potential is the same as that of the sub power supply line VCT via the MOSFE. On the other hand, the output node N1 of the first-stage inverter circuit INV1 and the output node N4 of the fourth-stage inverter circuit INV4 that are correctly connected have the same potential as the power supply line VCC and the ground line VSS, respectively. . Focusing on this, in the circuit analysis simulation, the potentials of the sub power supply line VCT and subground line VST are set to be different from the potential settings of the power supply line VCC and ground line VSS, and the potential of each node is obtained. To. Then, the potentials of the nodes N1 and N4 of the inverter circuits INV1 and INV4 that are correctly connected are equal to VCC and VSS, respectively, whereas the potentials of the inverter circuits INV2 and INV3 that are incorrectly connected are The potentials of the nodes N2 and N3 are equal to VCT and VST, respectively. By searching for a node that becomes the potential of the set sub power supply line VCT and sub ground line VST, it is possible to find an inverter circuit or a logic gate that is erroneously connected.

  For example, the sub power line VCC is increased with respect to the power line VCC, the sub ground line VST is decreased with respect to the ground line VSS, the voltage VN of a certain node is obtained by circuit simulation, and the conditions of VN> VCC and VN <VSS are obtained. It is possible to easily find the wrong connection. Conversely, the sub power line VCC is lowered with respect to the power line VCC, the sub ground line VST is raised with respect to the ground line VSS, and the voltage VN of a certain node is obtained by circuit simulation, and VN <VCC and VN> VSS. If the condition is found, the condition of VN> VSS is established when NV = VCC is established by the correct connection, and the condition of VN> VCC is established when NV = VSS is established by the correct connection. It cannot be detected by comparison. Therefore, when the sub power supply line VCT is set lower than the power supply line VCC and the subground line VST is set higher than the ground line VSS, the voltage VN equal to the set voltage VCT or VST is set. I will try to find out.

  FIG. 26 shows a system configuration diagram of an embodiment of a verification system for implementing the above-described power connection verification method. The power connection verification system according to this embodiment is not particularly limited, and includes a circuit simulator using a computer such as SPICE and post-processing software for analyzing the output of the circuit simulator and detecting a connection error. In the circuit simulator, the potentials of the sub power supply line VCT and subground line VST are set to be different from the potentials of the power supply line VCC and ground line VSS as described above, as shown in FIG. The potential VN is calculated. The result is processed by post-processing software via an intermediate file. As described above, when the sub power supply line VCT is made higher than the power supply line VCC and the subground line VST is made lower than the ground line VSS, those having the conditions of VN> VCC and VN <VSS are extracted. The extracted nodes are printed out as a list, and the position on the circuit diagram is displayed on the screen of the graphic terminal.

  In the above embodiment, in order to reduce the subthreshold leakage current by lowering the threshold voltage, the logic gate or the inverter circuit whose output is inactive is connected to the power supply line VCC and the ground side is connected to the logic gate or inverter circuit. Connected to the sub-ground line VST, the switch MOSFET provided on the sub-ground line VST is turned off, and the logic gate or inverter circuit whose output when inactive is low is connected to the ground line VSS, and the power supply side is connected Connected to the sub power supply line VCT, the switch MOSFET provided in the sub power supply line VCT is turned off.

  When the above switches are turned on or off, in the above embodiment, in order to obtain a desired on-resistance, the driving current of the switch MOSFET having a relatively large gate capacitance and the peak of the power supply current accompanying the on-state In order to reduce the current, there is a great feature in that it is divided into a plurality of parts, and a delay signal is supplied to each of them and the switch is controlled with a time difference like a domino effect. This has the possibility of being used as a general power switch in addition to the reduction of the subthreshold leakage current by the sub power line and the sub ground line as described above. In other words, with the advancement of semiconductor technology, a large number of functional blocks can be mounted on a single semiconductor substrate, and a digital information processing system can be realized by itself, and this trend is expected to increase in the near future. Is done.

  In this case, a large number of functional blocks need not always be in an operating state. At this time, if there is a functional block that does not need to operate while performing predetermined data processing, all the current consumption including the leakage current such as the subthreshold leakage current is cut off. This has enough significance. In such a case, when viewed from the functional block in the operating state when the power switch is in an on state or an off state, it is not allowed to have a large noise on the power line. From this point of view, when a specific functional block mounted on one semiconductor integrated circuit device is in operation, there is a big problem in turning off or turning on the power of other functional blocks that do not operate.

  However, the switch MOSFET of the embodiment can be turned on and off without generating such a peak current. That is, the switch MOSFET according to the present invention can be used as a switch MOSFET that selectively supplies power to a circuit block formed in a semiconductor integrated circuit device.

  FIG. 27 shows a system configuration diagram of an embodiment of a one-chip microcomputer to which the present invention is applied. The microcomputer MCU of this embodiment has a central processing unit CPU of a stored program system including an arithmetic unit ALU as its central component. A multiplier MULT, a memory management unit MMU, and a cache memory CACHE are coupled to the central processing unit CPU via a system bus S-BUS, and an address conversion table TLB is coupled to the memory management unit MMU. The memory management unit MMU and the cache memory CACHE are further coupled to the cache bus C-BUS on the other side, and the bus controller BSC is coupled to the cache bus C-BUS.

  Bus controller BSC is otherwise coupled to peripheral bus P-BUS and external bus E-BUS. Among these, peripheral bus P-BUS includes peripherals such as refresh controller REFC, direct memory access controller DMAC, timer circuit TIM, serial communication interface SCI, digital / analog conversion circuit D / A, and analog / digital conversion circuit A / D. A device controller and a clock controller CKC are coupled, and an external interface EXIF is coupled to the external bus E-BUS.

  The refresh controller REFC, the direct memory access controller DMAC, the timer circuit TIM, the serial communication interface SCI, the digital / analog conversion circuit D / A, and the analog / digital conversion circuit A / D are coupled to the interrupt controller INTC on the other side, and this interrupt The controller INTC is coupled to the central processing unit CPU via an interrupt request signal IRQ. A clock pulse generation circuit CPG and a plurality of clock switches described later are coupled to the clock controller CKC, and a portable information terminal PDA, an external memory, and the like are coupled to the external interface EXIF.

  A real-time clock circuit RTC is further coupled to the interrupt controller INTC. The real-time clock circuit RTC is supplied with a clock signal having a stable frequency whose frequency is not changed. Thereby, the real-time clock circuit RTC performs accurate time management.

  The real time clock circuit RTC outputs an interrupt signal RTCI to the interrupt controller INTC at a predetermined time interval, and generates an interrupt request at a predetermined time interval with respect to the central processing unit CPU. The interrupt controller INTC is also supplied with an external interrupt signal OINT via a predetermined external terminal. As a result, the external device is logically coupled to the central processing unit CPU via the interrupt controller INTC.

  In this embodiment, the clock controller CKC includes a plurality of control registers. In these control registers, predetermined control data is written or read out from the central processing unit CPU via the peripheral bus P-BUS. The clock controller CKC selectively forms the control signals PLLON, PLLSB, COSEL1, COSEL2, or CKEN according to the control data set in each control register, and selectively forms a plurality of module enable signals ADEN and the like. . In order to avoid the complexity of the drawing, these control signals and module enable signals are shown by a single wiring. Needless to say, the clock controller CKC may be coupled to the system bus S-BUS instead of the peripheral bus P-BUS.

  Here, the central processing unit CPU operates in synchronization with the system clock signal CK1 supplied from the clock pulse generation circuit CPG, and executes predetermined arithmetic processing according to a control program read from the cache memory CACHE, for example, and a microprocessor. Control and supervise each part of MPU. At this time, the arithmetic unit ALU executes arithmetic logic operations as necessary, and the multiplier MULT executes multiplication processing. In addition, the memory management unit MMU converts the logical address output from the central processing unit CPU when accessing the memory into a physical address using the address conversion table TLB.

  The cache memory CACHE is a memory that can be accessed at high speed, reads out and holds a program or data stored in an external memory provided outside the microprocessor MPU in predetermined block units, and operates at a high speed of the central processing unit CPU. Contribute to. The central processing unit CPU, the multiplier MULT, the memory management unit MMU, and the cache memory CACHE operate according to a relatively high frequency system clock signal CK1.

  The bus controller BSC manages the bus access of each peripheral device controller coupled to the peripheral bus P-BUS and controls the operation of these peripheral device controllers. On the other hand, the refresh controller REFC, which is one of the peripheral device controllers, controls the refresh operation of a dynamic RAM (random access memory) provided as an external memory, and the direct memory access controller DMAC, for example, includes an external memory and a cache memory CACHE. Support high-speed data transfer to and from.

  The timer circuit TIM supports time management required by the central processing unit CPU, and the serial communication interface SCI supports serial data transfer with an external communication control device or the like. Further, the analog / digital conversion circuit A / D converts an analog signal input from an external sensor or the like into a digital signal of a predetermined bit, and the digital / analog conversion circuit D / A is output from the central processing unit CPU. The converted digital signal is converted into a predetermined analog signal and output externally.

  The interrupt controller INTC selectively accepts an interrupt request from each peripheral device controller with a predetermined priority and transmits it as an interrupt request signal IRQ to the central processing unit CPU. The external interface EXIF controls and manages data exchange between each part of the microcomputer MCU and the externally connected portable information terminal PDA, external memory, etc., and between these external devices and the microcomputer MCU. Perform interface matching. The bus controller BSC and various peripheral device controllers operate in synchronization with a system clock signal cks having a relatively low frequency.

  In this embodiment, each part constituting the microcomputer MCU is formed in one semiconductor integrated circuit device LSI with a predetermined layout condition. These parts are so-called modularly and selectively based on user specifications. It is formed. The microcomputer MCU of this embodiment includes a plurality of power switch MOSFETs provided corresponding to each of the plurality of modules and selectively turned on in response to the effective level of the corresponding module enable signal. Such a switch MOSFET is turned off when is deactivated, resulting in substantially zero current consumption there.

  The digital / analog converter D / A and the analog / digital converter A / D have a linear circuit portion, and consume a relatively large current even in a non-operating state. Moreover, it often does not need to work all the time. Therefore, by interrupting the operating current with the power switch MOSFET as described above, the current consumption when inactive can be made zero. In other digital circuits, if a leakage current such as a subthreshold leakage current is generated, it is significant to shut off the power supply. When the power switch MOSFET as described above is provided, a large peak current flows during the switch control. Therefore, the switch MOSFETs provided in the functional blocks of each module, etc. are made into a plurality of switch MOSFETs connected in parallel, and the peak is obtained by sequentially turning them on / off like a domino effect by an activation signal. The current can be reduced. Therefore, the functional block of each module or the like is not required to be a circuit that does not allow direct current to flow during non-operation, such as a linear circuit such as the digital / analog conversion circuit D / A.

  In a system with high integration, high speed, and low voltage using a MOSFET with a low threshold voltage, subthreshold leakage current becomes a problem as in the dynamic RAM. Therefore, in each functional block, in the portion where the level at the time of inactivity is fixed, it is connected to the sub power line or sub ground line as in the above embodiment, and the switch MOSFET provided there is turned off. Needless to say, generation of leakage current such as sub-threshold leakage current during standby may be prevented.

The effects obtained from the above embodiment are as follows. That is,
(1) Between the internal power supply lines of a plurality of circuit blocks divided for each function and each configured to perform a circuit operation by an operation control signal, and a power supply line for transmitting an operation voltage supplied from an external terminal A plurality of switch MOSFETs are provided in a parallel form, and these switch MOSFETs are sequentially turned on by supplying the operation voltage as if the above-mentioned operation control signals are sequentially delayed by the control signal delayed by the control signal. While preventing generation of a peak current in the off state, current consumption when the functional block or module is in an inactive (non-operating) state can be made zero.
(2) An input circuit block that responds to an input signal supplied from an external terminal including an operation start signal, an internal circuit block that operates in response to an input signal input through the input circuit block, and an output of the internal circuit block A first circuit portion that does not require a memory operation when it is in a non-operating state among a power supply line for transmitting an operating voltage supplied from the external terminal and the internal circuit block. A plurality of switch MOSFETs are provided in parallel with the internal power supply line, and the operating voltage is sequentially turned on like a domino effect by a control signal obtained by sequentially delaying the start signal supplied through the input circuit. To prevent the occurrence of peak current in the on / off state without sacrificing the operating speed, and The current consumption in the inactive (non-operating) state in such a functional block can be made zero.
(3) Of the input circuit block and the internal circuit block, the second circuit portion and the output circuit block that require a storage operation are provided with an operating voltage from the power supply line, thereby operating speed. The desired circuit function can be maintained without sacrificing.
(4) The internal circuit block is composed of a CMOS circuit, and the first circuit portion of the CMOS circuit has a first circuit corresponding to the ground voltage for a circuit whose output signal level is high when in the non-operating state. A circuit connected to the internal power supply line and whose output signal is at a low level is connected to a second internal power supply line corresponding to the power supply potential, between the first internal power supply line and the power supply line, and to the second internal power supply line. By providing an internal power switch circuit composed of a plurality of switch MOSFETs that are sequentially turned on like a domino effect by a control signal in which the start signal is sequentially delayed between the line and the ground line The subthreshold leakage current can be reduced while maintaining the speed and suppressing the peak current.
(5) The P-channel type MOSFET and the N-channel type MOSFET constituting the CMOS circuit can reduce the subthreshold leakage current while maintaining the low voltage and high speed by reducing the threshold voltage. it can.
(6) The input circuit block and the output circuit block are constituted by CMOS circuits, and the P-channel MOSFET and N-channel MOSFET constituting the CMOS circuit and the MOSFET constituting the internal power switch circuit are the internal circuit. By setting the threshold voltage relatively large compared to the threshold voltages of the P-channel MOSFET and N-channel MOSFET of the CMOS circuit constituting the circuit, high-speed operation can be maintained while suppressing the subthreshold leakage current.
(7) The threshold voltage is set by the MOSFET channel length dependency, and the counter doped layer having the same conductivity type as the source and drain and having a low impurity concentration is formed on the surface of the channel region. , Speed up and peak current can be reduced.
(8) The internal circuit block is divided into a plurality of blocks corresponding to the operation sequence, and the activation signal is delayed in synchronization with the operation sequence and supplied to the internal power switch circuit. The peak current can be reduced by further distributing the current when the power switch is turned on / off.
(9) The input circuit is an input circuit to which an address signal and a control signal are supplied in an address multiplex system, and the internal circuit block includes a memory array using dynamic memory cells and an X-system address selection circuit thereof. And the Y-system address selection circuit. The output circuit is divided like a data input / output circuit, so that the circuit is divided in accordance with the operation sequence of the dynamic RAM and sequentially controls the power switch MOSFET. Thus, the peak current can be rationally reduced while maintaining the operation speed.
(10) The internal power switch circuit provided in the Y-system address selection circuit is composed of one or a plurality of MOSFETs configured to flow an operation current necessary for the operation of the circuit, and has a long time until operation. Can be used to moderate the change in the control signal supplied to the gate of the MOSFET, thereby reducing the peak current with a simple configuration.
(11) Between the first internal power line and the second internal power line, a short-circuit switch MOSFET that is temporarily turned on when the corresponding internal power switch MOSFET is turned off. By providing the voltage, the inactive voltage can be determined at high speed by the charge share between the first internal power supply line and the second internal power supply line, so that the subthreshold leakage current can be further reduced.
(12) Between the first internal power supply line and the second internal power supply line, the first internal power supply line and the second internal power supply line follow the potential change of the power supply line and the ground line. By providing a coupling means composed of a MOS diode or a capacitor for changing the potential, when the potential of the power supply line or the ground line greatly fluctuates due to the power supply bump, the first internal power supply line and the first power supply line with respect to the power supply line or the ground line The voltage difference from the potential of the internal power supply line 2 can be kept small, and an increase in peak current when the internal circuit is activated can be suppressed.
(13) An input signal is supplied to the input terminal of the first circuit portion composed of the CMOS circuit via a gate by a control signal for activating the first circuit portion, and control corresponding to the inactive state is performed. By fixing the signal level input to the input terminal of the first circuit portion by the signal, the input signal can be maintained at a fixed level against power supply noise and the like. Undesirable fluctuations in the internal power supply line can be prevented and the voltage difference from the power supply line and the ground line can be kept small, and an increase in peak current when the internal circuit is activated can be suppressed.
(14) Of the internal circuits composed of CMOS circuits, the first circuit whose output signal level is low when in the non-operating state is the first internal corresponding to the power supply line to which the power supply voltage supplied from the external terminal is transmitted The second circuit having a high level output signal connected to the power supply line and a ground line to which the ground potential supplied from the external terminal is transmitted is connected to the power supply line and the corresponding second internal power supply line. In such a semiconductor integrated circuit device, the computer simulator sets a potential different from that of the power supply line and the ground line to the first and second internal power supply lines, respectively, and calculates the potential of the output node of each circuit. By detecting that the potential of the node corresponds to the potential of the first and second internal power supply lines and outputting the node information, it is possible to easily find the erroneous connection location. Can.

  The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, a method of forming a MOSFET having a threshold voltage such that the subthreshold leakage current does not substantially become a problem like the input unit, the output circuit, and the power switch MOSFET uses the channel length dependency as described above. In addition, various embodiments can be adopted such as increasing the impurity concentration of the channel portion, controlling the gate insulating film, or supplying a deep back bias to the substrate on which they are formed.

  The internal circuit in the dynamic RAM may be one in which the operation mode is determined by a command like the synchronous dynamic RAM, in addition to the one in which the operation mode is set by the control signal from the external terminal as described above. In this case, the switch MOSFET may be controlled by a control timing circuit that receives command data output. In the static RAM, the switch MOSFET may be controlled by a chip enable signal. However, since the static RAM for cache memory has a mode in which the circuit operates even if the external input signal does not change, the switch MOS control circuit may be switched by a mode determination signal or the like corresponding thereto. The present invention can be applied to various semiconductor integrated circuit devices constituted by MOSFETs in addition to the memory circuit as described above and a one-chip microcomputer.

1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is mainly applied, an X system circuit and an array block; FIG. 1 is a block diagram showing one embodiment mainly of a Y-system and a write circuit and an output buffer of a dynamic RAM to which the present invention is applied. FIG. 1 is a circuit diagram showing one embodiment of an X-system address input section of a dynamic RAM to which the present invention is applied. FIG. 1 is a circuit diagram showing one embodiment of a predecoder for receiving an internal address signal of a dynamic RAM to which the present invention is applied. FIG. 1 is a specific circuit diagram showing an embodiment of an X decoder of a dynamic RAM to which the present invention is applied, a latch circuit provided in the decoder, and a word driver. FIG. 1 is a circuit diagram showing one embodiment of a mat control circuit of a dynamic RAM to which the present invention is applied. FIG. It is a timing diagram explaining an example of the operation of the dynamic RAM to which the present invention is applied. 1 is a block diagram showing an embodiment of a dynamic RAM memory array and its peripheral selection circuit to which the present invention is applied; FIG. 1 is a block diagram showing an embodiment of an input / output interface unit and a timing control circuit of a dynamic RAM to which the present invention is applied. FIG. 3 is a circuit diagram of a principal part showing an embodiment of a memory array portion of a dynamic RAM according to the present invention. 1 is a cross-sectional view of an element structure of one embodiment for explaining a dynamic RAM according to the present invention. 1 is a block diagram for explaining one embodiment of a semiconductor integrated circuit device according to the present invention. It is a block diagram for demonstrating another Example of the semiconductor integrated circuit device based on this invention. 3 is a circuit diagram showing one embodiment of an X-system input portion in the dynamic RAM according to the present invention. FIG. FIG. 15 is a timing chart for explaining an example of the operation of the X-system input portion of FIG. 14. 1 is a schematic cross-sectional view showing an embodiment of a MOSFET used in a semiconductor integrated circuit device according to the present invention. FIG. 6 is a characteristic diagram showing the relationship between the gate length and the threshold voltage of an N-channel MOSFET for explaining the present invention. FIG. 6 is a characteristic diagram showing a relationship between a peak current and a delay time of a start signal of a switch MOSFET for explaining the present invention. It is a circuit diagram which shows another Example of this invention. FIG. 20 is a timing chart for explaining the operation of the embodiment of FIG. 19. It is a circuit diagram which shows another Example of this invention. FIG. 10 is a characteristic diagram for explaining a case where the present invention is applied to a peripheral circuit of a dynamic RAM of about 64 Mbits. It is a circuit diagram which shows another Example of this invention. It is a circuit diagram which shows another Example of this invention. It is a circuit diagram for explaining the principle of a method for verifying the power supply connection of a logic circuit for reducing subthreshold leakage current according to the present invention. FIG. 26 is a system configuration diagram showing an embodiment of a verification system for implementing the power connection verification method of FIG. 25. 1 is a system configuration diagram showing an embodiment of a one-chip microcomputer to which the present invention is applied. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... RAS input buffer, 2 ... RAS clock generation circuit, 3 ... Address buffer, 4 ... X address latch circuit, 5 ... CBR counter, 6 ... X predecoder, 7 ... Mat select circuit, 8 ... X address comparator, 9 ... Mat control circuit, 12 ... X decoder, 13 ... word driver, 14 ... sense amplifier, 15 ... memory array, 16 ... common source switch, 17a-17d ... delay circuit, 18 ... CAS input buffer, 19 ... CAS clock generation circuit, 20 ... Y address latch, 21 ... write clock generation circuit, 22 ... output enable input buffer, 23 ... write enable input buffer, 24 ... data input buffer, 25 ... address change detection circuit, 26 ... equalizing pulse generation circuit, 27 ... main Amplifier control circuit, 28 ... Predecoder, 29 ... Y address comparator, 30 ... main amplifier, 31 ... write buffer control circuit, 32 ... write buffer, 33 ... Y decoder, 34 ... vendor test circuit, 35 ... data selector, 36 ... data output buffer, QP1 QN5: Switch MOSFET,
CN1-CN4 ... clocked inverter circuit, Q1-Q9 ... MOSFET, IV1 ... inverter circuit,
MAT0 to MAT7 ... Memory mat, MARY0, MARY1 ... Memory array, XD0 to XD7 ... Decoder circuit, WD0 to WD7 ... Word driver, SA01 to SA67 ... Sense amplifier, XDEC ... Row decoder circuit, ARYCTRL ... Array control circuit, YDEC ... Column Decoder circuit, MATCTRL0 to MATCTRL3 ... mat control circuit, TG ... timing control circuit, I / O ... input / output circuit, RAB ... row address buffer, CAB ... column address buffer, AMX ... multiplexer, RFC ... refresh address counter circuit, XPD, YPD: Pre-coder circuit, X-DEC: Row redundant circuit, XIB: Decoder circuit,
M1-M3: Aluminum wiring layer, TH1, TH2: Through hole, LCNT, FCNT ... Contact, FG ... First layer polysilicon (gate electrode), SG ... Second layer polysilicon (storage node), TG ... Third layer Polysilicon (plate).

QMC, QMS ... switch MOSFET, DP1, DN1 ... diode connection MOSFET, CTC, CSC ... coupling capacitance, INV1-INV4 ... inverter circuit, N1 ... gate circuit,
CPU ... Central processing unit, ALU ... Calculator, MULT ... Multiplier, MMU ... Memory management unit, TLB ... Address conversion table, CACHE ... Cache memory, BSC ... Bus state controller, REFC ... Refresh controller, DMAC ... Direct memory access controller , TIM ... Timer circuit, SCI ... Serial communication interface, D / A ... Digital / analog conversion circuit, A / D ... Analog / digital conversion circuit, INTC ... Interrupt controller, CPG ... Clock generation circuit, S-BUS ... System bus, C-BUS ... cash bus, P-BUS ... peripheral bus.

Claims (7)

  1. A first circuit block that receives a first address signal and outputs a second address signal based on the input of the first address signal ;
    A second circuit block that receives a third address signal and outputs a fourth address signal based on the input of the third address signal;
    The second address signal output from the first block and the fourth address signal output from the second circuit block are connected to the first circuit block and the second circuit block, respectively. A third circuit block;
    With
    Each of the first to third circuit blocks is supplied with power according to activation of the first to third power control signals, respectively.
    After the power supply of the first circuit block is started by the activation of the first power supply control signal, and before the power supply of the second circuit block is started by the activation of the second power supply control signal, the second circuit block is started. Starting power supply to the third circuit block by activating three power control signals;
    A semiconductor integrated circuit device.
  2. The power supply of the second circuit block is started after the power supply of the first circuit block is started and the power supply of the third circuit block is started. A semiconductor integrated circuit device.
  3. In claim 2,
    The first circuit block is a circuit block that forms an X-system circuit with respect to the memory array,
    The second circuit block is a circuit block that forms a Y-system circuit for the memory array,
    The third circuit block is a circuit block including the memory array.
    A semiconductor integrated circuit device.
  4. In claim 3,
    A row address strobe signal is input from the outside, the first address signal is output based on the row address strobe signal, and a column address strobe signal is input from the outside, and the second address signal is input based on the column address strobe signal. Is further provided with an input circuit block for outputting
    The first circuit block includes an X predecoder to which a first address signal output from the input circuit block is input, and an X decoder to which a selection signal output from the X predecoder is input.
    The second circuit block includes a Y predecoder to which a second address signal output from the input circuit block is input, and a Y decoder to which a selection signal output from the Y predecoder is input.
    The memory array of the third circuit block includes a word line selected according to the output signal of the X decoder and a bit line selected according to the output signal of the Y decoder,
    The selected word line of the third circuit block is supplied with power to the third circuit block after power supply to the first circuit block is started and before power supply to the second circuit block is started. Activated upon supply,
    A semiconductor integrated circuit device characterized by the above.
  5. In claim 4,
    The X predecoder of the first circuit block includes a plurality of circuit stages that are serially connected in multiple stages, and each stage has a power supply,
    The plurality of circuit stages include a first NAND circuit to which the first address signal is input, a second NAND circuit to which an output of the first NAND circuit is input, and a first CMOS inverter circuit to which an output of the second NAND circuit is input. And a second CMOS inverter circuit to which the output of the first CMOS inverter circuit is input,
    The power supply includes a first power supply line connected to the first NAND circuit and the first CMOS inverter circuit, a second power supply line connected to the second NAND circuit and the second CMOS inverter circuit, and the first NAND circuit. And a first ground line connected to the first CMOS inverter circuit, and a second ground line connected to the second NAND circuit and the second CMOS inverter circuit.
    A semiconductor integrated circuit device.
  6. 6. The semiconductor integrated circuit device according to claim 4 , wherein a transition speed of the second power control signal is slower than a transition speed of the first power control signal.
  7. 7. The MOSFET according to claim 6, wherein one end is connected to a circuit block, the other end is connected to a power source of the circuit block, and a power supply control signal corresponding to the circuit block is input to a gate terminal. A semiconductor integrated circuit device comprising three circuit blocks.
JP2007336586A 1995-12-21 2007-12-27 Semiconductor integrated circuit device Expired - Fee Related JP4852524B2 (en)

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