JP4847163B2 - Cmos製造技術と両立可能なバイポーラデバイス - Google Patents
Cmos製造技術と両立可能なバイポーラデバイス Download PDFInfo
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- JP4847163B2 JP4847163B2 JP2006061615A JP2006061615A JP4847163B2 JP 4847163 B2 JP4847163 B2 JP 4847163B2 JP 2006061615 A JP2006061615 A JP 2006061615A JP 2006061615 A JP2006061615 A JP 2006061615A JP 4847163 B2 JP4847163 B2 JP 4847163B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000005516 engineering process Methods 0.000 title description 8
- 238000005192 partition Methods 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 24
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 description 7
- 238000002955 isolation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Description
31 STI(分離構造)
32 活性領域
33 エミッタ
34 コレクタ
35 外部ベース
36 Nウェル(半導体基板)
36’ P型基板
37 内部ベース
38 ゲート(ゲート端子)
39 仕切部
40 バイポーラデバイス
41 エミッタ
42 コレクタ
43 内部ベース
44 外部ベース
45 Nウェル(半導体基板)
46 活性領域
47 STI(分離構造)
48 制御ゲート(ゲート)
49 ダミーポリゲート
50 バイポーラデバイス
53 エミッタ
54 コレクタ
55 仕切部
56 外部ベース
61 仕切部
62 外部ベース
70 バイポーラデバイス
73 外部ベース
80 バイポーラデバイス
85 第1のエミッタ
86 第2のエミッタ
87 第1のコレクタ
88 第2のコレクタ
89 共有する外部ベース
90 バイポーラデバイス
91 第1のゲート端子
92 第2のゲート端子
93 第1の仕切部
94 第2の仕切部
95 第1の外部ベース
96 第2の外部ベース
97 第1のコレクタ
98 第2のコレクタ
99 共有するエミッタ
100 バイポーラデバイス
101 外部ベース
102 外部ベース
711 第1のゲート端子
712 第1のエミッタ
713 第1のコレクタ
714 第1の仕切部
721 第2のゲート端子
722 第2のエミッタ
723 第2のコレクタ
724 第2の仕切部
Claims (6)
- 基板の活性領域に形成されるバイポーラデバイスであって、
前記基板に形成される第1のエミッタと、
前記第1のエミッタから横方向に空間を置いて、前記基板に設けられる第1のコレクタと、
前記第1のエミッタと前記第1のコレクタ間の空間上に配置される第1のゲート端子と、
前記第1のゲート端子の下部に規定され、前記第1のエミッタおよび前記第1のコレクタと第1のバイポーラ接合部を形成する第1の内部ベースと、
前記基板に形成される第2のエミッタと、
前記第2のエミッタから横方向に空間を置いて、前記基板に設けられる第2のコレクタと、
前記第2のエミッタと前記第2のコレクタ間の空間上に配置される第2のゲート端子と、
前記第2のゲート端子の下部に規定され、前記第2のエミッタおよび前記第2のコレクタと第2のバイポーラ接合部を形成する第2の内部ベースと、
前記第1のコレクタおよび前記第2のコレクタに隣接し、前記第1のコレクタおよび前記第2のコレクタから隔離されると共に、前記基板を経由して前記第1の内部ベースと前記第2の内部ベースに接続される共通の外部ベースと、
前記共通の外部ベースから、前記第1のコレクタと前記第2のコレクタをそれぞれ隔離する第1の仕切部と第2の仕切部と、
からなることを特徴とするバイポーラデバイス。 - 前記第1の仕切部と前記第2の仕切部は、シリサイド形成を遮断するための遮断層であることを特徴とする請求項1記載のバイポーラデバイス。
- 前記第1の仕切部と前記第2の仕切部は、ダミーゲートであることを特徴とする請求項1記載のバイポーラデバイス。
- CMOS製造工程を利用して、基板の活性領域に形成されるバイポーラデバイスであって、
共通のエミッタと、
前記共通のエミッタから横方向に空間を置いて、前記基板に設けられる第1のコレクタと、
前記共通のエミッタと前記第1のコレクタ間の空間上に配置される第1のゲート端子と、
前記第1のゲート端子の下部に規定され、前記共通のエミッタおよび前記第1のコレクタと第1のバイポーラ接合部を形成する第1の内部ベースと、
前記第1のコレクタと隣接し、前記第1のコレクタから隔離されると共に、前記基板を経由して前記第1の内部ベースに接続される前記第1の外部ベースと
前記共通のエミッタから横方向に空間を置いて、前記基板に設けられる第2のコレクタと、
前記共通のエミッタと前記第2のコレクタ間の空間上に配置される第2のゲート端子と、
前記第2のゲート端子の下部に規定され、前記共通のエミッタおよび前記第2のコレクタと第2のバイポーラ接合部を形成する第2の内部ベースと、
前記第2のコレクタに隣接し、前記第2のコレクタから隔離されると共に、前記基板を経由して前記第2の内部ベースに接続される第2の外部ベースと、
前記第1の外部ベースと前記第2の外部ベースから、前記第1のコレクタと前記第2のコレクタをそれぞれ隔離する第1の仕切部と第2の仕切部と、
からなることを特徴とするバイポーラデバイス。 - 前記第1の仕切部と前記第2の仕切部は、シリサイド形成を遮断するための遮断層であることを特徴とする請求項4記載のバイポーラデバイス。
- 前記第1の仕切部と前記第2の仕切部は、ダミーゲートであることを特徴とする請求項4記載のバイポーラデバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/075,141 | 2005-03-07 | ||
US11/075,141 US7723803B2 (en) | 2005-03-07 | 2005-03-07 | Bipolar device compatible with CMOS process technology |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006253686A JP2006253686A (ja) | 2006-09-21 |
JP4847163B2 true JP4847163B2 (ja) | 2011-12-28 |
Family
ID=36943340
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006061615A Active JP4847163B2 (ja) | 2005-03-07 | 2006-03-07 | Cmos製造技術と両立可能なバイポーラデバイス |
Country Status (4)
Country | Link |
---|---|
US (3) | US7723803B2 (ja) |
JP (1) | JP4847163B2 (ja) |
CN (2) | CN1838431A (ja) |
TW (1) | TWI358124B (ja) |
Families Citing this family (16)
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US8089129B2 (en) * | 2002-08-14 | 2012-01-03 | Advanced Analogic Technologies, Inc. | Isolated CMOS transistors |
US8115280B2 (en) * | 2005-10-31 | 2012-02-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Four-terminal gate-controlled LVBJTs |
US8324713B2 (en) * | 2005-10-31 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Profile design for lateral-vertical bipolar junction transistor |
US8674454B2 (en) | 2009-02-20 | 2014-03-18 | Mediatek Inc. | Lateral bipolar junction transistor |
US20100213507A1 (en) * | 2009-02-20 | 2010-08-26 | Ching-Chung Ko | Lateral bipolar junction transistor |
US8415764B2 (en) * | 2009-06-02 | 2013-04-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-voltage BJT formed using CMOS HV processes |
CN105355594B (zh) * | 2009-06-17 | 2018-11-16 | 台湾积体电路制造股份有限公司 | 集成电路结构 |
US7968971B2 (en) * | 2009-06-22 | 2011-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thin-body bipolar device |
US8450672B2 (en) * | 2009-06-30 | 2013-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS image sensors formed of logic bipolar transistors |
WO2011161795A1 (ja) * | 2010-06-24 | 2011-12-29 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
US8921194B2 (en) | 2011-11-11 | 2014-12-30 | International Business Machines Corporation | PNP bipolar junction transistor fabrication using selective epitaxy |
US8916446B2 (en) | 2011-11-11 | 2014-12-23 | International Business Machines Corporation | Bipolar junction transistor with multiple emitter fingers |
US9269609B2 (en) * | 2012-06-01 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor isolation structure with air gaps in deep trenches |
CN104157684B (zh) * | 2014-08-25 | 2017-02-08 | 株洲南车时代电气股份有限公司 | 一种沟槽栅igbt芯片 |
CN114784094A (zh) * | 2017-05-05 | 2022-07-22 | 联华电子股份有限公司 | 双极性晶体管 |
US10600894B2 (en) * | 2018-07-03 | 2020-03-24 | Qualcomm Incorporated | Bipolar junction transistor and method of fabricating the same |
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-
2005
- 2005-03-07 US US11/075,141 patent/US7723803B2/en not_active Expired - Fee Related
-
2006
- 2006-03-07 CN CNA2006100568424A patent/CN1838431A/zh active Pending
- 2006-03-07 TW TW095107533A patent/TWI358124B/zh not_active IP Right Cessation
- 2006-03-07 JP JP2006061615A patent/JP4847163B2/ja active Active
- 2006-03-07 CN CN2009101423549A patent/CN101599490B/zh not_active Expired - Fee Related
-
2010
- 2010-04-01 US US12/752,431 patent/US8049284B2/en active Active
-
2011
- 2011-09-16 US US13/234,184 patent/US8445970B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US7723803B2 (en) | 2010-05-25 |
CN101599490A (zh) | 2009-12-09 |
US20060197185A1 (en) | 2006-09-07 |
TW200633187A (en) | 2006-09-16 |
US20120007191A1 (en) | 2012-01-12 |
CN1838431A (zh) | 2006-09-27 |
US20100187637A1 (en) | 2010-07-29 |
US8049284B2 (en) | 2011-11-01 |
TWI358124B (en) | 2012-02-11 |
US8445970B2 (en) | 2013-05-21 |
JP2006253686A (ja) | 2006-09-21 |
CN101599490B (zh) | 2012-03-21 |
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