JP4836162B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit such as an SRAM in which a memory unit having a plurality of data transmission lines and a logic unit are formed on a single semiconductor chip and simultaneously performs a plurality of data processing, and particularly used for image processing and the like. The present invention relates to a SIMD type semiconductor integrated circuit.

  Conventionally, in image processing and the like for processing a large amount of data, there are many semiconductor integrated circuits in which a memory unit and a logic unit (processor) are mounted on a single semiconductor chip and processed at high speed as a dedicated processing system. It is used. As such a semiconductor integrated device, a typical SIMD (Single Instruction Multiple Data) system simultaneously processes a large amount of data from a memory unit (memory core) in parallel by a plurality of arithmetic circuits with one instruction. By executing this repeatedly, various image processing is realized.

  In order to process such a large amount of data, a large-capacity memory circuit corresponding to the large amount of data and a plurality of arithmetic circuits for processing the data are required. In order to correspond to a large capacity memory area, a plurality of small capacity memory circuits can be used. However, in that case, a control circuit is required for each of the plurality of memory circuits, which increases the chip size.

In a semiconductor integrated circuit that performs parallel processing at the same time as in the SIMD method, a word line is driven by a common driver, including the purpose of reducing the chip size, and a single unit having a plurality of data transmission lines (data input / output lines). One large-capacity memory circuit (memory unit) can be mounted. In that case, data on one word line in the memory cell array is read in parallel, and the arithmetic processing of the read data is executed in parallel.
However, in order to process a large amount of data simultaneously, it is necessary to increase the number of data input / output lines of the memory core. However, in such a case, the load in the word line direction increases, and a large time difference (delay) occurs in the word line selection time between the vicinity of the driver and the farthest end due to the wiring resistance of the word line. As a result, the read timing and write timing from the memory section differ among the plurality of data input / output lines.

  Such wiring delay due to the increase in capacity may occur in the logic part as well. That is, the wiring length and the wiring load are considerably large even if the signal for controlling a plurality of arithmetic circuits to process a large amount of data is not as large as the signal for driving the word line of the memory unit. . Therefore, a delay occurs in the data processing timing between the arithmetic circuits in the logic unit.

On the other hand, Patent Document 1 discloses a technique for simulating changes in word line resistance and bit line capacitance in a circuit constituted by a single memory for the purpose of optimizing the timing of a dynamic sense amplifier in the memory circuit. Has been.
Further, Patent Documents 2 to 4 disclose a technique in which dummy cells are used in a circuit constituted by a single memory for the purpose of reducing current consumption in an SRAM self-timing circuit.

Japanese Patent No. 10-177792 JP 2002-367377 A JP 2003-7055 A JP 2003-36678 A

  Although the conventional semiconductor integrated circuit described above can process a large amount of data simultaneously as represented by the SIMD system, the input / output timings of the memory unit (memory core) and the logic unit including the arithmetic circuit are different. Therefore, there is a problem in that it becomes difficult to control the timing to synchronize both of them because they appear as input / output signals with independent delay values.

  For example, even when the input / output data near the driver in the control signal (word line signal) of the memory core is matched with the input / output data of the arithmetic circuit corresponding thereto, the input / output data far from the driver The timing of the logic part will not match because the degree of delay of the logic part is different. On the other hand, when a setup time and a hold time are provided for each data in order to operate all the arithmetic circuits normally, the operating frequency is lowered. Such a shift in operation timing not only hinders high-speed operation, but also wastes current consumption.

  Here, a layout peculiar to the memory cell can be cited as a reason why it is difficult to synchronize the memory core and the logic unit. Usually, an arithmetic circuit is synthesized by combining basic logic gates, but in a memory circuit, a cell shape per bit is created according to a special design rule in order to increase the degree of integration. For this reason, it is difficult to make delay information into a database and handle it like other logic circuits, and the memory core itself is often handled as a black box. Although it is possible to set the timing of each input / output data in advance, it is actually difficult to set the timing accurately due to variations in the manufacturing process, etc., and an operation margin is added to each specification. It was set in.

  Although it is not a big problem if data transfer is handled at the same timing if it is a semiconductor integrated circuit that handles small-capacity data, it is simultaneously parallel in a SIMD semiconductor integrated circuit (processor) that handles large-capacity data. In order to perform processing, control must be performed so that the operation timing is matched. In a SIMD type semiconductor integrated circuit, input / output lines of a large-capacity memory circuit and input / output lines of a logic unit including an arithmetic circuit are arranged at the same pitch in layout. However, since the wiring load of each control signal is different, a method for adjusting the timing deviation of the input / output lines is required.

  In order to solve such a problem, a technique for controlling the activation timing of a sense amplifier or the like of a memory circuit by monitoring a delay component of a word line or a bit line in the memory circuit is also disclosed. In these techniques, dummy circuits in which word lines and bit lines actually used are duplicated are provided to simulate their operations. Specifically, dummy memory cells are arranged at the farthest ends of the word lines and bit lines, thereby simulating memory cell access in the critical path and controlling the activation period of the memory circuit. However, such a technique does not cause a problem for a small-capacity memory circuit in which input / output timing is uniformly defined in order to determine timing in accordance with the slowest path, but a large-capacity memory circuit In contrast, the circuit only supports the critical path.

  On the other hand, all of the above-described technologies such as Patent Literature 1 to Patent Literature 4 are those in which a dummy circuit is provided in a circuit constituted by a single memory, and the memory portion and the logic portion are on a single semiconductor chip. It does not control variations due to delays between the input / output data lines in the semiconductor integrated circuit formed in FIG.

  The present invention has been made to solve the above-described problems, and a memory unit in a semiconductor integrated circuit in which a memory unit and a logic unit are formed on a single semiconductor chip and perform a plurality of data processing simultaneously. It is an object of the present invention to provide a semiconductor integrated circuit in which the timing of data exchange between the logic unit and the logic unit is optimized to improve operation performance and operation speed and reduce current consumption.

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit in which a memory unit having a plurality of data transmission lines and a logic unit are formed on a single semiconductor chip and simultaneously perform a plurality of data processing. a is a monitor circuit for monitoring the information relating to the delay occurring between the plurality of data transmission lines in the memory unit, and a generation circuit for the phase to generate a plurality of different internal synchronous clock in accordance with the said delay The internal synchronization clock is used as a signal for adjusting the timing between the memory unit and the logic unit, the plurality of data transmission lines are a plurality of word lines and bit lines, and the monitor circuit includes the word line A dummy word line formed so as to simulate the operation of a line, and the word line is connected to a plurality of memory cells. The dummy word line is connected to a dummy memory cell that holds data fixed in advance and simulates the operation of the memory cell, and operates in reverse phase with respect to the dummy word line. A second dummy word line formed on the second dummy memory cell; a second dummy memory cell connected to the second dummy word line; an output node of the dummy memory cell; and the second dummy memory cell A precharge circuit to which an output signal from the cell is input; a second precharge circuit to which an output signal from the dummy memory cell is input while being connected to an output node of the second dummy memory cell; It is equipped with .

The semiconductor integrated circuit according to a second aspect of the present invention is the semiconductor integrated circuit according to the first aspect, wherein the generation circuit generates the internal synchronization clock in accordance with a change in rising or falling of the word line. Is.

  In a semiconductor integrated circuit in which a memory unit and a logic unit are formed on a single semiconductor chip and perform a plurality of data processing at the same time, the delay information between data transmission lines in the memory unit is monitored and the delay is reduced. In addition, an internal synchronous clock having a different phase is generated and used as a signal for timing adjustment. As a result, the timing of data exchange between the memory unit and the logic unit is optimized, so that a semiconductor integrated circuit in which operation performance and operation speed are improved and current consumption is reduced can be provided.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected to the part which is the same or it corresponds, The duplication description is simplified or abbreviate | omitted suitably.

Embodiment 1 FIG.
A first embodiment of the present invention will be described in detail with reference to FIGS. In the description of the first embodiment, FIGS. 7 and 8 relating to a conventional semiconductor integrated circuit are appropriately referred to.
FIG. 1 is a circuit diagram showing a SIMD semiconductor integrated circuit according to the first embodiment. In contrast, FIG. 7 is a circuit diagram showing a conventional SIMD type semiconductor integrated circuit. The semiconductor integrated circuit 1 according to the first embodiment is greatly different from the conventional one in that a dummy word line 12 to which a plurality of dummy memory cells 21 are connected is provided.
FIG. 2 is a timing chart showing the operation timing in the semiconductor integrated circuit of the first embodiment, and FIG. 3 is a timing chart showing the operation timing when only the logic unit operates. On the other hand, FIG. 8 is a timing chart showing the operation timing in the conventional semiconductor integrated circuit.

Referring to FIG. 1 (or FIG. 7), the SIMD semiconductor integrated circuit 1 is mainly composed of a memory unit 2 (memory core) and a logic unit 3 having a plurality of data transmission lines 11 and 13. The memory unit 2 and the logic unit 3 are connected to the decoder 6.
The SIMD semiconductor integrated circuit 1 drives a plurality of circuits with a single data transmission line (control signal line) in order to simultaneously process a large amount of data in parallel. Specifically, a plurality of memory cells 20 are connected on the word line 11 of the memory unit 2.

First, in understanding the configuration and operation of the semiconductor integrated circuit 1 according to the first embodiment, the problems of the conventional semiconductor integrated circuit 1 will be summarized with reference to FIGS. 7 and 8.
When the semiconductor integrated circuit 1 is used as an image processor, for example, 8-bit data is processed by 512 PE (processor element). In such a case, it is necessary to select 4096 memory cells at a time. That is, 4096 memory cells must be driven by one word line 11. For this reason, the wiring load on the word line 11 is very heavy and the wiring length is considerably long.
Therefore, in the conventional semiconductor integrated circuit 1 shown in FIG. 7, a time difference due to wiring delay occurs between the vicinity of the word line 11 and the farthest end, and the data transferred between the memory unit 2 and the logic unit 3 accordingly. There has been a problem that the timing at which data appears differs depending on the location.

Here, as a method of reducing the wiring load of the word line 11, a method of buffering the local wiring by dividing it into a global wiring and a local wiring is conceivable. If this method is used, the wiring load of the global wiring is reduced, so that the wiring delay can be reduced to some extent. However, since the layout size of the memory cell 20 per bit is reduced, the layout size is considerably increased when a buffer is inserted for each word line 11 in accordance with the pitch. Further, in a recent miniaturized semiconductor process, when a logic layout is inserted into the memory portion 2, a layout dummy pattern is required to stabilize the finish of the boundary region. If such a dummy pattern is inserted for each buffer of the word line 11, the layout size becomes considerably larger than that in the case of single driving of the word line 11.
Thus, in order to reduce the wiring load of the word line 11, there arises a problem that the chip size cannot be reduced. In order to realize a small area and high performance, it is necessary to match the data input / output timing in the logic unit 3 while keeping the delay component due to the location of the input / output data in the memory unit 2 as it is.

As shown in FIG. 8, the conventional semiconductor integrated circuit 1 has a problem that the delay component of the word line 11 in the memory unit 2 and the delay component of the control signal (CTREG) in the logic unit 3 are different. It was.
Specifically, the bit line 13 (BL (0), BL (m), BL (n) is caused by the local delay of the word line 11 (WL0 (0), WL0 (m), WL0 (n)) in the memory unit 2. )), The output signals (DO (0), DO (m), DO (n)) from the memory unit 2 are output at different timings. When this output signal is received by the register circuit 31 of the logic unit 3, it must be fetched in accordance with the output timing from the memory unit 2 on the register circuit 31 side. That is, it is necessary to determine the output of the memory unit 2 before the CTREG signal rises in the register circuit 31. However, if the rise of the control signal (CTREG) in the logic unit 3 is too fast, data cannot be captured depending on the location.

Referring to FIG. 8, the data output from DO (0) near decoder 6 has a quick access time output from memory unit 2, so that there is a margin for data capture in register circuit 31. However, when the farthest DO (n) from the decoder 6 is reached, the output of the data is delayed due to the delay of the word line 11, but the control signal of the register circuit 31 is faster, so the memory unit 2 The data from can not be imported.
Thus, when the timing of the control signal of the memory unit 2 and the logic unit 3 does not match and the signal of the logic unit 2 becomes faster, the logic unit 3 malfunctions due to insufficient data setup. Will be caused. If the control signal of the logic unit 3 is delayed, data from the memory unit 2 cannot be held, and erroneous writing to the logic unit 3 occurs.

The semiconductor integrated circuit 1 according to the first embodiment operates the control signal of the logic unit 3 and the word line 11 of the memory unit 2 with the same delay component in order to prevent the above-described malfunction.
Specifically, referring to FIG. 1, in semiconductor integrated circuit 1 according to the first embodiment, dummy word line 12 for simulating the operation of word line 11 is provided in memory unit 2. A plurality of dummy memory cells 21 are connected to the dummy word line 12. In the dummy memory cell 21, data is fixed in advance so that “L (low)” is output to one (DBL) of the pair of bit lines 13. A precharge circuit 22 is connected to the output node of the DBL so that its output is fixed to “H (high)” in advance.

  As described above, the semiconductor integrated circuit 1 according to the first embodiment is obtained by adding one word line (dummy word line 12) in the memory unit 2 to the conventional one (see FIG. 7). It is. Such addition corresponds to the addition of one bit of the memory cell and has almost no influence on the entire chip size.

  A signal (internal synchronization clock) output from the dummy word line 12 is supplied from the memory unit 2 to the logic unit 3 as an internal synchronization signal. The logic unit 3 is provided with selection circuits 35 and 36 for using the control signal (CTREG, CTALU) in the logic unit 3 or the synchronization signal (CKI) from the memory unit 2 depending on the application. Can be used properly. In the first embodiment, one of the signals is stopped using an OR gate as the selection circuits 35 and 36, but one of the signals is selected using a multiplexer as the selection circuit. You can also.

The operation of the semiconductor integrated circuit 1 according to the first embodiment configured as described above will be described with reference to FIG.
The word lines 11 (WL0 (0), WL0 (m), WL0 (n)) are selected fast on the side closer to the decoder 6 and delayed on the far side, as in the prior art. The dummy word line 12 (WLd) also performs the same operation as the word line 11 by simulating the operation of the word line 11.

When the dummy memory cell 21 is selected by the dummy word line 12, “L” is output to DBL. Since DBL is fixed to “H” in advance by the precharge circuit 22, CKI (which is an internal synchronization clock output from the dummy word line 12) is set to “L” in accordance with the output from the dummy memory cell 21. To “H”. This is transmitted to the logic unit 3 as an internal synchronization signal.
Thereafter, when a synchronization signal is transmitted to the logic unit 3, the data from the memory unit 2 is taken in by the logic unit 3 in accordance with the synchronization timing.

  Here, the falling edge of the internal synchronization signal is obtained when the dummy word line 12 falls and the precharge signal (PRC) in the precharge circuit 22 is enabled. At this time, the timing of the precharge signal may be synchronized with the change of the word line 11 (this will be described in another embodiment).

As described above, since the synchronization signal generated by the dummy word line 12 in which the delay of the word line 11 in the memory unit 2 is monitored is also used in the logic unit 3, the data setup time depends on the location of the input / output lines described above. The conventional problem of being different is solved. That is, the timing margin can be minimized and the operating frequency can be improved. Further, by adjusting the timing, unnecessary operations in the semiconductor integrated circuit 1 are reduced, and current consumption is reduced.
The synchronization signal supplied to the logic unit 3 is used not only for timing adjustment with the register circuit (REG) but also for timing adjustment with the arithmetic circuit 32 (ALU). It is possible to operate the arithmetic circuit 32 and the like.

  In FIG. 2, the operation of reading data from the memory unit 2 and the effect at that time have been described. However, the same effect can be obtained when a write operation from the logic unit 3 to the memory unit 2 is performed. . That is, data can be normally written in accordance with the selection period of the word line 11 of the memory unit 2 and the timing of the input data from the logic unit 3.

  As described above, in the first embodiment, the dummy word line 12 functions as a monitor circuit for monitoring information related to the delay generated in the word line 11, and the plurality of dummy memory cells 21 connected to the dummy word line 12 are It functions as a generation circuit that generates a plurality of internal synchronization clocks having different phases in accordance with the delay.

That is, the semiconductor integrated circuit 1 according to the first embodiment is a semiconductor integrated circuit that handles a large amount of data at the same time, such as a SIMD processor, and a timing shift that occurs when data is transferred between the memory unit 2 and the logic unit 3. By correcting and matching the input / output timing, the operating frequency is improved.
This is realized by generating an internal synchronous clock using a layout shape peculiar to the memory cell 20. By using this semiconductor integrated circuit 1, the timing adjustment between the memory unit 2 and the logic unit 3 is facilitated, and the operating frequency can be improved. Further, by stabilizing the operation timing, unnecessary current consumption can be reduced. Further, since the memory unit 2 is handled as one lump without being divided, the chip size can be relatively reduced.

Next, the operation timing of the semiconductor integrated circuit 1 when operating only the logic unit 3 without operating the memory unit 2 will be described with reference to FIG.
When only the logic unit 3 is operated, it is not necessary to shift the operation timing of the circuit in the processor element (PE) direction in accordance with the delay generated in the word line 11. For this reason, the internal synchronization signal (CKI) supplied from the memory unit 2 is not used. Since the logic unit 3 is provided with a pre-database logic circuit, it is easy to synchronize the register circuit 31 (REG) and the arithmetic circuit 32 (ALU). As shown in FIG. 3, when only the logic unit 3 is operated, the operation timing is adjusted in the logic unit 3. That is, the load in the control signal (CTREG, CTALU) is reduced, and the delay in the logic unit 3 is reduced. As a result, when only the logic unit 3 is operating, it is possible to operate at a higher speed than when operating including the memory unit 2.

  As described above, in the first embodiment, in the semiconductor integrated circuit 1 in which the memory unit 2 and the logic unit 3 are formed on a single semiconductor chip and simultaneously perform a plurality of data processing, the word in the memory unit 2 The delay information between the lines 11 is monitored, an internal synchronous clock having a different phase according to the delay is generated, and this is used as a signal for timing adjustment. As a result, the timing of data exchange between the memory unit 2 and the logic unit 3 is optimized, so that the operation performance and the operation speed are improved and the current consumption is reduced.

  In the first embodiment, the same number of dummy memory cells 21 as the memory cells 20 connected to the word line 11 are connected to the dummy word line 12. On the other hand, the dummy memory cell 21 can be connected to the dummy word line 12 every several bits (every predetermined interval). As a result, the memory unit 2 generates a synchronization signal every several bits. Even in such a case, since the degree of delay occurring there is not so large as long as it is between several bits, the same effect as in the first embodiment can be obtained.

Embodiment 2. FIG.
The second embodiment of the present invention will be described in detail with reference to FIG.
FIG. 4 is a circuit diagram showing the semiconductor integrated circuit 1 according to the second embodiment. The semiconductor integrated circuit 1 of the second embodiment is different from that of the first embodiment in that the logic unit 3 is provided with a dummy word line 41 as a second monitor circuit.

As shown in FIG. 4, in the second embodiment, a dummy word line 41 in which a plurality of dummy memory cells 44 are connected to the logic unit 3 is formed in the logic unit 3 in order to synchronize with the memory unit 2. Has been.
The signal output from the dummy word line 41 is supplied as an internal synchronization signal to the selection circuit 42 connected to the register circuit 31 and the selection circuit 43 connected to the arithmetic circuit 32. Each of the selection circuits 42 and 43 selects whether to use a control signal (CTREG, CTALU) or an internal synchronization signal generated by the dummy memory cell 44.

  In order to stabilize the process, it is preferable to form a dummy pattern of the layout around the dummy memory cell 44 connected to the dummy word line 41. In the second embodiment, the area is larger than when a dummy word pattern is formed in the memory unit 2 (in the case of the first embodiment), but the chip size is large and the synchronization signal is sent from the memory unit 2. This is effective for a semiconductor integrated circuit whose distance is long.

  As described above, in the second embodiment, the timing of data exchange between the memory unit 2 and the logic unit 3 is optimized, and the timing adjustment in the logic unit 3 is also optimized. Performance and operating speed are improved and current consumption is reduced.

Embodiment 3 FIG.
A third embodiment of the present invention will be described in detail with reference to FIG.
FIG. 5 is a circuit diagram showing the semiconductor integrated circuit 1 according to the third embodiment. The semiconductor integrated circuit 1 of the third embodiment is different from that of the first embodiment in that a dummy bit line 23 is formed instead of the dummy word line 12.

  As shown in FIG. 5, in the third embodiment, dummy memory cells 28 are inserted at equal intervals with respect to each word line 11 without providing dummy word lines. Specifically, a dummy memory cell 28 is provided for every m bits. The number of dummy memory cells 28 is the same as the number of word lines 11 so that one of the dummy memory cells 28 is always selected. The dummy memory cell 28 is connected to a pair of dummy bit lines 23. Here, the dummy bit line 23 (DBL) is formed so as to simulate the operation of the bit line 13 (BL). The dummy bit line 23 is connected to a dummy sense amplifier 18 that duplicates the sense amplifier 14 connected to the bit line 13.

In the semiconductor integrated circuit 1 configured as described above, when the word line 11 is first selected, the memory cell 20 is selected and data appears on the pair of bit lines 13. At the same time, the dummy memory cell 28 is also selected, and data appears on the pair of dummy bit lines 23.
The data on the bit line 13 is amplified by the sense amplifier 14 and output. In synchronization with this, an output signal detection signal is generated from the dummy sense amplifier 18. By using this as an internal synchronizing signal, not only the delay component generated in the word line 11 but also the delay component generated in the bit line 13 can be monitored. Therefore, the internal synchronization signal can be generated at a timing closer to the output signal from the memory unit 2.

In the third embodiment, dummy circuits 18, 23, and 28 are formed next to the m-th bit, and the dummy circuits 18, 23, and 28 collectively collect data from 0 bits to m bits. Are treated as
Here, if the number of m decreases, the accuracy increases. However, since the number of dummy circuits inserted increases, the chip size increases accordingly. On the other hand, if the number of m increases, it becomes difficult to adjust the timing with the logic unit 3. Since the number of divisions (m) can be easily changed, it is preferable to change the number of divisions (m) appropriately according to the application of the semiconductor integrated circuit 1 after understanding the above relationship.

  As described above, in the third embodiment, since the information related to the delay generated in the bit line 13 is monitored and the internal synchronous clock corresponding to the information is generated, the data of the memory unit 2 and the logic unit 3 is stored. The timing of exchange is optimized, so that the operating performance and the operating speed are improved and the current consumption is reduced.

  In the third embodiment, a dummy sense amplifier 18 is connected to the dummy bit line 23 to generate a timing signal at the time of reading from the memory cell 20. On the other hand, by connecting a dummy write buffer that duplicates the write buffer 15 connected to the bit line 13 to the dummy bit line 23, a signal that is synchronized with the write timing at the time of writing to the memory cell 20 can be easily obtained. Can be generated.

Embodiment 4 FIG.
A third embodiment of the present invention will be described in detail with reference to FIG.
FIG. 6 is a circuit diagram showing the semiconductor integrated circuit 1 according to the fourth embodiment. The semiconductor integrated circuit 1 of the fourth embodiment is different from that of the first embodiment in that a second dummy word line 51 is formed in addition to the dummy word line 12.

  As shown in FIG. 6, in the fourth embodiment, in addition to the dummy word line 12 (WLd) that simulates the word line 11, the second dummy word that operates in the opposite phase to the operation of the dummy word line 12. A reverse phase word line 51 (WLb) as a line is formed. Similarly to the dummy word line 12, a dummy memory cell 54 having previously fixed data is connected to the negative phase word line 51. A second precharge circuit 52 is connected to the output node of each dummy memory cell 54. The precharge circuit 22 and the second precharge circuit 52 are connected so that their respective output signals become input signals of the respective precharge circuits. With such a configuration, the signal from the dummy word line 12 is used as an internal synchronization signal, and the signal from the reverse-phase word line 51 is used as a precharge signal (PRC).

In the semiconductor integrated circuit 1 configured as described above, when the word line 11 is not selected, the reverse-phase word line 51 is selected and the precharge signal is enabled.
When the word line 11 rises, the anti-phase word line 51 falls at the same time, and the internal synchronization signal (CKI) rises as the precharge ends. On the other hand, when the word line 11 falls, the dummy memory cell 21 connected to the dummy word line 12 is deselected, and the anti-phase word line 51 is selected in accordance with that, and a precharge signal is generated. Is done. The internal synchronization signal changes from “H” to “L”. As described above, in the semiconductor integrated circuit 1 according to the fourth embodiment, the internal clock can be generated in synchronization with the rise and fall of the word line 11.

  As described above, in the fourth embodiment, since the internal synchronization clock is generated in accordance with the rise or fall of the word line 11, the timing of data exchange between the memory unit 2 and the logic unit 3 Is optimized to improve operation performance and operation speed and reduce current consumption.

  In each of the above embodiments, the present invention is applied to a 1-port SRAM as a semiconductor integrated circuit. However, the present invention is naturally applied to a multi-port semiconductor integrated circuit such as a dual-port SRAM. Can do. Furthermore, it is possible to adjust the timing with the logic unit by monitoring a delay generated in the data transmission line and generating an internal synchronous clock corresponding to the delay in the memory circuit such as a DRAM.

  It should be noted that the present invention is not limited to the above-described embodiments, and within the scope of the technical idea of the present invention, the embodiments can be modified as appropriate in addition to those suggested in the embodiments. Is clear. In addition, the number, position, shape, and the like of the constituent members are not limited to the above embodiments, and can be set to a number, position, shape, and the like that are suitable for carrying out the present invention.

1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing operation timings in the semiconductor integrated circuit of FIG. 1. FIG. 2 is a diagram illustrating operation timing when only a logic unit operates in the semiconductor integrated circuit of FIG. 1. It is a circuit diagram which shows the semiconductor integrated circuit in Embodiment 2 of this invention. It is a circuit diagram which shows the semiconductor integrated circuit in Embodiment 3 of this invention. It is a circuit diagram which shows the semiconductor integrated circuit in Embodiment 4 of this invention. It is a circuit diagram which shows the conventional semiconductor integrated circuit. It is a figure which shows the operation timing in the semiconductor integrated circuit of FIG.

Explanation of symbols

1 Semiconductor integrated circuit,
2 Memory part (memory core),
3 logic part, 6 decoder,
11 word lines,
12, 41, 51 Dummy word line,
13 bit lines, 14 sense amplifiers,
15 write buffer, 18 dummy sense amplifier,
20 memory cells,
21, 28, 44, 54 dummy memory cells,
23 Dummy bit line,
22, 45, 52 Precharge circuit,
31 register circuit, 32 arithmetic circuit,
35, 36, 42, 43 Selection circuit.

Claims (2)

A semiconductor integrated circuit in which a memory unit having a plurality of data transmission lines and a logic unit are formed on a single semiconductor chip and simultaneously perform a plurality of data processing ,
A monitor circuit for monitoring information related to a delay generated between the plurality of data transmission lines in the memory unit;
A generation circuit that generates a plurality of internal synchronization clocks having different phases in accordance with the delay;
With
Using the internal synchronization clock as a signal for adjusting the timing of the memory unit and the logic unit,
The plurality of data transmission lines are a plurality of word lines and bit lines,
The monitor circuit is a dummy word line formed to simulate the operation of the word line,
The word line is connected to a plurality of memory cells,
The dummy word line is connected to a dummy memory cell formed so as to hold data fixed in advance and simulate the operation of the memory cell,
A second dummy word line formed to operate in reverse phase with respect to the dummy word line;
A second dummy memory cell connected to the second dummy word line;
A precharge circuit connected to an output node of the dummy memory cell and to which an output signal from the second dummy memory cell is input;
And a second precharge circuit connected to an output node of the second dummy memory cell and to which an output signal from the dummy memory cell is input . The semiconductor integrated circuit according to claim 1, wherein the generation circuit generates the internal synchronization clock in accordance with a change in rising or falling of the word line.

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