JP4812256B2 - Liquid crystal display - Google Patents

Description

    The present invention relates to a liquid crystal display device, and particularly to a device capable of high-speed driving.

  Conventionally, a TN liquid crystal display element has been generally used as the liquid crystal display element. However, since the response speed of the TN liquid crystal display device is slow, an OCB type display device has been studied as a liquid crystal display device capable of high-speed response. Refer to Non-Patent Document 1 for details of this OCB type liquid crystal display device.

In this OCB type liquid crystal display device, liquid crystal is sandwiched between substrates, and a transparent electrode is formed on the inner surface of the substrate. In the state before the power is turned on, the alignment state of the liquid crystal is a state called splay alignment. Then, when the power of the liquid crystal display device is turned on, a relatively large voltage is applied to the transparent electrode in a short time to shift the liquid crystal alignment to the bend alignment state. Displaying using this bend alignment state is a feature of the OCB type liquid crystal display mode, which enables high-speed response.
IEICE Technical Report EDI98-144 199 pages

  By the way, the problem of the HOLD type display device is “The 142th Committee of Organic Materials for Information Science, A Group (Liquid Crystal Materials) 71st Study Group, B Group (Intelligent Organic Materials) 62nd Study Group” On November 20, 2012, the Japan Society for the Promotion of Science, pages 1 to 5 ”pointed out that a technology for realizing a moving image equivalent to a CRT on a liquid crystal display was suggested. The simplest of these techniques is to write the screen at high speed and periodically insert a black screen. In this specification, the methods for performing the screen writing time in a short time as described above are collectively referred to as “high-speed driving”.

  However, although the OCB type liquid crystal display device can respond at high speed, there has been a problem that the OCB type liquid crystal display device has not yet been able to sufficiently cope with the high speed driving.

  The present invention has been made to solve such problems, and an object of the present invention is to provide a liquid crystal display device capable of high-speed driving.

In order to solve the above problems, a liquid crystal display device according to the present invention includes a liquid crystal layer capable of bend alignment, and a display screen including a plurality of pixels that display an image by light transmitted through the bend-aligned liquid crystal layer, Pixel voltage application means for sequentially applying a pixel voltage to the liquid crystal layers of all the pixels corresponding to the luminance information for each pixel of the image information, and changing the light transmittance by applying the pixel voltage. A liquid crystal display device for displaying an image corresponding to the image information on the display screen, comprising gate driving means for sequentially scanning the plurality of pixels through a gate electrode, and the pixel voltage applying means is scanned. Source driving means for applying a base voltage based on the luminance information of the pixel of the image information to the liquid crystal layer of the pixel through the source electrode; After the scanning, an offset voltage is applied to the pixel together with the base voltage to form the pixel voltage through the capacitive coupling formed between the liquid crystal layer and the liquid crystal layer to prevent reverse transition from bend alignment to splay alignment. It may have an offset voltage applying means .

With such a configuration, the offset voltage can be applied without limiting the application size depending on the charge capacity of the liquid crystal panel as in the case of applying the offset voltage by changing the counter electrode. In addition, by configuring the pixel voltage to change transiently, an offset voltage can be applied using CC driving, so that the speed can be significantly increased and the configuration for applying the offset voltage is simplified. A liquid crystal display device can be obtained. Further, with such a configuration, the offset voltage can be applied using the gate electrode, so that the configuration of the offset voltage applying means is simplified.

Further, a liquid crystal layer capable of bend alignment, a display screen including a plurality of pixels for displaying an image by light transmitted through the bend-aligned liquid crystal layer, and a pixel voltage corresponding to luminance information for each pixel of the image information. A liquid crystal display for displaying an image corresponding to the image information on the display screen by changing the transmittance of the light by applying the pixel voltage to the liquid crystal layer of all the pixels. In the display device, the pixel voltage application means forms the pixel voltage together with a voltage applied to the liquid crystal layer of the pixel during the sequential application, and after the sequential application, the pixel voltage application unit An offset voltage for preventing reverse transition from the bend alignment to the splay alignment of the liquid crystal layer may be applied to the pixel through capacitive coupling formed between the capacitor line and the capacitor line. (Claim 2).

The offset voltage may be 1 v or more (claim 3 ).

  With this configuration, it is possible to prevent reverse transition from bend alignment to splay alignment in a general OCB type liquid crystal panel.

Further, the offset voltage may be those above the reverse transition voltage from the bend alignment to the splay alignment of the liquid crystal layer (claim 4).

  With this configuration, reverse transition from bend alignment to splay alignment can be prevented.

Moreover, in its period is a field period for writing the image information for one field at a predetermined period, a substantially black screen may be made is configured to be displayed on the display screen (Claim 5).

  With such a configuration, it is possible to reduce the necessary offset voltage and improve the interruption of moving image display.

  According to the present invention, there is an effect that it is possible to obtain a liquid crystal display device that can support high-speed driving.

  Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1
1 is a block diagram showing the configuration of the liquid crystal display device according to Embodiment 1 of the present invention, FIG. 2 is a cross-sectional view schematically showing the configuration of the liquid crystal display element of FIG. 1, and FIG. 3 is the liquid crystal display element of FIG. FIG. 4 is a cross-sectional view schematically showing the configuration of the auxiliary capacitance electrode, and FIG. 5 is a circuit diagram showing an equivalent circuit of the pixel.

  As shown in FIG. 1, the liquid crystal display device 1 includes a liquid crystal display element (liquid crystal panel) 106, a backlight 18, and a display control circuit 19, and displays light from the backlight 18 to the liquid crystal display element 106. And the display control circuit 19 drives the liquid crystal display element 106 to transmit display light according to the video signal 14, whereby an image corresponding to the video signal 14 is displayed on the liquid crystal display element 106. It is configured as follows.

  The backlight 18 supplies light for display from the light source 15 driven by the lighting circuit 16 to the liquid crystal display element 106 through a light guide plate (not shown).

  The display control circuit 19 includes a display controller 13, a gate driver 11, a source driver 12, and an illumination controller 17. The display controller 13 outputs control signals to the gate driver 11, the source driver 12, and the illumination controller 17 according to the video signal 14, respectively. In response to the control signal, the gate driver 11 outputs a gate signal through the gate electrode 2 to sequentially scan (select) the pixels of the liquid crystal display element 106 for each gate electrode 2. The source driver 12 sequentially writes the source signal to the scanned pixels through the source electrode 3 by outputting the source signal in time with the gate signal in accordance with the control signal. Thereby, the transmittance of each pixel with respect to the display light changes in accordance with the source signal, whereby an image corresponding to the video signal 14 is displayed on the liquid crystal display element 106. The illumination controller 17 controls the driving of the light source 15 by the lighting circuit 16 in accordance with a control signal from the display controller 13.

  As shown in FIG. 2, the liquid crystal display element 106 is formed of an active matrix type here, and a liquid crystal 103 is sandwiched between a counter substrate 101 and a TFT substrate 102 arranged so as to face each other. A phase difference plate 104 and a polarizing plate 105 are arranged in this order on the outside of the substrates 101 and 102, respectively. A counter electrode 8 (see FIG. 4) is formed on the inner surface of the counter substrate 101, and an alignment film (not shown) is formed on the surface of the counter electrode 8. Referring also to FIG. 3, a gate electrode 2, a source electrode 3, a pixel electrode 6 and the like are formed on the inner surface of the TFT substrate 102, and an alignment film (not shown) is formed so as to cover them. Yes. The alignment films of both substrates 101 and 102 are rubbed in directions parallel to each other. FIG. 2 shows a cross section parallel to the rubbing direction. A nematic liquid crystal is used as the liquid crystal. That is, the liquid crystal display element 106 employs the OCB liquid crystal mode. In this OCB liquid crystal mode, in the initial state where no voltage is applied, the liquid crystal has a splay alignment in which molecules are arranged almost in parallel. However, when a relatively large voltage, for example, a voltage of about 25 V is applied thereto, the liquid crystal is in a display state. Transition to bend orientation. FIG. 2 shows this bend alignment state.

  As shown in FIG. 3, a plurality of linear gate electrodes 2 and a plurality of linear source electrodes 3 are formed on the inner surface of the TFT substrate 102 so as to be orthogonal to each other. Regions partitioned in a matrix form the pixels 4. An area composed of a set of all the pixels 4 forms a display screen (not shown). Each pixel 4 is provided with a pixel electrode 6, and a switching element 5 made of a TFT (Thin Film Transistor) is formed for each pixel 4. The switching element 5 has a source and a drain connected to the source electrode 3 and the pixel electrode 6, respectively, and a gate connected to the gate electrode 2. A gate signal is sequentially output from the upper side to the lower side of FIG. 3 to the gate electrode 2, whereby the pixels connected to each gate electrode 2 are sequentially scanned for each gate electrode 2. Hereinafter, the front and rear in the scanning order are referred to as a front stage and a rear stage. In each pixel 4, an auxiliary capacitance electrode 7 is disposed so as to be capacitively coupled to the gate electrode 2 on the previous stage side, and is connected to the pixel electrode 6. That is, the liquid crystal display element 106 employs a so-called capacitive coupling driving method (hereinafter referred to as CC driving). For details of this CC drive, refer to Japanese Patent Laid-Open No. 2-157815 or page 59 of AM-LCD95 Digest of Technical papers. Specifically, as shown in FIG. 4, the gate electrode 2 is formed on the TFT substrate 102, and the insulating layer 9 is formed so as to cover the surface of the TFT substrate 102 on which the gate electrode 2 is formed. Then, a pixel electrode 6 is formed so as to cover a portion of the insulating layer 9 located in the pixel, and a portion of the insulating layer 9 located on the gate electrode 2 and an edge of the pixel electrode 6 adjacent thereto are formed. An insulating layer 10 is formed so as to cover it. An auxiliary capacitance electrode 7 is formed on the insulating layer 10 and connected to the pixel electrode 6 on the rear stage side by a contact hole 41. By adopting such a structure, the equivalent circuit of the pixel 4 has a switching element 5 connected to the source electrode 3 and a liquid crystal capacitor Clc between the switching element 5 and the counter electrode 8 as shown in FIG. An auxiliary capacitor Cst is connected between the switching element 5 and the previous gate electrode 2. Cgd indicates the stray capacitance between the pixel electrode 6 and the gate electrode 2.

  Next, the operation of the liquid crystal display device 1 configured as described above will be described.

  6 is a graph showing the potential of the gate signal, the source signal, and the counter electrode, FIG. 7 is a graph showing the relationship between the change in the gate signal and the change in the pixel voltage, and (a) shows the change in the odd field. (B) is a figure which shows the change in an even-numbered field.

  As shown in FIGS. 1 and 6, the potential of the counter electrode (hereinafter referred to as counter voltage) Vcom is set constant. On the other hand, the liquid crystal display element 106 is AC driven. That is, the source driver 12 outputs a source signal Ss that alternately takes positive and negative values for each pixel connected to the same source electrode 3 with respect to the counter voltage Vcom. Further, the polarity of the source signal Ss with respect to the counter voltage Vcom is inverted for each screen, that is, for each field. In the present embodiment, the counter voltage Vcom is set to 3v. Further, the amplitude (base voltage) Vs of the source signal Ss is set to 3v, and therefore the source signal Ss alternately takes values of 6v and 0v.

  On the other hand, the gate driver 11 outputs the following gate signal Sg. That is, the gate signal Sg becomes Vgon in the writing period Ta, and in the accumulation period Tp following the writing period Ta, becomes Vge1 in the odd field, Vge2 in the even field, and excludes the writing period Ta and the accumulation period Tp. Vg0ff for the remaining period Tr. Here, Vge1 is set to a voltage higher than Vg0ff by Vge (+), and Vge2 is set to a voltage lower than Vg0ff by Vge (−). In addition to Vg2, Vge1 is set to such a voltage that the switching element 5 is cut off (high resistance state). Further, the accumulation period Tp is set to a period slightly more than twice the writing period. In this embodiment, Vgon of the gate signal Sg is set to a positive predetermined value, Vgoff is set to −10v, Vge1 is set to −3v, Vge (+) is set to 7v, Vge2 is set to −18v, and Vge (−) is set to −8v. ing.

  As a result, in any pixel, as shown in FIGS. 3 and 7, in the writing period Ta, the switching element 5 becomes conductive (low resistance state), and the pixel electrode 6 is charged to the voltage Vs of the source signal Ss. The Thereby, the source signal Ss is written to the pixel 4. Here, in the case of the odd field, here, the pixel voltage Vp ′ changes from positive to negative. In this case, as shown in FIG. 7A, when the source signal Ss is written to the pixel 4, A voltage Vge1 is applied to the gate electrode 2 on the front stage side. In addition, a voltage smaller than a voltage (a set pixel voltage Vp described later) that is originally applied to the liquid crystal is applied to the pixel electrode 6. Next, when the accumulation period Tp is entered, the voltage of the gate electrode 3 at that stage drops to Vge2, thereby switching the switching element 5 into a cut-off state. On the other hand, the voltage of the gate electrode 3 on the preceding stage is lowered to Vgoff. That is, Vge (+) is lowered. Then, since the switching element 5 is in the cut-off state and the pixel electrode 6 is coupled to the gate electrode 3 on the previous stage side by the auxiliary capacitor Cst, the potential of the pixel electrode 6 is lowered in conjunction with the voltage of the gate electrode 3. . This amount of voltage change (hereinafter referred to as compensation voltage or accumulated voltage) Vcc has a value as shown in an expression described later.

  In the case of an even field, the pixel voltage Vp ′ changes from negative to positive here. In this case, when the source signal Ss is written in the pixel 4, as shown in FIG. A voltage of Vge2 is applied to the side gate electrode 2. Next, when the accumulation period Tp is entered, the voltage of the gate electrode 3 at the corresponding stage is lowered to Vge1, whereby the switching element 5 is cut off. On the other hand, the voltage of the gate electrode 3 on the preceding stage rises to Vgoff. That is, Vge (-) is increased. Then, the potential of the pixel electrode 6 increases by the compensation voltage Vcc in conjunction with the voltage of the gate electrode 3. In this case and the above case, the compensation voltage Vcc is expressed by the following equation.

Vcc = Cst / (Cst + Cgd + Clc) x (Vge (+) or Vge (-))
Usually, the pixel electrode 6 has a voltage in anticipation of the compensation voltage Vcc, that is,
Vp '= Vs + Vcc
Is designed to be applied.

  The driving method of such a liquid crystal display element is CC driving. It is known that when this CC drive is used, the response speed of the TN liquid crystal is increased to some extent. This is due to the dielectric anisotropy.

  Consider a case where the transmittance of a liquid crystal display element (hereinafter simply referred to as transmittance) changes from 100% to 0% in an arbitrary pixel. The display mode is assumed to be a normally white mode. Then, when the transmittance is 100%, the voltage applied to the liquid crystal is low, and the dielectric constant of the liquid crystal is small. Conversely, when the transmittance is 0%, the voltage applied to the liquid crystal is high and the dielectric constant is large.

  Since the response of the liquid crystal molecules requires more time than the charging of the pixel electrode, a time delay occurs with respect to the charging of the pixel electrode (writing of the source signal).

The voltage (hereinafter referred to as pixel voltage) Vp ′ applied to the pixel electrode at the beginning of charging (exactly immediately after the end of the writing period) is
Vp ′ (initial value) = Vs + Cst / (Cst + Cgd + Clc (100)) × Vge (+)
But this is due to the response of the liquid crystal,
Vp ′ (saturation value) = Vs + Cst / (Cst + Cgd + Clc (0)) × Vge (+)
To change.

Here, Clc (100) is the liquid crystal capacity when the transmittance is 100%, and Clc (0) is the liquid crystal capacity when the transmittance is 0%. In this liquid crystal capacity,
Clc (100) <Clc (0)
Because there is a relationship
Vp '(initial value)>Vp' (saturation value)
It becomes a relationship.

  In this case, Vp ′ (saturation value) is the voltage that should be originally applied to the pixel electrode 6, that is, the set pixel voltage Vp. The set pixel voltage Vp is a voltage corresponding to luminance information (gradation) for each pixel of the video signal.

  Here, since the transmittance changes from 100% to 0%, the voltage applied to the liquid crystal changes from a low state to a large state. At that time, since a high voltage such as Vp ′ (initial value) is applied to the liquid crystal at the beginning of charging, the response speed of the liquid crystal is increased by this transient high voltage. The

  On the other hand, when the transmittance changes from a low and dark state to a relatively bright halftone state where the transmittance is relatively high and relatively bright, the voltage applied to the liquid crystal is relatively high to relatively low. Change to state. However, in this case, since the relationship of Vp ′ (initial value) <Vp ′ (saturation value) is established, a low voltage of Vp ′ (initial value) is transiently applied to the liquid crystal at the beginning of charging. . Accordingly, also in this case, the response speed of the liquid crystal is increased.

  Next, in order to clarify the characteristics of the present invention, the present invention will be described in comparison with a normal driving method (hereinafter simply referred to as normal driving).

  FIG. 8 is a circuit diagram showing an equivalent circuit of a pixel in normal driving, FIG. 9 is a graph for explaining a change in the transmittance of the pixel by normal driving, (a) shows a gate signal, and (b) ) Is a graph showing the change in the pixel voltage, (c) is a graph showing the change in the pixel voltage during the transition from the writing period to the holding period, (d) is a graph showing the change in the dielectric constant of the liquid crystal in the pixel, (e FIG. 10 is a graph for explaining the change in the transmittance of the pixel according to this embodiment, (a) is a diagram showing the gate signal, and (b) is the pixel. Graph showing change in voltage, (c) is a graph showing change in pixel voltage at the time of transition from the writing period to the holding period, (d) is a graph showing change in dielectric constant of liquid crystal in the pixel, (e) in the pixel It is a graph which shows the change of the transmittance | permeability.

  First, in normal driving, as shown in FIG. 8, the auxiliary capacitance electrode is disposed so as to be capacitively coupled to a capacitance line (not shown), and the capacitance line is connected to the counter electrode 8. As a result, the equivalent circuit of the pixel is such that the auxiliary capacitor Cst is connected in parallel with the liquid crystal capacitor Clc.

  The normal drive operation will be described. Here, a case where the voltage (pixel voltage vp ′) applied to the liquid crystal changes rapidly from a high state to a low state will be described. As shown in FIGS. 9A and 9C, when the gate signal is output to the pixel, the switching element becomes conductive in the writing period Ta in which the voltage is high, and the pixel electrode becomes the source signal voltage. Charged. The writing period Ta has a value of 20 μs, for example, and is extremely short. However, the response time of the liquid crystal molecules is a value on the order of several ms even if the liquid crystal is in the OCB mode, and is longer than the charging time. As described above, since the dielectric constant of the liquid crystal changes according to the response of the liquid crystal molecules, this response is also slow. Therefore, at the initial stage of charging, the voltage applied to the liquid crystal, that is, the pixel voltage Vp ′ changes as shown in FIG. 9B, and the dielectric constant of the liquid crystal at this time is as shown in FIG. 9D. In addition, it remains in a high state at high voltage. Next, when the switching element enters a cut-off state and shifts to the holding period, liquid crystal molecules respond, and the dielectric constant changes accordingly. Due to this change in dielectric constant, charge redistribution occurs, and the pixel voltage Vp ′ changes as shown in FIGS. 9B and 9C. Thereby, the pixel voltage Vp ′ becomes a value deviated from the set pixel voltage Vp. As a result, as shown in FIG. 9 (e), the transmittance gradually changes over many fields over one field period Tf. That is, the response of the liquid crystal is slow. Here, the pixel voltage Vp ′ is represented by the following equation.

Vp '= (Cst + Clc (0)) / (Cst + Clc (100)) × Vp
That is, in normal driving, the pixel voltage Vp ′ is changed so that the change in the dielectric constant of the liquid crystal impairs the response of the liquid crystal.

  Therefore, in the present embodiment, the pixel voltage Vp ′ is changed so that the change in the dielectric constant of the liquid crystal increases the response speed of the liquid crystal. That is, as shown in FIG. 10A, the point that the gate signal is pulsed is the same as in the normal drive, but as shown in FIG. 10B, the initial period of the holding period Th immediately after the end of the writing period Ta. In addition, the above-described compensation voltage Vcc is applied from the gate electrode to the pixel electrode via the auxiliary capacitor Cst. At this time, the dielectric constant of the liquid crystal also changes slowly as shown in FIG. 10 (d), and as a result, the compensation voltage Vcc changes as shown in FIG. 10 (b). The change in the compensation voltage Vcc accompanying the change in the rate acts to accelerate the response of the liquid crystal. Therefore, as shown in FIG. 10 (e), the transmittance does not slow down the response, but rather changes at such a speed as to temporarily overshoot. This also has the effect of highlighting the change in transmittance. As a result, the liquid crystal can finish the response within one screen, that is, within one field period Tf.

  As described above, it is a feature of the present invention that the compensation voltage is applied in a direction that accelerates the response, and further, CC driving is performed by automatically applying the compensation voltage using the change in the liquid crystal capacitance.

  Next, effects of the liquid crystal display device according to the present embodiment will be described. The OCB liquid crystal mode is characterized by high speed, but in normal driving, response within one field is difficult even with the OCB liquid crystal mode. This is because there was an inhibitory effect due to a change in dielectric constant as described above. Therefore, in the present invention, by combining the OCB liquid crystal mode and the CC drive, a response within one field period can be realized with certainty.

  FIG. 11 is a graph showing the response speed between gradations of the liquid crystal display device, FIG. 12 is a table showing rise time and decay time between gradations, and FIG. 11A shows the case of the OCB liquid crystal mode of normal driving. Table (b) is a table showing a case of CC-driven OCB liquid crystal mode, and (c) is a table showing a case of CC-driven TN liquid crystal mode.

  As shown in FIG. 12, in order to confirm the effect of the liquid crystal display device according to the present embodiment, a normal drive OCB liquid crystal mode, a CC drive OCB liquid crystal mode (this embodiment), and a CC drive TN liquid crystal For the mode, Rise time and Decay time between each gradation were measured. This measurement was performed at room temperature in the normal driving OCB liquid crystal mode, and at 32 ° C. in the CC driving OCB liquid crystal mode and CC driving TN liquid crystal mode. In each table of FIGS. 12A, 12B, and 12C, the upper right half indicates Decay time (τd), and the lower left half indicates Rise time (τr). The numerical value representing the level of each gradation represents the percentage when the black display level in the screen brightness is 0 and the white display level is 100. In order to make this measurement result easy to understand, FIG. 11 shows a graph of the response speed with respect to the target gradation. Here, the target gradation means two gradations that are response speed calculation targets. The response speed means the sum of the rise time from one of the two gradations to the other and the decay time from the other. In a liquid crystal display device, the response speed is usually expressed as the sum of rise time and decay time. As a specific example, in the normal driving OCB liquid crystal mode (FIG. 12 (a)), when the target gradation is 0 level and 25 level (represented as 0-25 in FIG. 11), The response speed is 0.92 (τr) +3.2 (τd) = 4.12 [ms].

  In FIG. 11, the characteristic of the OCB liquid crystal mode of normal driving is indicated by a curve B. As is apparent from the curve B, the response speed of the normally driven OCB liquid crystal mode has to be said to be slow in practical use at intermediate gray levels. In other words, it is necessary to insert a black screen in order to produce a moving picture similar to a CRT. To that end, a video signal is written at a frequency faster than the normal field frequency of 60 Hz, and the black screen is displayed in a surplus time. Need to be inserted. If possible, it is desirable to set the black screen insertion time to at least half of one field period in order to produce the necessary moving picture cuts. In order to realize this, it is necessary to write a video signal at a frequency of 120 Hz. There is. For this purpose, it is necessary to realize a response speed of 8 ms or less. Further, when the liquid crystal display element is interlocked with the backlight, or when it is intended to realize a high-speed response even at a low temperature, higher speed is required. In this specification, writing a video signal at a frequency of 120 Hz is particularly called “double speed driving”.

  On the other hand, in the normally driven OCB liquid crystal mode, the response speed between gradations was 12.8 ms at the maximum. Accordingly, it is possible to partially support not only writing of a video signal at a normal field frequency of 60 Hz but also “high-speed driving”, but writing of a video signal at 120 Hz capable of displaying a sharp moving image, that is, , "Double speed drive" cannot be supported at all, and cannot be put to practical use in applications such as televisions and monitors.

  On the other hand, the characteristic of the OCB liquid crystal mode of the CC drive is shown by a curve A in FIG. 11. As is clear from this curve A, the response speed between gradations is a maximum of 6 ms or less (more precisely, 5.4 ms). Below). This response speed is less than half that of the normal driving OCB liquid crystal mode, and 8 ms corresponding to a video signal writing period (hereinafter referred to as an image information writing period) having a frequency of 120 Hz capable of displaying a sharp moving image. It was well below. Therefore, the liquid crystal display device according to the present embodiment can perform not only “high speed driving” but also “double speed driving”, and as a result, the response speed can be sufficiently put to practical use in applications such as televisions and monitors. It has become. That is, for the first time, the liquid crystal display device of this embodiment has made it possible to display a practical moving image at a response speed.

  The characteristic of the normally driven TN liquid crystal mode that is widely used at present is shown by a curve C in FIG. 11. In this liquid crystal mode, the gray scale that can respond in a time shorter than the normal 60 Hz frequency field period. The range is extremely small, and not only “double speed driving” but also “high speed driving” cannot be sufficiently handled. Therefore, the response speed is insufficient to display a moving image.

  FIG. 13 is a three-dimensional graph visually showing Rise time and Decay time between gradations, where (a) is a table showing the case of the CC drive OCB liquid crystal mode, and (b) is the normal drive OCB liquid crystal mode. It is a table | surface which shows a case.

  FIG. 13 shows the measurement of Rise time and Decay time between gradations with finer step increments than the measurement of FIG. The level of each gradation is represented at a stage in the screen brightness when black display is 0 and white display is 255.

  As is clear from FIG. 13, the OC drive liquid crystal mode of CC drive has a higher effect than the normal drive OCB liquid crystal mode particularly in the decay time, that is, the response time in the direction in which the liquid crystal is relaxed. In the CC-driven OCB liquid crystal mode, the response time is about 3 ms or less between all gradations. When this is seen in response speed (τr + τd), it is 6 ms or less. Furthermore, the difference in gradation is much smaller than that in the normal driving OCB liquid crystal mode. This is because the largest compensation voltage is automatically applied to the pixel electrode at the time of the change from the black display level to the white display level where the response becomes the slowest. As described above, even when the gradation level is made finer, the liquid crystal display device according to the present embodiment has a response speed that can be practically used for televisions, monitors, and the like.

  Next, temperature characteristics of the liquid crystal display device according to the present embodiment will be described. In the CC-driven OCB liquid crystal mode, the low temperature limit at which “double speed driving” is possible was 10 ° C. However, the temperature of 10 ° C. indicates the temperature of the liquid crystal display element warmed by a backlight or the like, and the environmental temperature in this case was 0 ° C. Therefore, the liquid crystal display device according to the present embodiment can realize sufficiently good “double speed driving” even at room temperature or lower. In the normal drive OCB liquid crystal mode, the low temperature limit at which a field frequency of 60 Hz can be driven is 25 ° C., and even a field frequency of 60 Hz is difficult at a temperature lower than that.

  Next, preferable conditions of the present embodiment will be described. The speeding up by CC driving is brought about by the superposition of the compensation voltage Vcc and the change in the pixel voltage Vp ′ due to the dielectric anisotropy as described above. Therefore, it is preferable that the dielectric anisotropy is large. In this embodiment, a liquid crystal material having a dielectric constant of 11 under all voltages, 5 under no voltage, 10 under black display voltage, and 7 under white display voltage is used. An important parameter in selecting the liquid crystal material is the ratio between the dielectric constant under the black display voltage and the dielectric constant under the white display voltage (hereinafter referred to as the dielectric ratio), and the larger this is, the more effective. In the present embodiment, a liquid crystal material having a dielectric ratio of 1.4 is used. If this dielectric ratio is 1.2 or more, the effect of speeding up appears, and if it is 1.4 or more, it can be applied to “double speed driving” in which the frequency of the image information writing period is 120 Hz. A TN liquid crystal usually has a dielectric ratio of 2 or more. However, since an OCB liquid crystal is used in a state where molecules are considerably standing even during white display, the dielectric ratio is small. This is a major limitation in selecting a liquid crystal material. However, in the present embodiment, the dielectric ratio is improved by selecting a liquid crystal material having a large dielectric anisotropy. The dielectric constant of the liquid crystal material used in this embodiment is ε vertical = 3.7 and ε parallel = 11.5. Therefore, the dielectric anisotropy Δε = ε parallel−ε vertical = 7.8. Regarding the selection of this liquid crystal material, if Δε> 6.5 or more, the dielectric ratio becomes 1.2 or more, and the effect of speeding up appears. If Δε> 7.7 or more, the dielectric ratio is 1.4 or more. This was applicable to “double speed drive”.

  Another important parameter in CC driving is the ratio of the auxiliary capacitance Cst to the liquid crystal capacitance Clc, and the larger the auxiliary capacitance Cst, the more effective. In the present embodiment, this capacity ratio = Cst / Clc is set to 1. In order to achieve the effect of speeding up, it is preferable to set the capacity ratio to 0.7 or more. Further, in order to apply to “double speed driving”, it is preferable to set this capacity ratio to 1 or more.

  As described above, according to the present embodiment, the response time of the liquid crystal display element can be reduced to ½ or less of the conventional driving method. This is a very large effect considering the TN liquid crystal mode empirical rule. This is considered to be due to the fact that the amount of variation in the amount of transmitted light with respect to the change in dielectric constant of the liquid crystal is large in the OCB liquid crystal mode. In other words, the effect of this embodiment is not simply the sum of the speed-up effect by CC driving and the speed-up effect by OCB liquid crystal mode, but the configuration of CC driving and the above characteristics of OCB liquid crystal mode match. This is thought to be due to the synergistic effect of both. It was also confirmed that this speed-up effect can be further improved by increasing the anisotropy of the dielectric constant.

  Next, a modification of the present embodiment will be described.

[Modification 1]
The method of supplying the compensation voltage to the pixel electrode is not limited to the pre-stage side gate method. The compensation voltage may basically be supplied from an electrode capacitively coupled to the pixel electrode.

  FIG. 14 is a plan view showing the configuration of a capacitor line according to this modification, and FIG. 15 is a cross-sectional view taken along the line XV-XV in FIG. As shown in FIG. 14, in this modification, an independent capacitance line 31 is formed on the inner surface of the TFT substrate 102 in parallel with the gate electrode 2. The capacitor line 31 is formed corresponding to each gate electrode 2. As shown in FIG. 15, the capacitor line is formed on the TFT substrate 102 so as to be covered with the insulating layer 9, and the pixel electrode 6 is formed on the insulating layer 9. Therefore, an auxiliary capacitor is formed between the pixel electrode 6 and the portion 31 a located below the pixel electrode 6 of the capacitor line 31. In general, a general capacity line is connected to the counter electrode 8, but the capacity line 31 is connected to a dedicated driver (not shown). This is because a predetermined voltage must be applied to the capacitor line 31 in synchronization with the scanning of the gate electrode 2, and the capacitor line 31 needs to be driven independently. As a result, the number of drivers on the gate side increases, but by forming these drivers with polysilicon, the burden due to the increase in the number of drivers is reduced. A voltage corresponding to Vg (+) and Vg (−) applied to the front gate electrode in FIG. 6 is applied to the capacitor line 31 by the dedicated driver at the same timing as in FIG. Thereby, the same effect as in the case of FIG. 6 is obtained.

[Modification 2]
In the above configuration example, the compensation voltage is automatically superimposed by supplying the compensation voltage from the capacitively coupled gate electrode. However, the essence of the present invention is that the compensation voltage is applied to the transmittance of the liquid crystal display element. Therefore, it is possible to realize this without using the capacitive coupling described above. Therefore, in this modification, such a compensation voltage application circuit is configured.

  FIG. 16 shows the configuration of a compensation voltage applying device according to this modification. In FIG. 16, the compensation voltage applying device 30 includes, for example, a plurality (two in this case) of field memories 32 and 33, and image information for one screen (one field) that precedes and follows the video signal 14, respectively. The difference calculation circuit 34 calculates the difference between the gradations (luminance information) of the pixels of the image information stored in the field memories 32 and 33, and the compensation voltage generation circuit 35 corresponds to the difference between the gradations. A voltage (source signal) obtained by superimposing the compensation voltage on the base voltage (the voltage Vs of the source signal in FIG. 6) based on the gradation of the pixel in the subsequent field of the video signal 14 in the source driver 12 in the source driver 12. Is supplied to the liquid crystal display element 106. At present, since a large amount of calculation is required to calculate the difference in gradation of each pixel between fields, it is difficult to realize this in terms of calculation speed. However, in the near future, it is expected that the size and speed of the semiconductor will be increased to such an extent that it can be processed in the controller chip. If so, it will be possible to realize this configuration.

[Modification 3]
According to the present embodiment, it is possible to further increase the speed by adopting the CC drive OCB liquid crystal mode. However, in this modification, this configuration is combined with a configuration in which a black screen is inserted in the field period. It is. With such a configuration, a moving image is cut off, that is, visibility is improved. Here, in this specification, the field period means a period of writing image information (here, a video signal) for one screen at a constant period. In addition, a period in which image information for one screen is sequentially written in all pixels in the field period is referred to as an image information writing period. In addition, a period during which the black screen is written in the field period is referred to as a black screen insertion period. This modification is effective when the image information writing time is less than 90% of the field period. For example, when the black screen insertion period is set to 10% or more of the field period, the liquid crystal hardly returns to the splay alignment, that is, there is an effect of preventing reverse transition. Further, when the image information writing period is set to be half or less of the field period, the remaining period can be set as the black screen insertion period, so that the visibility can be further improved. The black screen display voltage may be either a black level voltage or a substantially black voltage, or a voltage equal to or higher than the black level.

[Modification 4]
In this modification, the backlight is turned off during the black screen insertion period within the field period. Specifically, in the configuration of FIG. 1, the lighting controller 17 controls the lighting circuit 16 to turn off the light source 15 over the entire period of the black screen insertion period. With such a configuration, it is possible to achieve both improvement in visibility and reduction in power consumption due to insertion of a black screen.

[Modification 5]
In this modification, the cell thickness is 3 μm or less in a CC-driven TN liquid crystal display device. With such a configuration, the electric field strength generated in the liquid crystal increases as the cell thickness decreases, thereby enabling high-speed response. In particular, when the cell thickness is 3 μm or less, “double speed driving” was possible as in the case of the CC driving OCB liquid crystal mode. In this configuration, it is needless to say that the response speed can be further increased by selecting the liquid crystal material in the same manner as described above with respect to the dielectric anisotropy and the dielectric ratio.

Embodiment 2
The CC drive used in the first embodiment has an advantage that the drive voltage can be optimized in addition to the high speed. Therefore, in the second embodiment of the present invention, an offset voltage is applied using this CC drive.

  FIG. 17 is a pixel voltage-transmittance graph showing the setting of the offset voltage in the liquid crystal display device according to the present embodiment.

  The overall configuration of the liquid crystal display device according to the present embodiment is the same as that of the first embodiment. However, in the present embodiment, unlike the first embodiment, the value of the compensation voltage (hereinafter referred to as the accumulated voltage) Vcc in FIG. 7 is set to a value that allows for the offset voltage. Here, the offset voltage is a voltage applied to bend-aligned liquid crystal for the purpose of preventing reverse transition to splay alignment as shown in FIG. In the present embodiment, this offset voltage is set to 2v. Note that the capacitively coupled electrode may be a gate electrode or an independent capacitive line. This is the same as in the first embodiment. With such a configuration, the reverse transition of the liquid crystal can be prevented using CC driving, and thus the configuration for preventing the reverse transition is simplified.

  That is, the OCB type liquid crystal display device has a problem that splay alignment occurs when the voltage is too low. For this reason, in general, a driving method that does not lower the pixel voltage below a certain value is used. As a preferable example of such a driving method, for example, it is conceivable to apply an offset voltage by changing the potential of the counter electrode into an alternating rectangular wave.

  However, this driving method is suitable for a small liquid crystal panel (liquid crystal display element), but is not suitable for a large liquid crystal panel. This is because the CR time constant during charging becomes too large because the capacity of the liquid crystal panel becomes too large. As a result of the study by the present inventors, it was practically impossible to apply an offset voltage by the above driving method in a liquid crystal panel of 10 type or more. Further, in the liquid crystal panel of 15 type or more, the application of the offset voltage cannot be realized by a method other than the CC driving. Here, the circle shape means that the diagonal line length of the substantially rectangular display screen of the liquid crystal panel is circle inches.

  Therefore, the offset voltage is applied using CC drive as in the present embodiment.

By the way, in the OCB type liquid crystal display device, the voltage that reversely transitions to the splay alignment depends on the pretilt angle. When the pretilt angle was 15 degrees, the reverse transition voltage was 1 v. According to the study of the present inventor, a general OCB type liquid crystal panel requires an offset voltage of 1 v or more. However, when a black screen was inserted in one field, a lower offset voltage was also good. That is, when a black screen is inserted, the bend alignment is maintained even if a low voltage is temporarily applied to the liquid crystal. However, this only reduces the critical voltage that reversely transitions to the splay alignment, and the offset voltage must always be applied. In this case, the offset voltage may be lower than 1v.
Embodiment 3
In the third embodiment of the present invention, CC drive is used for transition from splay alignment to bend alignment when the liquid crystal display device is activated.

  FIG. 18 is a graph showing the waveform of the counter voltage at the start-up of the liquid crystal display device according to the present embodiment, FIG. 19 is a graph showing the waveforms of the counter voltage, the gate signal, and the source signal, and FIG. The graph which shows the waveform in a rest period, (b) is a graph which shows the waveform in a transition voltage application period. 18 and 19, the same reference numerals as those in FIG. 6 denote the same or corresponding parts.

  In the liquid crystal display device according to the present embodiment, in the configuration of the first embodiment, the counter voltage, the gate signal, and the source signal are output with waveforms as described below at startup. A driver for driving the counter electrode is also provided.

  As shown in FIG. 18, when the liquid crystal display device is activated, a counter voltage Vcom having a low frequency AC waveform of 0.5 to 10 Hz is applied to the counter electrode over a predetermined transition period T3. The counter voltage Vcom of the AC waveform has a waveform in which a pause period T1 having a value of 3v and a transition voltage application period T2 having a value of −25v are alternately repeated. Here, the reason why the value of 3v is taken is to prevent a voltage from being applied to the liquid crystal as will be described later.

  Referring also to FIG. 19, the gate signal Sg is output to the gate electrode even during the transition voltage application period. As the gate signal Sg, a signal having a binary value of Vgon and Vgoff is output during the pause period T1, as shown in FIG. 19A, and during the transition voltage application period T2, the transition occurs as shown in FIG. 19B. The same quaternary signal is output as later (see FIG. 6). For this reason, in the transition voltage application period T2, the accumulated voltage Vcc is applied to the pixel electrode, and in the normal driving method, only a transition voltage of +3-(− 25) = 28v can be applied to the liquid crystal. A transition voltage of 30 V or more could be applied to the liquid crystal. This is because the accumulated voltage Vcc is generated at 2v or more. Further, when the gate signal Sg takes the value of Vge2, a particularly large accumulated voltage Vcc is generated, and a larger transition voltage can be applied accordingly. Therefore, it is desirable to output a signal having three values of Vgon, Vgoff, and Vge2 during the transition voltage application period T2 as the gate signal Sg. However, in this case, since the waveform of the gate signal Sg is different from the waveform after the transition, another routine work is imposed on the gate driver.

  On the other hand, the binary signal is output in the rest period T1, for the following reason. In other words, it is desirable not to apply a voltage to the liquid crystal during the rest period T1 in order to perform the transition well. However, when a quaternary signal is output as in the transition voltage application period T1, the accumulated voltage Vcc is applied to the liquid crystal by CC driving. Therefore, the binary signal as described above is used as the gate signal Sg in the pause period T1 so that the accumulated voltage Vcc is not generated.

  Further, the source signal Ss has the same voltage as the counter voltage Vcom at least during the idle period T1. This is to prevent voltage from being applied to the liquid crystal during the rest period T1. In the present embodiment, the source signal Ss is a constant value of 3v in both the rest period T1 and the dislocation voltage application period T2 during the transition period T3.

  In the present embodiment, it is possible to speed up the transfer by configuring as described above. Specifically, the transition time, which was conventionally 3 seconds, could be reduced to 2 seconds.

  As a prior art, there is one disclosed in Japanese Patent Laid-Open No. 9-185037, which applies a transition voltage with the gate voltage always kept at a high level. On the other hand, in the present embodiment, the gate electrode is scanned in the same manner as in the display state (after the transition), so that the accumulated voltage Vcc is effectively used even during the transition and the transition is performed efficiently.

  Next, a modification of the present embodiment will be described. FIG. 20 is a graph showing waveforms of the counter voltage, gate signal, source signal, and pixel electrode voltage according to this modification.

  In the present modification, the source signal Ss and the counter voltage Vcom are both 0 v in the pause period T1, so that no voltage is applied to the liquid crystal. In the transition voltage application period T2, the counter voltage Vcom is swung to the negative side as large as −20v, and the source signal Ss is swung to the positive side as + 7v. Further, the gate signal Sg is a ternary signal as shown in the enlarged view in the dotted line of FIG. 20, and therefore, the accumulated voltage Vcc by CC driving is applied to the pixel electrode. As a result, in the pixel electrode, the accumulated voltage Vcc is accumulated on the voltage 7v of the source signal Ss, and the potential becomes + 10v. As a result, the pixel voltage was as high as 30 V, and this could be applied to the liquid crystal. Further, since the gate signal Sg during the transition voltage application period T2 is a ternary signal, the accumulated voltage Vcc of only one side polarity is superimposed, and the accumulated voltage Vcc is as large as about 3v. The transition voltage application period T2 is set to 1 second here. Further, the gate signal Sg is made a binary signal during the suspension period T1, as in the above configuration example. Further, if the source electrode and the counter electrode have the same potential during the rest period T1, the potential of both may change, but it was most stable to keep them constant.

  In the first to third embodiments, a layered electrode made of a conductive material is formed on the inner surface of the substrate as the electrode portion. However, the electrode portion in the present invention is not limited to this electrode. For example, an electrical property variable body whose electrical property is switched between insulating and conductive by irradiating light between the electrode and the liquid crystal is disposed, and the electrical property variable body and the electrode You may make it comprise an electrode part.

  The liquid crystal display device according to the present invention can also be applied to applications such as a moving image compatible liquid crystal display that requires high-speed driving.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the structure of the liquid crystal display of FIG. 1 typically. FIG. 2 is a plan view schematically showing a configuration of a pixel of the liquid crystal display element of FIG. 1. It is sectional drawing which shows the structure of an auxiliary capacity electrode. It is a circuit diagram which shows the equivalent circuit of a pixel. It is a graph which shows a gate signal, a source signal, and a counter voltage. FIG. 4 is a graph showing a relationship between a change in a gate signal and a change in a pixel voltage, where (a) shows a change in an odd field, and (b) shows a change in an even field. It is a circuit diagram which shows the equivalent circuit of the pixel in normal drive. It is a graph for explaining a change in transmittance of a pixel due to normal driving, (a) is a diagram showing a gate signal, (b) is a graph showing a change in pixel voltage, (c) is a writing period to a holding period (D) is a graph showing the change in the dielectric constant of the liquid crystal in the pixel, (e) is a graph showing the change in the transmittance in the pixel. 4 is a graph for explaining a change in transmittance of a pixel according to the first embodiment of the present invention, where (a) is a diagram showing a gate signal, (b) is a graph showing a change in pixel voltage, and (c) is a graph showing the change in pixel voltage. 4 is a graph showing a change in pixel voltage at the time of transition from a writing period to a holding period, (d) is a graph showing a change in dielectric constant of liquid crystal in the pixel, and (e) is a graph showing a change in transmittance in the pixel. It is a graph which shows the response speed between the gradations of a liquid crystal display device. FIG. 6 is a table showing Rise time and Decay time between gradations, where (a) is a table showing the case of a normal drive OCB liquid crystal mode, (b) is a table showing a case of a CC drive OCB liquid crystal mode, and (c) ) Is a table showing the case of the CC-driven TN liquid crystal mode. 3A and 3B are three-dimensional graphs visually showing Rise time and Decay time between gradations, in which (a) is a table showing the case of CC-driven OCB liquid crystal mode, and (b) is a case of normal driving OCB liquid crystal mode. It is a table. It is a top view which shows the structure of the capacity | capacitance line by the modification 1 of Embodiment 1 of this invention. It is XV-XV sectional drawing of FIG. It is a block diagram which shows the structure of the compensation voltage application apparatus by the modification 2 of Embodiment 1 of this invention. It is a pixel voltage-transmittance graph which shows the setting of the offset voltage in the liquid crystal display device which concerns on Embodiment 2 of this invention. It is a graph which shows the waveform of the counter voltage at the time of starting of the liquid crystal display device which concerns on Embodiment 3 of this invention. 6 is a graph showing waveforms of a counter voltage, a gate signal, and a source signal at the time of starting the liquid crystal display device according to Embodiment 3 of the present invention, where (a) is a graph showing waveforms during a pause period, and (b) is a graph showing It is a graph which shows the waveform in a transition voltage application period. It is a graph which shows the waveform of the voltage of the counter voltage by the modification of Embodiment 3 of this invention, a gate signal, a source signal, and a pixel electrode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Gate electrode 3 Source electrode 4 Pixel 5 Switching element 6 Pixel electrode 7 Auxiliary capacity electrode 8 Counter electrode 9 Insulating layer
10 Insulation layer
11 Gate driver
12 Source driver
13 Display controller
14 Video signal
15 Light source
16 Lighting circuit
17 Lighting controller
18 Backlight
19 Display control circuit
30 Stacked voltage application circuit
31 capacitance line
32,33 field memory
34 Difference calculation circuit
35 Compensation voltage generator
41 Contact hole
101 Counter substrate
102 TFT substrate
103 LCD
104 retardation plate
105 Polarizer
106 Liquid crystal display elements
Cgd Stray capacitance between pixel electrode and gate electrode
Clc LCD capacity
Cst auxiliary capacity
Sg gate signal
Ss source signal
T1 transition voltage application period
T2 suspension period
T3 metastasis period
Ta Write period
Tf field duration
Th retention period
Tp Stacking period
Tr remaining period
Vcc stacking voltage (stacking voltage)
Vcom counter voltage
Vp set pixel voltage
Vp 'pixel voltage
Vs Source signal amplitude

Claims (5)

A liquid crystal layer capable of bend alignment, a display screen including a plurality of pixels for displaying an image by light transmitted through the bend-aligned liquid crystal layer, and pixel voltages corresponding to luminance information for each pixel of the image information. A liquid crystal display device comprising: pixel voltage application means for sequentially applying to the liquid crystal layer of the pixel, and displaying an image corresponding to the image information on the display screen by changing the transmittance of the light by applying the pixel voltage. Because
Gate driving means for sequentially scanning the plurality of pixels through the gate electrode;
The pixel voltage applying means includes source driving means for applying a base voltage based on the luminance information of the pixel of the image information to the liquid crystal layer of the scanned pixel through the source electrode, and the pixel electrode and the previous stage side in the scanning direction. A reverse transition from the bend alignment to the splay alignment of the liquid crystal layer is performed by applying an offset voltage so as to form the pixel voltage together with the base voltage after the scanning through capacitive coupling formed between the liquid crystal layer and the gate electrode. A liquid crystal display device comprising offset voltage applying means for preventing the occurrence of the problem.   A liquid crystal layer capable of bend alignment, a display screen including a plurality of pixels for displaying an image by light transmitted through the bend-aligned liquid crystal layer, and pixel voltages corresponding to luminance information for each pixel of the image information. A liquid crystal display device comprising: pixel voltage application means for sequentially applying to the liquid crystal layer of the pixel, and displaying an image corresponding to the image information on the display screen by changing the transmittance of the light by applying the pixel voltage. Because
  The pixel voltage application means forms the pixel voltage together with the voltage applied to the liquid crystal layer of the pixel during the sequential application, and after the sequential application, between the pixel electrode and the dedicated capacitor line. A liquid crystal display device, wherein an offset voltage for preventing reverse transition from the bend alignment to the splay alignment of the liquid crystal layer is applied to the pixels through capacitive coupling formed.   The liquid crystal display device according to claim 1, wherein the offset voltage is 1 v or more.   3. The liquid crystal display device according to claim 1, wherein the offset voltage exceeds a reverse transition voltage from bend alignment to splay alignment of the liquid crystal layer.   3. The liquid crystal display device according to claim 1, wherein a substantially black screen is displayed on the display screen within a field period which is a cycle of writing image information of one field at a constant cycle.

Images