JP4748610B2 - 取り出されたデータをメモリに直接に書き込むストレージコントローラによるバッファスペースの最適な使用 - Google Patents
取り出されたデータをメモリに直接に書き込むストレージコントローラによるバッファスペースの最適な使用 Download PDFInfo
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- JP4748610B2 JP4748610B2 JP2008157068A JP2008157068A JP4748610B2 JP 4748610 B2 JP4748610 B2 JP 4748610B2 JP 2008157068 A JP2008157068 A JP 2008157068A JP 2008157068 A JP2008157068 A JP 2008157068A JP 4748610 B2 JP4748610 B2 JP 4748610B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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Description
[0022]本発明の一態様に従って提供されるストレージコントローラは、単一バッファを使用して、複数の二次ストレージユニットから取り出されるデータを記憶する。一実施形態において、ストレージコントローラの中に提供される制御ユニットは、バッファにおける1組の(1つ又は複数の)メモリロケーションのおのおのにおける二次ストレージユニットのうちのどれかから取り出されるデータ要素を記憶する柔軟性を伴って、設計される。バッファスペースは、最適に使用することができ、そしてバッファサイズ要件は、結果として低減させることができる。
[0028]図1は、本発明のいくつかの特徴を実施することができる一例のシステムを示す図である。図は、中央演算処理装置(central processing unit)(CPU110)と、ストレージコントローラ120と、メインメモリ130と、二次ストレージユニット140A〜140Nとを含めて示されている。典型的な環境は、(タイプにおいても数においても)様々な他のコンポーネントを含むことができ、これらのコンポーネントは、説明される特徴の理解に関連していないとして示されてはいないことを理解しなければならない。同様に、一部の他のシステムは、より少ないコンポーネントを含むこともできる。図1の各コンポーネントについては、以下で詳細に説明される。
[0038]図2は、本発明の一実施形態におけるストレージコントローラの詳細を示すブロック図である。ストレージコントローラ120は、バッファ210と、制御ユニット220と、FIFO240A〜240Nと、バスマスタ250とを含んで示されている。ストレージコントローラ120は、以下の説明に関連のないものとして図に示されていない様々な他のコンポーネント/ブロックを含むことができる。以下の説明では、データ要素が、二次ストレージユニット140Aから取り出されるべきであり、取り出されたデータ要素が、メインメモリ130に記憶されるべきであることを指し示す読取り要求が受け取られることを仮定する。しかしながら、異なるストレージユニットとターゲットメモリは、本発明の様々な態様の範囲及び趣旨を逸脱することなく指定することができる。図2の各コンポーネントについては、以下で詳細に説明される。
[0046]図3の(A)及び図3の(B)は、それぞれメインメモリと、制御ユニット220の中のレジスタの一部分を表し、ロケーションデスクリプタ上の情報が、一実施形態においてCPU110によって制御ユニット220に対して供給される方法を示すために、図1及び2と組み合わせて使用される。上述したように、各ロケーションデスクリプタは、データ要素の対応するブロックが書き込まれるべきターゲットメモリとその中におけるロケーションを指し示す。
[0055]図4は、ロケーションデスクリプタが、本発明の一態様に従って、取り出され、使用される方法を示すフローチャートである。フローチャートは、単なる例証のために、図1に関して、そしてストレージコントローラ120に関連して説明される。しかしながら、様々な特徴は、(例えば、図3に関して上記した共用されたバッファを有する又は有さない)他の環境、及び他のコンポーネントの形で実施することができる。
[0070]図5Aは、一実施形態におけるバッファ210の詳細を示すブロック図である。バッファ210は、データバッファ510と制御バッファ520を含めて示され、これらは、同様に図5Bを参照して以下でさらに詳細に説明される。図5Bは、一実施形態における、制御バッファ520に記憶されるデータの性質を示している。
[0080]図6は、本発明の一実施形態における、ファイル読取りオペレーション中に関与するCPU110と、ストレージコントローラ120と、二次ストレージユニット140Aのおのおのにおけるオペレーションのシーケンスを示すために使用される一例のシーケンス図である。
[0091]本発明の様々な実施形態が上記されたが、それらは例にすぎず、そして限定ではないものとして表されていることを理解すべきである。したがって、本発明の幅と範囲は、上記の例示の実施形態のうちのどれによっても限定されるべきではなく、添付の特許請求の範囲とそれらの均等物に従ってのみ定義されるべきである。
Claims (8)
- 複数の二次ストレージユニットに対するアクセス要求を制御するストレージコントローラであって、
バッファと、
(i)第1の二次ストレージユニットから読み取られてメインメモリに転送される第1のデータ列を指定する第1の読取り要求と、(ii)第2の二次ストレージユニットから読み取られて前記メインメモリに転送される第2のデータ列を指定する第2の読取り要求とを受け取る、制御ユニットと
を備え、
前記制御ユニットが、前記第1の読取り要求と前記第2の読取り要求にそれぞれ応じて、前記第1の二次ストレージユニットからの前記第1のデータ列と、前記第2の二次ストレージユニットからの前記第2のデータ列とを取り出し、
前記バッファは、前記第1のデータ列と前記第2のデータ列とがそれぞれ前記メインメモリに転送される前に、前記第1のデータ列と前記第2のデータ列の両方を共に記憶し、
前記制御ユニットは、さらに前記第1のデータ列と前記第2のデータ列とが記憶されるべき、前記メインメモリのロケーションを指し示すデータを記憶し、
前記第1の要求が、前記メインメモリと、前記第1のデータ列の第1のサブセットが前記メインメモリ内で記憶されるべきロケーションとを指し示す第1のロケーションデスクリプタをさらに指定し、
前記制御ユニットが、前記第1のサブセットの取出しの完了の前に前記第1のロケーションデスクリプタをプリフェッチする、
ストレージコントローラ。 - 前記第1のデータ列と前記第2のデータ列を前記メインメモリに対して転送するマスタユニットをさらに備える、請求項1に記載のストレージコントローラ。
- 前記バッファが、制御バッファと、データバッファとを備え、
前記制御ユニットが、前記第1のデータ列と、前記第2のデータ列とを前記データバッファに記憶する、請求項2に記載のストレージコントローラ。 - 前記制御ユニットが、前記第1のサブセットが前記第1の二次ストレージユニットから受け取られている間に、第2のロケーションデスクリプタをプリフェッチし、前記第2のロケーションデスクリプタが、前記第1のサブセットに続くデータの第2のサブセットを識別する、請求項1に記載のストレージコントローラ。
- メモリと、
前記メモリに結合されており第1の二次ストレージユニットと第2の二次ストレージユニットとを含む複数の二次ストレージユニットと、
前記複数の二次ストレージユニットに結合された処理装置であって、(i)前記第1の二次ストレージユニットから読み取られて前記メモリに転送される第1のデータ列を指定する第1の読取り要求と、(ii)前記第2の二次ストレージユニットから読み取られて前記メモリに転送される第2のデータ列を指定する第2の読取り要求とを発行する、処理装置と、
前記複数の二次ストレージユニットに結合されており前記第1の読取り要求と前記第2の読取り要求とを処理する、ストレージコントローラであって、
バッファと、
前記第1の読取り要求と前記第2の読取り要求とを受け取る制御ユニットであって、前記第1の読取り要求と前記第2の読取り要求にそれぞれに応じて、前記第1の二次ストレージユニットからの前記第1のデータ列と、前記第2の二次ストレージユニットからの前記第2のデータ列とを取り出す、前記制御ユニットと、
を備える前記ストレージコントローラと、
を備え、
前記バッファが、前記第1のデータ列と前記第2のデータ列とがそれぞれ前記メモリに転送される前に、前記第1のデータ列と前記第2のデータ列の両方を共に記憶し、
前記制御ユニットが、さらに前記第1のデータ列と前記第2のデータ列とが記憶されるべき、前記メモリのロケーションを指し示すデータを記憶し、
前記第1の要求が、前記メモリと、前記第1のデータ列の第1のサブセットが前記メモリ内で記憶されるべきロケーションとを示す第1のロケーションデスクリプタをさらに指し示し、
前記制御ユニットが、前記第1のサブセットの取出しの完了の前に前記第1のロケーションデスクリプタをプリフェッチする、
システム。 - 前記第1のデータ列と前記第2のデータ列とを前記メモリに対して転送するマスタユニットをさらに備える、請求項5に記載のシステム。
- 前記バッファが、制御バッファと、データバッファとを備え、
前記制御ユニットが、前記第1のデータ列と、前記第2のデータ列とを前記データバッファに記憶する、請求項6に記載のシステム。 - 前記制御ユニットが、前記第1のサブセットが前記第1の二次ストレージユニットから受け取られている間に、第2のロケーションデスクリプタをプリフェッチし、前記第2のロケーションデスクリプタが、前記第1のサブセットに続くデータの第2のサブセットを識別する、請求項5に記載のシステム。
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US11/829,983 | 2007-07-30 | ||
US11/829,983 US8683126B2 (en) | 2007-07-30 | 2007-07-30 | Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory |
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JP2009032243A (ja) | 2009-02-12 |
KR20100106262A (ko) | 2010-10-01 |
CN101359314A (zh) | 2009-02-04 |
TWI365375B (en) | 2012-06-01 |
US20090037689A1 (en) | 2009-02-05 |
KR20090013085A (ko) | 2009-02-04 |
US8683126B2 (en) | 2014-03-25 |
KR101051815B1 (ko) | 2011-07-25 |
TW200921387A (en) | 2009-05-16 |
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