JP4709394B2 - Method and apparatus for exception handling used in program code conversion - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of computer system program code conversion, and more particularly, but not exclusively, to the field of emulation using dynamic binary conversion.
[0002]
[Prior art]
A computer program takes several different forms. Typically, programs are first written in a high-level language that is easily understood by human programmers. The program is compiled from a high-level language into a low-level language that is more suitable for control of the computer's processor and related components.
[0003]
However, in order for the processor to function, the program code must be provided in a machine-readable form that directs the basic operations of the processor, such as load operations, shift operations, addition operations, and storage operations.
[0004]
In order to operate faster, some processors use an extended instruction set, each representing a sequence of basic instructions. This is known as a complex instruction set computer (CISC). However, program code with a specific instruction set written (or compiled) specifically for the first processor is most likely not available on other types of processors due to differences between instruction sets for different processors. Cannot be executed.
[0005]
An emulator allows program code written for a first type of processor (a “subject” processor) to be executed on a second type of processor (a “target” processor or a “host” processor) It is. One form of this emulation process is known as binary conversion because it converts executable binary code suitable for the subject processor into executable binary code suitable for the target processor.
[0006]
Static binary conversion involves converting the entire program and then executing the converted program on the target processor, but this involves considerable delay. Therefore, emulators have been developed that convert small sections of source programs using dynamic binary conversion so that they can be executed immediately on the target processor.
[0007]
This is much more efficient because large sections of the source code are not actually used or rarely used. An emulator using a dynamic conversion system selects to convert only the necessary part of the source program according to demand, in parallel with program execution.
[0008]
The following briefly summarizes and describes a dynamic binary conversion for an emulator that can be used in a preferred embodiment of the present invention. More detailed background on the field of dynamic binary conversion is given in Applicant's co-pending application GB98 22075.9 entitled “PROGRAM CODE CONVERSION”, the contents of which are to avoid unnecessary duplication. Incorporated herein by reference.
[0009]
When performing dynamic binary conversion, the emulator appears to the subject code as if the subject code is being executed by an appropriate subject processor. The emulator duplicates the subject machine, including, for example, a register of the subject processor, in order for the emulator to provide a virtual subject machine. The emulated registers are referred to herein as "abstract registers", which correspond to the subject processor register set used by the subject code.
[0010]
In the preferred dynamic conversion process, the emulator first converts a given subsection of the subject code into an intermediate representation that represents the subject code instructions in a general format, and optionally optimizes the intermediate representation, and then the optimized intermediate Convert the representation into executable binary code for the target processor. The sub-section of the subject code preferably corresponds to a “basic block” starting with the first instruction at the unique entry point and ending with the last instruction at the unique exit point. Typically, the last instruction in a block is a jump instruction, a call instruction or a branch instruction (conditional or unconditional).
[0011]
In the field of binary conversion, there are problems associated with exception handling. Exception handling refers to the occurrence of a condition in which processing cannot be continued unless it is handled. This includes explicit exception handling that is executed as an instruction in the subject code (eg, an exception is reported if the value of one register is greater than the value of the second register), and memory that is not currently available Includes exception handling resulting from memory read or write operations on the page. In either case, it is desirable to report exception handling to the exception handler written in the subject code.
[0012]
However, many subject machine architecture definitions require that exception handling be reported at the boundary between subject code instructions according to a predetermined set of rules. For example, in the subject architecture definition, if exception handling is reported, the effect of all previous subject instructions has been completed and the exception handling points to the first instruction of subject code that has not been executed. It may be necessary that the effect from the subject instruction or any subsequent instruction has not yet occurred. Furthermore, the architecture definition of a particular processor may have different rules for different types of exception handling.
[0013]
In the context of binary conversion, it is clear that the target instruction itself, which is executed by the target processor and reports exception handling, does not satisfy the condition for reporting exception handling to the exception handler written in the subject code. The instructions are often executed in a different order on the target processor when compared to the order of the instructions in the corresponding subject code block. This is primarily due to differences between the subject processor instruction set for which the subject code was written and the target processor executing the converted target code, and secondly, typically during conversion. This is due to the optimization of the intermediate representation performed.
[0014]
Exception handling can occur in response to executing the converted target code on the target processor, and can also occur during execution of the emulator code on the target processor, i.e. during conversion. In order to report exception handling to the subject exception handler, the state of the virtual subject processor represented by the emulator, including the exact state of the subject processor registers, must be available from the subject exception handler.
[0015]
One approach to this problem is to return the virtual subject machine to the conditions applied when entering the section of code being translated or executed, i.e., subject code instructions that are transforming or executing the virtual subject machine. May return to the prevailing condition at the entry point to the current block. In such an approach, the exception handler can step through the instructions of the source code block individually and identify the instruction causing the exception handling.
[0016]
US Pat. No. 5,832,205 (Kelly et al.) Discloses an emulator that uses a set of “work” registers during the emulation of each subject code section. The contents of each of these working registers is copied to the “official” virtual subject register set at the end of the subject code section using a gated store buffer. Thus, if exception handling occurs while emulating a subject code section, this only affects the working register, and the state of the virtual subject machine recovers from the “official” register at the entry point to that subject code section. be able to.
[0017]
However, as in the prior art described above, the use of the “work” and “official” registers copies information from the “work” register to the corresponding “official” register at the end of each subject code section. The overhead of the emulation process in the network will increase significantly.
[0018]
[Problems to be solved by the invention]
An object of the present invention is to provide a method for representing a subject register in an emulator, which allows exceptions to be accurately reported to the subject exception handler according to handler rules, while at the same time minimizing overhead in the emulator. Keep it down. It is another object of the present invention to provide an emulation method and apparatus that allows accurate exception handling by representing a subject register.
[0019]
[Means for Solving the Problems]
According to the present invention, a method for representing a subject register in an emulator is provided, the method comprising: (a) mapping an abstract register representing a subject register of a subject machine to a first location or a second location in a target machine. And (b) the contents of one of the first location or the second location represent a deterministic version of the abstract register for use by the emulator during exception handling, and at the same time the first location or second Swapping the abstract register mapping between the first position and the second position so that the other of the positions represents a speculative version of the abstract register.
[0020]
For a given section of subject code, one of the first position or the second position holds the definite value of the abstract register when entering the section, and the other of the first position or the second position is It is preferable to keep the speculative current value of the abstract register used in the section.
[0021]
When the end of the subject code section is reached, the abstract register is preferably mapped to a position opposite that of the first position or the second position. If it is confirmed that no exception has occurred in the subject code section, the speculative version becomes deterministic. Ideally, the mapping change step is performed only if the content of the speculative version of the abstract register has been updated in a given subject code section.
[0022]
Step (a) includes (a1) providing a plurality of abstract registers each representing a register of the subject machine; and (a2) each of the plurality of abstract registers for each position of the first position set in the target machine. Or preferably mapping to each position of the second set of positions. Step (b) preferably includes the step of swapping the mapping for each abstract register between the first position set and the second position set, respectively.
[0023]
The first location and / or the second location is preferably a memory location in the target machine. Alternatively, the first location and / or the second location is preferably a register of the target machine.
[0024]
The method according to the invention is preferably used with an emulator that performs dynamic binary conversion. Suitably, the predetermined section of the subject code represents one or more basic blocks of the subject code.
[0025]
Further, according to the present invention, there is provided a method for use in exception processing by an emulator that performs program code conversion between a subject code suitable for a subject processor and a target code suitable for a target processor.
[0026]
The method includes providing at least one abstract register (X, Y) each representing a register of a subject processor; and (b) placing the one or each abstract register at a corresponding location in a target processor. Mapping to a pair; and (c) for a given section of subject code, one of the first location or the second location is used by the emulator during exception handling to enter the section of the abstract register Hold the deterministic value, while the other of the first position or the second position holds the estimated current value of the abstract register for the emulator to update in that section. Swap the one abstract register or the mapping of each abstract register between a position and the second position of the position pair Including the step.
[0027]
Furthermore, according to another aspect of the present invention, there is provided an emulator method and an emulator apparatus for performing the method according to the written contents of this specification. The present invention also relates to a computer, when programmed to perform a method according to any written content herein, to a computer program for performing a method according to any written content, and to a book. A computer program product that includes computer readable instructions for performing a method according to any written content in the specification.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
For a better understanding of the present invention, how the embodiments of the present invention are implemented will be described with reference to the accompanying schematic drawings.
[0029]
Referring to FIG. 1, a typical prior art arrangement is shown, which represents the configuration of a subject machine in which a subject code 10 is directly executed by a subject processor 11. The subject code is suitably executable binary code. However, as known to those skilled in the art, the subject code can be expressed in any suitable language having an intermediate layer (such as a compiler) between the subject code 10 and the subject processor 11. .
[0030]
Referring now to FIG. 2, a typical prior art configuration is shown, which represents an example of using the binary conversion type emulator 20 as an intermediate layer that allows the target processor 31 to execute the subject code 10. Yes. The preferred embodiment of the present invention is particularly intended for use with the emulator 20 that dynamically binary converts the subject code 10 into a target code 30 executable on the target processor 31.
[0031]
Referring now to FIG. 3, the emulator 20 of the preferred embodiment is shown in more detail and is comprised of a front end 21, a core 22, and a back end 23.
[0032]
The front end 21 has a configuration unique to the subject processor 11 to be emulated. The front end 21 converts the instructions of the subject code 10 into a generic intermediate representation for each basic block of the subject code. Each basic block may contain a set of consecutive instructions between the first instruction representing a unique entry point and the last instruction (such as a jump instruction, call instruction, or branch instruction) at a unique exit point. Is appropriate. In a particularly preferred embodiment, the emulator 20 selects a group block consisting of two or more basic blocks selected as a unit for code generation and optimization. Furthermore, the emulator 20 supports isoblocks representing the same basic block of subject code under different entry conditions. Each predetermined section of the subject code 10 becomes an intermediate representation block ("IR block").
[0033]
The core 22 optimizes each IR block generated by the front end 21 using optimization techniques that need not be described in detail herein. The back end 23 takes the optimized IR block from the core 22 and generates a target code 30 that can be executed by the target processor 31.
[0034]
As shown in FIG. 4, in use, the first predetermined section of the subject code 10 is identified, for example, as a basic block 100 and converted by the emulator 20 running on the target processor 31 in conversion mode. The target processor 31 then executes the corresponding optimized and transformed block 300 of the target code 30.
[0035]
The preferred emulator 20 includes a plurality of abstract registers that are appropriate when provided to the core 22 of FIG. 3, which represents physical registers used to execute the subject code 10 in the subject processor 11. The abstract register defines the state of the subject processor 11 being emulated by representing the expected effect of the subject code instruction on the subject processor register.
[0036]
As shown in FIG. 5, in the preferred embodiment, two sets of abstract registers, referred to herein as set A and set B, are provided. At initialization, the first of these two sets, eg, set A, holds a “determined” value. That is, the set A registers are defined as holding initial values known to be valid, representing the expected contents of the physical registers of the emulated subject processor 11.
[0037]
A second set of abstract registers, referred to as set B in this example, is initially defined to represent a “guess” value. That is, at initialization, the second set of abstract registers (set B) also holds the expected initial contents of the physical registers of the subject processor 11, but the value of this set B is not trusted to be valid.
[0038]
During the conversion process, the emulator 20 uses an inferred set of abstract registers (i.e., set B), updating its contents to predict the physical registers of the subject processor 11 after execution of the block 100 of subject code 10. Indicates the state. During the conversion of the first block, the contents of the definite set of abstract registers (ie, set A) are not changed.
[0039]
If an exception occurs during the conversion or execution of the basic block 100, the emulator 20 enters the block 100 and uses the abstract register (ie, set A) marked as holding deterministic data, and the subject register's Recover immediately. The exception handler can then step through the instructions in block 100 of source code 10 sequentially to identify the instruction causing the exception. Here, the state of the abstract register is updated after each instruction. Thus, once the subject code instruction causing the exception is identified, the state of the virtual subject machine represented by the emulator is reported to the subject code exception handler according to that machine's rules. The subject code exception handler recovers the exception according to the processing process and returns to the point in the subject code appropriate for the exception. For example, it is common for an exception handler to return the emulator to the next unexecuted instruction in the source code 10. The conversion process or execution process can continue from that point.
[0040]
Upon successful execution of the converted block of the target code 300, the register of the set holding the guess value (ie, set B) is updated and the corresponding register of the subject processor 11 being emulated at the end of the basic block 100 of the subject code 10 The prediction content of is retained. At this point, the first set (ie, set A) of abstract registers holds the state of the subject processor as it entered the block of subject code 100, and the second set (ie, set B) of abstract registers is: The state at the end of block 100 is retained. Since block 100 has been successfully converted and executed, it is now defined that the set B abstract register holds a definite value and the set A abstract register holds an inferred value.
[0041]
Suitably the set A and set B abstract registers form a register pair. Each register in set A has a partner register corresponding to set B. One of the pair holds the final value of its abstract register and the other holds the guess value. The definitions of these two registers are reversed at the end of each section of code so that each register of the pair performs the opposite function during the next code section. Swapping the function of the two registers in each register pair provides a simple and clear way to maintain entry conditions for the current code section.
[0042]
Another advantage is that the state of all abstract registers does not have to be updated upon successful completion of each code section. Only the registers that have changed during the section need to be updated to show the new functionality. If the value of a particular abstract register is not changed during a code section, that value is kept as is during the next section and performs the same deterministic or speculative function accordingly.
[0043]
A simplified exemplary embodiment will now be described with reference to FIGS. In step 1 of FIG. 5, the first abstract register (RegX) representing the register X of the subject processor 11. _A ) Holds the final value and the second abstract register (RegX) _B ) Holds the estimated value. The abstract register is suitably kept in a memory location, and the working map of register X is a speculative version RegX. _B Point to the position. Similarly, for register Y in this example, initially RegY _A Is confirmed, RegY _B Is speculation. After execution of one or more instructions, such as block 100 of subject code 10, the abstract register mapping is updated in step 2 as shown in FIG. In this example, the contents of speculation register Y have changed, so this time RegY _B Is considered the definitive version used in subsequent blocks. Register Y map is updated and RegY _A Point to the guessed version. In contrast, register X is not affected by one or more instructions in block 100, and thus RegX _A Remains a definitive version, RegX _B Remains a speculative version.
[0044]
To allow continuity of register contents between code sections, it is appropriate that the first read operation encountered during the current code section uses a definitive version of each particular abstract register. The definitive version represents the state of that register when it enters the current code section, and therefore maintains continuity with previous sections. Subsequent read operations also use a definitive version of each abstract register until a write operation is encountered. The first write operation uses a speculative version of each specific abstract register. Thus, the definitive version is not changed, and the speculative version now holds the current value of the associated abstract register. Subsequent read and write operations use the speculative version throughout the rest of the code section.
[0045]
As described above, in the preferred embodiment of the present invention, an abstract register corresponding to each physical register of the subject processor 11 is provided, and this abstract register is mapped to two predetermined locations. One of each pair of abstract register locations holds a deterministic value and the other holds a guess value. The functions of these two positions are easily reversed and the positions holding deterministic contents are exchanged. Therefore, a time-consuming copy operation is avoided.
[0046]
In the preferred embodiment, the two versions of each abstract register are implemented by mapping to two sets of memory locations, and the swapping of the definite version and the speculative version is accomplished by swapping the memory mapping between these two locations. . Updating the abstract register map maintained in the target machine to replicate the subject processor's physical registers is done quickly and easily during the conversion, and overhead is incurred when the conversion code is executed many times. Absent.
[0047]
In another preferred embodiment, instead of using a pair of memory locations, one or both of a fixed version and an inferred version of the abstract register is stored in a target machine register pair (on a target machine with sufficient capacity). Can do.
[0048]
One aspect of the preferred embodiment of the present invention addresses the problem of fixing register references across branches, particularly branches (or loops) from the current block of subject code to a previously transformed block. Branches between code blocks are common in practice, but often involve referencing the same code block from multiple other locations in the subject code, thereby creating different entry conditions . One solution is to copy the contents from the definitive version of the abstract register to the speculative version, thereby making the entry condition suitable for use by previously converted code blocks. For example, when the block is first converted, the first version RegX _A Was definite. Therefore, the same block of translated code will be used again later, and the second version of the abstract register RegX _B If the block is reached under the condition that is definite, register X before continuing _B The contents of register RegX _A Must be copied to. This creates a copy overhead when performing a branch to a previously converted code block. The preferred solution used in the embodiment of the present invention is to re-transform the block, this time with the conditions used at the time of branching, with multiple versions of the previously translated code each associated with a specific set of entry conditions. This avoids this copying operation. More conversion work is required, but ongoing copy overhead is avoided. In general, transforming the subject code section (including any number of basic blocks) once again eliminates the compensation copy required for the particular register updated odd times during the loop.
[0049]
Although the above embodiments relate to emulators that use dynamic binary translation, the method can also be applied to static translations that transform large sections of code before execution. In static translation, the code section selected for translation typically represents the entire program or the majority of the program. Nevertheless, it is advantageous to use the above method that handles exceptions that occur during code conversion and execution of the conversion code and at least allows exception handling to be performed from the state when it entered the code section. Furthermore, the method can be applied to program code optimization where the subject machine and the target machine have the same or at least compatible instruction set and architecture.
[0050]
The present invention relates to a computer program product that retains computer readable instructions for performing the above method, and a computer program for performing the above method on a computer when programmed to perform the above method. Over.
[0051]
The reader's notice is directed to all documents and documents filed with or prior to this specification in connection with the present application and published to the public handbook along with this specification. Is incorporated herein by reference.
[0052]
All features disclosed in this specification (including the appended claims, abstracts, and drawings), and / or every step of a method or process disclosed herein, are at least one of such features and / or steps. Any combination may be used except for combinations in which the parts are mutually exclusive.
[0053]
Each feature disclosed in this specification (including the appended claims, abstract, and drawings) may be replaced with an alternative feature serving the same purpose, an equivalent purpose, or a similar purpose, unless expressly stated otherwise. . Thus, unless expressly stated otherwise, each feature disclosed is one example of a generic series of equivalent or similar features.
[0054]
The invention is not limited to the details of the embodiment (s) described above. The present invention is directed to any new feature, or any new combination of features disclosed herein (including any of the appended claims, abstracts, and drawings), or any of the steps of the method or process disclosed herein. Over a new step, or any new combination.
[Brief description of the drawings]
FIG. 1 is a diagram of a typical subject processor configuration according to the prior art.
FIG. 2 is a diagram of an exemplary emulator that uses binary conversion.
FIG. 3 is a diagram representing the configuration of an emulator using binary conversion that can be used in a preferred embodiment of the present invention.
FIG. 4 is a diagram of a preferred binary conversion type emulator used.
FIG. 5 is a diagram of an exemplary abstract register set.
FIG. 6 is a diagram of an exemplary abstract register set.

Claims (14)

A method for representing a subject register in an emulator, wherein the emulator device is
(A) mapping the emulated abstract register (X) representing the subject register of the subject machine to a first location (XA) and a second location (XB) in the target machine, wherein One of the position 1 and the second position (XA, XB) represents a speculative version of the abstract register, while the other of the first position and the second position (XB, XA) is the abstract register the deterministic version and table, each of the first position (XA) and said second position (XB) is a memory location or target register, and said step of maps,
(B) one of the first position and the second position (XA, XB) represents a definitive version of the abstract register for use by the emulator during exception handling, while the first position and the second position An abstract register (X) between the first position (XA) and the second position (XB) so that the other of the second positions (XB, XA) represents a speculative version of the abstract register. look including to perform the steps of replacing the mapping, predetermined sections of the subject code represents one or more basic blocks of subject code, and the first position (XA) and said second position (XB) Wherein the mapping of the abstract register (X) is alternately performed in units of the basic block .   For a predetermined section of the subject code, one of the first position or the second position (XA, XB) holds a definite value of the abstract register (X) when entering the predetermined section, and the first position 2. The method of claim 1, wherein one of the second position or the other of the second positions (XB, XA) holds an inferred current value of an abstract register (X) for use during the predetermined section.   The method of claim 2, wherein step (b) of swapping mapping is performed when the end of the predetermined section of subject code is reached.   The method according to claim 1 or 3, wherein the step (b) of swapping mapping is performed only if the content of the speculative version of the abstract register (X) has been updated in the predetermined section of the subject code. Step (a)
(A1) providing a plurality of abstract registers (X, Y) each representing a subject machine register;
(A2) mapping each of the plurality of abstract registers (X, Y) to each position (XA, XB) of the first position set or each position (XB, YB) of the second position set in the target machine Including and
The step (b) comprises replacing the mapping for at least one abstract register (X, Y) between each position of each set of the first position set and the second position set. The method as described in any one of 1-4. The emulator is executed in a dynamic binary translation method according to any one of claims 1-5. A method for performing program code conversion between a subject code suitable for a subject processor and a target code suitable for a target processor, wherein an emulator device comprises:
(A) providing at least one emulated abstract register (X, Y) each representing a register of a subject processor;
(B) mapping the one abstract register (X or Y) or each abstract register (X, Y) to a corresponding position pair (XA, XB, YA, YB) in the target processor, respectively; One of the first position and the second position of the position pair (eg, XA, YA) holds the estimated current value of the abstract register (X, Y), while the first position and the second position The other of the positions (for example, XB, YB) holds the final value of the abstract register (X, Y) , and the first position (XA) and the second position (XB) are each a memory position or a target register a step is, to the map at,
(C) For a given section of subject code, when one of the first and second locations (eg, XA, YA) enters the given section for use by the emulator during exception handling Holds a definite value of an abstract register (X, Y), while the other of the first location and the second location (eg, XB, YB) is updated for updating by the emulator during the predetermined section. At least 1 between the first pair (XA, YA) of the position pair and the second pair (XB, YB) of the position pair so as to hold an estimated current value of the abstract register (X, Y) one abstract registers (X, Y) viewing including to perform the steps of replacing the mapping, one or more basic predetermined section of the subject code is subject code It represents the lock, the first position that between the (XA) and said second position (XB) replaced the mapping of abstract register (X) are alternately performed in the basic block unit, said method. The method of claim 7 , wherein step (c) of swapping mapping is performed when the end of the predetermined section of subject code is reached. 9. A method according to claim 7 or 8 , wherein the step (c) of swapping mapping is performed only for the one abstract register or each abstract register (X, Y) updated during the predetermined section of subject code. The emulator device, a computer program for executing the steps of the method according to any one of claims 1-9. An emulator device,
(A) Map the emulated abstract register (X) representing the subject register of the subject machine to a first location (XA) and a second location (XB) in the target machine, where the first And one of the second positions (XA, XB) represents a speculative version of the abstract register, while the other of the first position and the second position (XB, XA) is the definition of the abstract register. Version, wherein the first location (XA) and the second location (XB) are each a memory location or a target register;
(B) one of the first position and the second position (XA, XB) represents a definitive version of the abstract register for use by the emulator during exception handling, while the first position and the second position An abstract register (X) between the first position (XA) and the second position (XB) so that the other of the second positions (XB, XA) represents a speculative version of the abstract register. Swap the mapping , where a predetermined section of the subject code represents one or more basic blocks of the subject code, and an abstract register between the first location (XA) and the second location (XB) The emulator device , wherein the mapping of X) is alternately performed in units of basic blocks . For a predetermined section of the subject code, one of the first position or the second position (XA, XB) holds a definite value of the abstract register (X) when entering the predetermined section, and the first position The emulator device according to claim 11 , wherein the other position (XB, XA) of the second position or the second position holds an estimated current value of the abstract register (X) for use during the predetermined section. An emulator device that performs program code conversion between a subject code suitable for a subject processor and a target code suitable for a target processor,
At least one emulated abstract register (X, Y) each representing a register of the subject processor;
An emulator,
Each said abstract register (X, Y) or each abstract register (X, Y) is mapped to a corresponding position pair (XA, XB, YA, YB) in the target processor, where One of the first position and the second position (eg, XA, YA) holds the estimated current value of the abstract register (X, Y), while the other of the first position and the second position ( For example, XB, YB) holds a definite value of the abstract register (X, Y), and each of the first position (XA) and the second position (XB) is a memory location or a target register,
For a given section of subject code, one of the first and second locations (e.g., XA, YA) when the exception register (X, YA) enters the given section for use by the emulator during exception handling. Y), while the other of the first position and the second position (eg, XB, YB) is stored in the abstract register (X, Y) at least one abstract register (XB) between the first pair (XA, YA) of the position pair and the second pair (XB, YB) of the position pair so as to hold an estimated current value of Y) , Y) for switching the mapping, and the emulator, wherein a predetermined section of the subject code represents one or more basic blocks of the subject code. The emulator apparatus, wherein the mapping of the abstract register (X) between the first position (XA) and the second position (XB) is alternately performed in units of the basic block . Swapping the mapping is performed when the end of the predetermined section of subject code is reached, or for the one abstract register or each abstract register (X, Y) updated during the predetermined section of subject code The emulator device according to claim 13 , wherein the emulator device is executed only.

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