JP4687567B2 - Transmission / reception circuit, communication device including the same, and transmission / reception signal processing method - Google Patents

Transmission / reception circuit, communication device including the same, and transmission / reception signal processing method Download PDF

Info

Publication number
JP4687567B2
JP4687567B2 JP2006146050A JP2006146050A JP4687567B2 JP 4687567 B2 JP4687567 B2 JP 4687567B2 JP 2006146050 A JP2006146050 A JP 2006146050A JP 2006146050 A JP2006146050 A JP 2006146050A JP 4687567 B2 JP4687567 B2 JP 4687567B2
Authority
JP
Japan
Prior art keywords
transmission
circuit
signal
reception
baseband
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006146050A
Other languages
Japanese (ja)
Other versions
JP2007318462A (en
Inventor
貴志 武藤
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2006146050A priority Critical patent/JP4687567B2/en
Publication of JP2007318462A publication Critical patent/JP2007318462A/en
Application granted granted Critical
Publication of JP4687567B2 publication Critical patent/JP4687567B2/en
Application status is Expired - Fee Related legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Description

  The present invention relates to a transmission / reception circuit, and more particularly to a transmission / reception circuit having an RF circuit and a baseband circuit.

  Regarding the digital interface of RF circuit and BB (baseband) circuit, standardization specifications such as “DigRF DUAL-MODE 2.5G / 3G BASEBAND / RFIC INTERFACE STANDARD” (3G Dig RF) have been proposed by the DigRF Working Group. Yes.

JP 2001-345732 A JP 2003-318771 A

  However, the above specifications are based on "DigRF BASEBAND / RF DIGITAL INTERFACE SPECIFICATION" for 2.5G (GSM / GPRS System), which has been standardized in advance, and as shown in FIG. Only the system clock is supplied to the circuit 130. For this reason, the baseband clock (3.84 MHz or its multiplied frequency) of 3G System must be generated individually by both devices, resulting in wasteful configuration, and further passing of signals between the two circuits There has been a problem that it becomes difficult to control the synchronization of these. For example, Patent Documents 1 and 2 disclose a configuration for generating a baseband clock in both the RF circuit and the BB circuit as described above.

  Further, in the current 3G terminal, a function of estimating the reception timing of the base station from the data timing received by the mobile device and correcting the transmission timing of the mobile device is used. For example, the correction amount at one time is any one of −1/4 chip, 0 chip, and +1/4 chip. In order to realize this function only with the interface signal defined by DigRF, it is necessary to implement a function for managing radio timing on the RF circuit side as well. On the other hand, there is a difference in the process rules adopted between the conventional RF circuit and BB circuit due to the difference in electrical specifications required for the circuit, and the BB circuit where only the digital circuit is mounted is a finer process. Rules can often be adopted. Therefore, even when realizing the same digital circuit function, it can be expected that the functional arrangement on the BB circuit side will be realized with a smaller circuit area than the functional arrangement on the RF circuit side. When a function for managing wireless timing is mounted on the circuit side, there is a problem that it is difficult to reduce the size of the circuit.

  Therefore, it is an object of the present invention to provide a transmission / reception circuit that improves the disadvantages of the above-described conventional example, and in particular, can simplify the configuration, reduce the size, and reduce the power consumption. .

Therefore, a transmission / reception circuit which is one embodiment of the present invention
A transmission / reception circuit comprising: an RF circuit that performs transmission / reception processing of a transmission / reception signal via an antenna; and a baseband circuit that performs modulation / demodulation processing of the transmission / reception signal,
The baseband circuit generates a clock signal used for digital signal processing with respect to the transmission / reception signal in the baseband circuit, and outputs the clock signal to the RF circuit.
The RF circuit performs digital signal processing of the transmission / reception signal based on the clock signal input from the baseband circuit.
It is characterized by that.

  According to the above invention, a clock signal for digital signal processing is generated in a baseband circuit in which only a digital circuit is mounted and a miniaturization process is advanced, and the generated clock signal is also input to the RF circuit, The RF circuit also performs digital signal processing based on this. For example, the RF circuit performs processing for sampling a received signal received via an antenna and processing for sending the received signal to a baseband circuit. As a result, transmission / reception processing can be realized in the RF circuit without providing a clock signal generation function in the RF circuit, so that the circuit area can be reduced as a whole and power consumption can also be reduced. .

  Further, the RF circuit and the baseband circuit are characterized in that a signal passing process between them is performed at a timing based on the clock signal. As a result, the data transfer process between the RF circuit and the baseband circuit is executed at the timing based on the same clock signal, so that the control becomes easy.

  The baseband circuit is characterized in that the transmission timing of the transmission signal transmitted via the antenna is corrected based on the received signal received from the RF circuit and is transmitted to the RF circuit. At this time, the baseband circuit holds delay time information indicating the delay time by analog signal processing of the transmission / reception signal transmitted / received via the antenna, and corrects the transmission timing of the transmission signal based on this delay time information. It is characterized by. Thereby, since the digital signal processing in the RF circuit is performed based on the clock signal generated in the baseband circuit, the transmission timing correction processing of the transmission signal is performed in the baseband circuit based on the received signal. This can be realized and functions can be concentrated in a baseband circuit constituted by a digital circuit, so that the entire circuit can be reduced in size. Then, the delay time due to the analog signal processing is held in advance, and the correction timing is calculated based on the value, whereby the transmission timing can be corrected with higher accuracy.

  Further, the RF circuit is characterized by detecting whether or not the transmission timing of the transmission signal is corrected based on the transmission timing and the clock signal of the transmission signal transmitted from the baseband circuit. As a result, it is possible to detect that the transmission timing has been corrected in the RF circuit without notifying the RF circuit of the presence / absence of correction from the baseband circuit, and realize processing such as setting change associated therewith. Thus, the circuit can be simplified and the power consumption can be reduced.

  The transmitter / receiver circuit is more effective by being installed in a communication device such as a mobile phone that is required to be reduced in size and power consumption.

In addition, a transmission / reception signal processing method according to another aspect of the present invention includes:
A transmission / reception signal processing method using a transmission / reception circuit including an RF circuit that performs transmission / reception processing of a transmission / reception signal via an antenna, and a baseband circuit that performs modulation / demodulation processing of the transmission / reception signal,
The baseband circuit generates a clock signal used for digital signal processing with respect to the transmission / reception signal in the baseband circuit and outputs the clock signal to the RF circuit
The RF circuit and the baseband circuit perform digital signal processing of the transmission / reception signal based on the clock signal.
It is characterized by that.

  In the digital signal processing, the RF circuit and the baseband circuit perform a signal transfer process between them at a timing based on the clock signal. Further, at the time of digital signal processing, the baseband circuit corrects the transmission timing of the transmission signal transmitted via the antenna based on the received signal received from the RF circuit, and transmits the corrected signal to the RF circuit. At this time, at the time of digital signal processing, the transmission signal is based on the delay time information indicating the delay time by the analog signal processing of the transmission / reception signal transmitted / received via the antenna held in advance by the baseband circuit and the received signal It is characterized by correcting the transmission timing. Further, the digital signal processing is characterized in that the RF circuit detects whether or not the transmission signal transmission timing is corrected based on the transmission timing and clock signal of the transmission signal transmitted from the baseband circuit.

  Even the invention of the method having the above-described configuration has the same operation as the above-described transmission / reception circuit, and thus the above-described object of the present invention can be achieved.

  Since the present invention is configured and functions as described above, according to this, a clock generation function is provided in a baseband circuit in which only a digital circuit is mounted and a miniaturization process is advanced, and the generated clock signal is provided in an RF circuit. Since the RF circuit can perform transmission / reception processing without providing a function for generating a clock signal in the RF circuit, the circuit area can be reduced as a whole and the power consumption can be reduced. It has an unprecedented excellent effect of being able to.

  The present invention is characterized in that the wireless timing management function is integrated into the baseband circuit without being provided in the RF circuit. Hereinafter, specific circuit configurations and operations thereof will be described in the embodiments.

  A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a circuit configuration. FIG. 2 is a diagram illustrating the flow of signals in the circuit, and FIG. 3 is a timing chart.

[Constitution]
In this embodiment, a transmission / reception circuit mounted on a mobile phone based on the 3G DigRF specification will be described as an example, but the present invention can also be applied to a circuit mounted on another communication device.

  As shown in FIG. 1, the transmission / reception circuit in this embodiment includes an RF circuit 20 that performs transmission / reception processing of transmission / reception signals via an antenna 40, and a baseband circuit 30 (BB circuit) that performs modulation / demodulation processing of transmission / reception signals. In addition, Crystal 1 (crystal oscillator) serving as a source oscillation of the operation clock is provided. In addition to this configuration, the mobile phone is equipped with a configuration for realizing a call function and a data communication function, but the description thereof is omitted.

  The BB circuit 30 is configured by a digital circuit, and performs synchronization processing on the PLL 2 that generates a baseband clock (clock signal), the PLL 3 for high-speed differential I / F operation, and the serial data from the RF circuit 20. A reception data extraction unit 10 (S / P) for extracting reception data, a demodulation circuit 11 (Demodulator) for processing the reception data, a modulation circuit 12 (Modulator) for generating transmission data, a packet by serially converting the transmission data A transmission serial data generation unit 13 (P / S). The generated baseband clock is output from the PLL 2 to the RF circuit 20.

  The RF circuit 20 includes a high-speed differential I / F operation PLL 4, a reception synthesizer 5 (RX Synth), a reception analog filter 6 (Pre Filter), a reception AD converter 7 (ADC), and a reception digital filter 8. (FIR), received serial data generating unit 9 (P / S) for serially converting received data to generate a packet, and transmission data extracting unit for detecting synchronization and extracting transmitted data for serial data from the BB circuit 30 14 (S / P), a transmission digital filter 15 (FIR), a transmission DA converter 16 (DAC), a transmission analog filter 17 (Post Filter), and a transmission synthesizer 18 (TX Synth).

  Among the configurations in the RF circuit 20 and the BB circuit 30 described above, the reception AD converter 7, the reception digital filter 8, the reception serial data generation unit 9, the reception data extraction unit 10, the demodulation circuit 11, the modulation circuit 12, The transmission serial data generation unit 13, the transmission data extraction unit 14, the transmission digital filter 15, and the transmission DA converter 16 operate in synchronization with the baseband clock generated by the BB circuit 30. That is, the BB circuit 30 operates in synchronization with the baseband clock generated in the BB circuit 30, and the RF circuit 20 has a digital circuit portion synchronized with the baseband clock supplied from the BB circuit 30. Will work.

  Further, an operation synchronized with the above-described baseband clock will be described in detail. In the RF circuit 20, the received signal is sampled by the AD converter 7, the received serial data is generated and transmitted to the BB circuit 30 by the P / S 9, and the received serial data is received from the BB circuit 30. P14 and the like are executed in synchronization with the baseband clock. At this time, in the BB circuit 30 as well, in synchronization with the baseband clock, the reception serial data extraction process by the S / P 10, the generation of transmission serial data by the P / S 13 and the transmission process to the RF circuit 20 are performed. Therefore, the signal passing process between the RF circuit 20 and the BB circuit 30 is performed in synchronization with the same baseband clock.

  Further, the BB circuit 30 has a function of predicting the radio timing on the base station side based on the received serial data received from the RF circuit 20 and correcting the transmission timing of the transmission serial data. Specifically, first, the BB circuit 30 has delay time information indicating a delay time of a transmission / reception signal between an analog signal processing part (filters 6 and 17 and the like) in the RF circuit and the antenna 40 (including the antenna itself). It is stored in advance, and a reception-to-transmission interval specification (for example, 1024 chips) is also stored. Then, the demodulation circuit 11 reproduces the timing of the received frame / slot based on the received serial data, and notifies the modulation circuit 12 of this. At this time, since the received serial data is processed in synchronization with the baseband clock generated by the BB circuit 30, the base station side can easily and more accurately use the delay time information in the analog signal processing portion or the like. Can be estimated. Then, the modulation circuit 12 determines whether or not the timing is corrected and notifies the transmission serial data generation unit 13 so that the transmission serial data generation unit 13 has a reception → transmission interval determined by the 3GPP regulations. That is, the transmission timing is corrected so that the base station side can correctly receive the transmission data from the mobile phone. The correction process will be described with an example when explaining the operation.

  Further, the RF circuit 20 detects whether or not the transmission timing is corrected based on the transmission timing of the transmission serial data transmitted and received from the BB circuit 30 and the baseband clock. For example, as shown in FIG. 3 to be described later, transmission data that is normally output every 4 cycles of the baseband clock is 3 cycle intervals (when transmission timing is advanced) or 5 cycle intervals (when delayed). And the presence or absence of correction is recognized. When detecting that the correction has been made in this way, the RF circuit 20 uses the transmission digital filter 15 to rate-convert transmission data input at a cycle of 3.84 MHz, for example, to an operating frequency of the DA converter 16 of 15.36 MHz. Since the process is performed, the operation (coefficient) of the filter 15 can be controlled.

  Here, the serial data transmitted / received between the reception serial data generation unit 9 → the reception data extraction unit 10 and the transmission serial data generation unit 13 → the transmission data extraction unit 14 described above is “Sync Word + Header + data part” described in DigRF. It shall consist of

[Operation]
Next, the operation of the transmission / reception circuit having the above configuration will be described. First, in the BB circuit 30, a baseband clock is generated based on a signal from Crystal 1 that is a source oscillation of the operation clock. The baseband clock is used at the time of digital signal processing in the BB circuit 30 and is also supplied to the RF circuit 20 and used at the time of digital signal processing in the RF circuit 20 as shown in FIG.

  In the RF circuit 20, the received signal received by the antenna 40 is subjected to digital signal processing based on the baseband clock and sent to the BB circuit 30. At this time, as shown by RxData in FIG. 3, the serial transmission start timing from the reception serial data generation unit 9 and the data transfer from the reception data extraction unit 10 to the demodulation circuit 11 in the BB circuit 30 are synchronized with the baseband clock. To be executed. Therefore, the input / output timing from the AD converter 7 to the demodulation circuit 11 is controlled by the baseband clock generated by the BB circuit 30.

  Further, in the BB circuit 30, the transmission signal transmitted from the antenna 40 is subjected to digital signal processing based on the baseband clock and sent to the RF circuit 20, but as described above, as shown in TxData in FIG. By synchronizing the serial transmission start timing from the transmission serial data generation unit 13 and the transmission of data from the transmission data extraction unit 14 to the transmission digital filter 15 of the RF circuit 20 with the baseband clock, the modulation circuits 12 to The processing timing of the DA converter 16 can also be controlled by the baseband clock.

  Further, the BB circuit 30 estimates the reception timing at the antenna 40 from the received serial data. Specifically, the reception timing at the antenna end is calculated by subtracting the stored delay time at the time of reception from the timing of receiving the received serial data. Estimate the radio timing on the base station side. And a correction process is performed according to the deviation | shift amount with this estimated radio | wireless timing. At this time, the correction is performed so that the stored delay time at the time of transmission is advanced and transmitted at the estimated wireless timing. For example, the transmission serial data generation unit 13 performs correction such as delaying or advancing 1/4 chip as shown in FIG.

  The RF circuit 20 detects whether or not the transmission timing is corrected from the timing of the transmission serial data and the baseband clock. For example, as shown in FIG. 3, transmission data is normally output every 4 clocks of the baseband clock (see TxData (Nomal)), but after -1/4 chip correction, 3 clocks after the previous input (TxData (Fast )), +1/4 chip correction will be input 5 clocks after the previous input (TxData (Slow)), so the presence of correction is detected by recognizing this. When detecting that such correction has been performed, the RF circuit 20 controls the operating coefficient of the digital filter 15 as described above.

  By doing so, the baseband clock is generated in the BB circuit 30 in which only the digital circuit is mounted and the miniaturization process is proceeding, and is also supplied to the RF circuit 20 to be used for digital signal processing. No baseband clock needs to be generated at 20, so that the circuit area can be reduced as a whole and the power consumption can be reduced. In addition, synchronization processing at the time of signal transfer between the RF circuit 20 and the BB circuit 30 is facilitated.

  Further, the radio timing can be estimated from the reception timing by the BB circuit 30, and the transmission timing correction processing of the transmission signal can be realized. Therefore, the wireless timing management function can be integrated into the BB circuit 30 constituted by a digital circuit, and the entire circuit can be further reduced in size.

  Further, it is possible to detect that the transmission timing has been corrected in the RF circuit 20 without notifying the RF circuit 20 of the presence or absence of correction from the BB circuit 30, and perform processing such as setting change associated therewith. This can be realized, and the circuit can be simplified and the power consumption can be reduced.

  The circuit according to the present invention is effective when mounted on a communication device that requires miniaturization and power saving, such as a cellular phone, and has industrial applicability.

It is a block diagram which shows the structure of a transmission / reception circuit. It is a figure explaining the flow of the signal in the transmission / reception circuit disclosed in FIG. 2 is a timing chart in the transmission / reception circuit disclosed in FIG. 1. It is a figure explaining the flow of the signal in the transmission / reception circuit in a prior art example.

Explanation of symbols

1 Crystal oscillator 2 PLL for baseband clock (for baseband clock generation)
3, 4 PLL for high-speed differential I / F operation
5 reception synthesizer 6 reception analog filter 7 reception AD converter 8 reception digital filter 9 reception serial data generation unit 10 reception data extraction unit 11 demodulation circuit 12 modulation circuit 13 transmission serial data generation unit 14 transmission data extraction unit 15 Digital filter 16 Transmission DA converter 17 Transmission analog filter 18 Transmission synthesizer 20 RF circuit 30 Baseband circuit 40 Antenna

Claims (16)

  1. A transmission / reception circuit comprising: an RF circuit that performs transmission / reception processing of a transmission / reception signal via an antenna; and a baseband circuit that performs modulation / demodulation processing of the transmission / reception signal,
    The baseband circuit generates a clock signal used for digital signal processing for the transmission / reception signal in the baseband circuit and outputs the clock signal to the RF circuit,
    The RF circuitry, have lines of digital signal processing of the transmit and receive signals based on the clock signal input from the baseband circuit,
    The baseband circuit corrects the transmission timing of a transmission signal transmitted via the antenna based on the received signal received from the RF circuit, transmits the corrected signal to the RF circuit, and transmits / receives the signal via the antenna. Holding delay time information representing a delay time due to analog signal processing of the transmission / reception signal, and correcting the transmission timing of the transmission signal based on the delay time information and the reception signal;
    A transceiver circuit characterized by the above.
  2. A transmission / reception circuit comprising: an RF circuit that performs transmission / reception processing of a transmission / reception signal via an antenna; and a baseband circuit that performs modulation / demodulation processing of the transmission / reception signal,
    The baseband circuit generates a clock signal used for digital signal processing for the transmission / reception signal in the baseband circuit and outputs the clock signal to the RF circuit,
    The RF circuit performs digital signal processing of the transmission / reception signal based on the clock signal input from the baseband circuit, and based on the transmission timing of the transmission signal transmitted from the baseband circuit and the clock signal. Detecting the presence or absence of correction of the transmission timing of the transmission signal;
    A transceiver circuit characterized by the above.
  3. Wherein said digital signal processing in the RF circuit includes a sampling processing of the reception signal received via the antenna, transmission and reception circuit according to claim 1 or 2, wherein the.
  4. Wherein said digital signal processing in the RF circuit, transmitting and receiving circuit according to any one of claims 1 to 3 comprising a process of sending the received signal to the baseband circuit, it is characterized.
  5. Wherein A RF circuit and the baseband circuit, transmitting and receiving circuit according to the transfer processing of the signals between each other, carried out at the timing based on the clock signal, any one of claims 1 to 4, characterized in that.
  6. The baseband circuit, according to claim 2, wherein on the basis of the received signal received from the RF circuit to correct the transmission timing of the transmission signal transmitted through the antenna is sent to the RF circuit, characterized in that Transmitter / receiver circuit.
  7. The baseband circuit holds delay time information indicating a delay time by analog signal processing of a transmission / reception signal transmitted / received via the antenna, and transmits the transmission signal based on the delay time information and the reception signal. The transmission / reception circuit according to claim 6 , wherein timing is corrected.
  8. The RF circuitry includes a transmitting and receiving according to claim 1, wherein on the basis of the transmission timing and the clock signal of the transmission signal transmitted from the baseband circuit for detecting the presence or absence of correction of the transmission timing of the transmission signal, characterized in that circuit.
  9. Communication apparatus comprising the transmitting and receiving circuit according to claim 1 to 8, wherein.
  10. Claims 1 to a mobile phone characterized by comprising a transceiver circuit according 8.
  11. A transmission / reception signal processing method by a transmission / reception circuit comprising: an RF circuit that performs transmission / reception processing of a transmission / reception signal via an antenna; and a baseband circuit that performs modulation / demodulation processing of the transmission / reception signal,
    The baseband circuit generates a clock signal used for digital signal processing for the transmission / reception signal in the baseband circuit and outputs the clock signal to the RF circuit;
    The RF circuit and the baseband circuit, have a row of digital signal processing of the transmit and receive signals based on the clock signal,
    At the time of the digital signal processing, the baseband circuit corrects the transmission timing of the transmission signal transmitted via the antenna based on the received signal received from the RF circuit and sends it to the RF circuit. Correcting the transmission timing of the transmission signal based on delay time information representing a delay time by analog signal processing of a transmission / reception signal transmitted / received via the antenna held in advance by the circuit, and the reception signal,
    And a transmission / reception signal processing method.
  12. A transmission / reception signal processing method by a transmission / reception circuit comprising: an RF circuit that performs transmission / reception processing of a transmission / reception signal via an antenna; and a baseband circuit that performs modulation / demodulation processing on the transmission / reception signal
    The baseband circuit generates a clock signal used for digital signal processing for the transmission / reception signal in the baseband circuit and outputs the clock signal to the RF circuit;
    The RF circuit and the baseband circuit, have a row of digital signal processing of the transmit and receive signals based on the clock signal,
    At the time of the digital signal processing, the RF circuit detects whether or not the transmission timing of the transmission signal is corrected based on the transmission timing of the transmission signal transmitted from the baseband circuit and the clock signal.
    And a transmission / reception signal processing method.
  13. 13. The transmission / reception signal processing method according to claim 11 or 12 , wherein, during the digital signal processing, the RF circuit and the baseband circuit perform a signal transfer process between them at a timing based on the clock signal. .
  14. During the digital signal processing, the baseband circuit corrects the transmission timing of the transmission signal transmitted via the antenna based on the received signal received from the RF circuit, and transmits the corrected signal to the RF circuit. The transmission / reception signal processing method according to claim 12 .
  15. At the time of the digital signal processing, the transmission based on delay time information representing a delay time by analog signal processing of a transmission / reception signal transmitted / received via the antenna held in advance by the baseband circuit, and the received signal 15. The transmission / reception signal processing method according to claim 14 , wherein signal transmission timing is corrected.
  16. The RF circuit detects the presence or absence of correction of the transmission timing of the transmission signal based on the transmission timing of the transmission signal transmitted from the baseband circuit and the clock signal during the digital signal processing. Item 12. The transmission / reception signal processing method according to Item 11 .
JP2006146050A 2006-05-26 2006-05-26 Transmission / reception circuit, communication device including the same, and transmission / reception signal processing method Expired - Fee Related JP4687567B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006146050A JP4687567B2 (en) 2006-05-26 2006-05-26 Transmission / reception circuit, communication device including the same, and transmission / reception signal processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006146050A JP4687567B2 (en) 2006-05-26 2006-05-26 Transmission / reception circuit, communication device including the same, and transmission / reception signal processing method

Publications (2)

Publication Number Publication Date
JP2007318462A JP2007318462A (en) 2007-12-06
JP4687567B2 true JP4687567B2 (en) 2011-05-25

Family

ID=38851924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006146050A Expired - Fee Related JP4687567B2 (en) 2006-05-26 2006-05-26 Transmission / reception circuit, communication device including the same, and transmission / reception signal processing method

Country Status (1)

Country Link
JP (1) JP4687567B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5330772B2 (en) * 2008-08-29 2013-10-30 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit and operation method thereof
JP5070238B2 (en) * 2009-03-30 2012-11-07 アンリツ株式会社 Mobile communication device test system and test method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268619A (en) * 1993-03-17 1994-09-22 Matsushita Electric Ind Co Ltd Data transmitter for time division multiplexing
JP2000152300A (en) * 1998-11-06 2000-05-30 Toshiba Corp Radio communication base station system, receiver for radio signal optical transmission and transmitter- receiver for radio signal optical transmission
JP2004519943A (en) * 2001-03-17 2004-07-02 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィKoninklijke Philips Electronics N.V. Interface concept for exchanging digital signals between RFIC and baseband IC
JP2004312150A (en) * 2003-04-03 2004-11-04 Nippon Telegr & Teleph Corp <Ntt> Digital radio-over-fiber transmission system
WO2005034544A1 (en) * 2003-09-30 2005-04-14 Telefonaktiebolaget Lm Ericsson (Publ) Interface, apparatus, and method for communication between a radio equipment control node and a remote radio equipment node in a radio base station
JP2007096762A (en) * 2005-09-29 2007-04-12 Toshiba Corp Radio device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268619A (en) * 1993-03-17 1994-09-22 Matsushita Electric Ind Co Ltd Data transmitter for time division multiplexing
JP2000152300A (en) * 1998-11-06 2000-05-30 Toshiba Corp Radio communication base station system, receiver for radio signal optical transmission and transmitter- receiver for radio signal optical transmission
JP2004519943A (en) * 2001-03-17 2004-07-02 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィKoninklijke Philips Electronics N.V. Interface concept for exchanging digital signals between RFIC and baseband IC
JP2004312150A (en) * 2003-04-03 2004-11-04 Nippon Telegr & Teleph Corp <Ntt> Digital radio-over-fiber transmission system
WO2005034544A1 (en) * 2003-09-30 2005-04-14 Telefonaktiebolaget Lm Ericsson (Publ) Interface, apparatus, and method for communication between a radio equipment control node and a remote radio equipment node in a radio base station
JP2007507957A (en) * 2003-09-30 2007-03-29 ジーメンス・アー・ゲー Communication interface, communication apparatus, and communication method between radio apparatus controller node and remote radio apparatus node in radio base station
JP2007096762A (en) * 2005-09-29 2007-04-12 Toshiba Corp Radio device

Also Published As

Publication number Publication date
JP2007318462A (en) 2007-12-06

Similar Documents

Publication Publication Date Title
EP0526388B1 (en) Radio communication system wherein transceivers retransmit messages in synchronism
US7403556B2 (en) Radio receiver supporting multiple modulation formats with a single pair of ADCs
EP0937349B1 (en) Synchronization in tdma systems in a non-real-time fashion
TWI258963B (en) Apparatus and method for low complexity synchronization for wireless transmission
EP1471653A1 (en) Direct conversion receiver and dc offset reducing method
RU2296435C2 (en) System and device for performing broadcast transfer of data and transferring local broadcast data
EP0693835B1 (en) Synchronization of a wireless telephone
JP2005203960A (en) Method for adjusting timing of radio communication equipment
JP3551235B2 (en) AFC circuit
DE60005030T2 (en) Multimode radio communication device with common reference oscillator
EP0744840A2 (en) CDMA receiver with reduced power consumption in intermittent state
KR20000011176A (en) Time synchronization method in cdma system
FR2645375A1 (en) Mobile telephone system with intermittent control of receiver components in a waiting status
JPWO2006082628A1 (en) Inter-base station synchronization system, synchronization control device, and base station
TW200715703A (en) Apparatus and method for sampling frequency offset estimation and correction in a wireless communication system
JP2001215267A (en) Receiving terminal and portable wireless terminal for global positioning system
WO2007049698A1 (en) Mobile communication system, base station, mobile station, and power-saving transmission/reception method used in them
DE102004043918B4 (en) Digital receiver and radio communication system
JP2004320739A (en) Uplink/downlink synchronizing apparatus for mobile communication terminal
US20080108318A1 (en) Ultra low-power wake-up receiver
KR20000070944A (en) Circuit for synchronizing cdma mobile phones
CN1156181C (en) Self adaption method for reducing power consumption of digital radio communication system in waisting status
EP0805560A3 (en) Digital PLL circuit and initial setting method
JP4341176B2 (en) Reception synchronizer and demodulator using the same
EP1269651A2 (en) Symbol combiner synchronization after a jump to a new time alignment

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090415

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20100604

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101004

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101019

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101125

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110118

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110131

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140225

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees