JP4673039B2 - Mask blank substrate - Google Patents

Mask blank substrate Download PDF

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JP4673039B2
JP4673039B2 JP2004322676A JP2004322676A JP4673039B2 JP 4673039 B2 JP4673039 B2 JP 4673039B2 JP 2004322676 A JP2004322676 A JP 2004322676A JP 2004322676 A JP2004322676 A JP 2004322676A JP 4673039 B2 JP4673039 B2 JP 4673039B2
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corners
substrate
shielding film
light
transparent
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JP2006133519A (en
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亮一 平野
日出夫 齊藤
宗博 小笠原
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Toshiba Corp
Nuflare Technology Inc
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Description

本発明は、光リソグラフィーにおいて使用される露光用マスクを形成するためのマスクブランクス基板に関する。   The present invention relates to a mask blank substrate for forming an exposure mask used in photolithography.

半導体製造プロセスの一つである光リソグラフィプロセスにおいては、透明基板上に遮光膜のパターンを形成した露光用マスクが用いられる。この露光用マスクは、溶融石英等の透明基板の一主面上にクロム等の遮光膜を成膜したマスクブランクス基板を基に、電子ビームリソグラフィーにより作製される(例えば、特許文献1参照)。   In a photolithography process which is one of semiconductor manufacturing processes, an exposure mask in which a light shielding film pattern is formed on a transparent substrate is used. This exposure mask is produced by electron beam lithography on the basis of a mask blanks substrate in which a light-shielding film such as chromium is formed on one main surface of a transparent substrate such as fused silica (for example, see Patent Document 1).

マスクブランクス基板の遮光膜にパターンを形成するプロセスは、以下の通りである。まず、遮光膜表面にレジストを塗布し、これに真空中でパターンを形成すべき場所に電子ビームを照射する。電子ビーム照射後、現像してレジストパターンを得、このレジストパターンをマスクとして遮光膜のエッチングを行い、遮光膜パターンを得る。   The process for forming the pattern on the light shielding film of the mask blank substrate is as follows. First, a resist is applied to the surface of the light-shielding film, and an electron beam is irradiated to a place where a pattern is to be formed in a vacuum. After the electron beam irradiation, development is performed to obtain a resist pattern, and the light shielding film is etched using the resist pattern as a mask to obtain a light shielding film pattern.

ところで、マスクブランクス基板を製造するために遮光膜を透明基板上に形成する際には、一般にスパッタ法が用いられる。その際に、透明基板を支持するために4隅をクランプするが、透明基板を支持した領域にはクランプするための保持機構が邪魔になって遮光膜が形成されない。従って、マスクブランクス基板の4隅は、遮光膜が形成されずに透明基板である溶融石英が剥き出しとなっている。   By the way, when forming a light shielding film on a transparent substrate in order to manufacture a mask blank substrate, a sputtering method is generally used. At that time, the four corners are clamped to support the transparent substrate, but the light-shielding film is not formed in the region supporting the transparent substrate because the holding mechanism for clamping becomes an obstacle. Therefore, at the four corners of the mask blank substrate, the light-shielding film is not formed, and the fused quartz that is a transparent substrate is exposed.

溶融石英は優れた絶縁体であり、体積抵抗率は1016Ωm以上とされている。従って、電子ビームを用いてパターニングを行う際に、この溶融石英部分に電子が入射すると、この部分は帯電する。真空中の絶縁破壊が起こる電場の強さは条件によって異なるが、文献(例えば、非特許文献1参照)によればオーダー的には50MV/m程度とされているので、電荷密度が20nc/cm2 程度になると、放電が生じる可能性がある。放電が生じると、塗布されたレジスト或いはガラスが遮光膜の上に飛散し、飛散したレジスト或いはガラスは遮光膜パターンの欠陥の原因となる。 Fused quartz is an excellent insulator and has a volume resistivity of 10 16 Ωm or more. Therefore, when patterning is performed using an electron beam, if electrons enter the fused silica portion, the portion is charged. The strength of the electric field at which dielectric breakdown occurs in vacuum varies depending on conditions, but according to the literature (for example, see Non-Patent Document 1), the order is about 50 MV / m, so the charge density is 20 nc / cm. When it is about 2 , discharge may occur. When discharge occurs, the applied resist or glass is scattered on the light shielding film, and the scattered resist or glass causes a defect in the light shielding film pattern.

なお、遮光膜のない部分は4隅であり、LSIパターンは基板の周辺を除く部分に形成されるため、遮光膜のない部分に電子ビームが照射されることはないように思えるが、識別マークやプロセスマーク等は基板の周辺部分に形成するため、遮光膜のない部分に電子ビームが照射されることが生じる。
特開平11−54077号公報 放電ハンドブック(改訂版)電気学会、第3部第4章 P220
The part without the light shielding film has four corners, and the LSI pattern is formed in the part other than the periphery of the substrate. Therefore, it seems that the part without the light shielding film is not irradiated with the electron beam. Since the process mark and the like are formed in the peripheral portion of the substrate, the electron beam may be irradiated to the portion without the light shielding film.
Japanese Patent Laid-Open No. 11-54077 Discharge Handbook (Revised) The Institute of Electrical Engineers of Japan, Part 3, Chapter 4, P220

このように従来、マスクブランクス基板の表面には遮光膜の形成されていない部分が4隅に存在し、この部分に電子ビームが照射されると、レジストの帯電や放電破壊が生じ、ゴミが発生し、遮光膜パターンの欠陥の原因となるという問題があった。   Thus, conventionally, there are four portions where no light-shielding film is formed on the surface of the mask blank substrate, and when this portion is irradiated with an electron beam, resist charging or discharge breakdown occurs, and dust is generated. However, there is a problem of causing a defect in the light shielding film pattern.

また、上記の問題は、電子ビームによってパターンを描画する場合に限らず、イオンビームによってパターンを描画する場合にも同様に言えることである。   Further, the above problem is not limited to the case where a pattern is drawn by an electron beam, but the same can be said when a pattern is drawn by an ion beam.

本発明は、上記事情を考慮してなされたもので、その目的とするところは、荷電ビーム照射に伴うレジストの帯電及び放電破壊を防止することができ、露光用マスクにおけるパターン精度の向上及び製造歩留まりの向上に寄与し得るマスクブランクス基板及びその製造方法を提供することにある。   The present invention has been made in consideration of the above circumstances, and the object of the present invention is to prevent resist charging and discharge breakdown due to charged beam irradiation, and to improve and manufacture pattern accuracy in an exposure mask. An object of the present invention is to provide a mask blank substrate that can contribute to an improvement in yield and a method for manufacturing the same.

上記課題を解決するために本発明は、次のような構成を採用している。   In order to solve the above problems, the present invention adopts the following configuration.

即ち、本発明の一態様に係わるマスクブランクス基板は、露光光に対して透明な透明基板と、前記透明基板の一主面上に該基板の4隅を除いて形成され、露光光に対して不透明な導電性材料からなり、荷電ビームリソグラフィーを含むプロセスによりパターンを形成するための遮光膜と、前記透明基板の一主面上の4隅の少なくとも1つに形成されたマークと、前記4隅を覆うように形成された透明導電膜と、を具備してなることを特徴とする。 That is , a mask blank substrate according to an aspect of the present invention is formed on a transparent substrate transparent to exposure light and on one main surface of the transparent substrate except for the four corners of the substrate. A light shielding film made of an opaque conductive material for forming a pattern by a process including charged beam lithography, a mark formed at at least one of four corners on one main surface of the transparent substrate, and the four corners And a transparent conductive film formed so as to cover the surface.

また、本発明の別の態様に係わるマスクブランクス基板の製造方法は、露光光に対して透明な透明基板の一主面上の4隅をクランプした状態で、該基板の一主面上の4隅を除く部分にスパッタ又は蒸着法により、露光光に対して不透明な導電材料からなり、荷電ビームリソグラフィーを含むプロセスによりパターンを形成するための遮光膜を成膜する工程と、前記透明基板の一主面上の4隅を除く部分を遮蔽するシャッターを用い、前記4隅の内の2つをクランプした状態で、クランプされていない2隅にスパッタ又は蒸着法により前記遮光膜又は該遮光膜とは材料の異なる導電膜を成膜する工程と、前記シャッターを用い、前記クランプする位置を別の2隅に変更した状態で、クランプされていない2隅にスパッタ又は蒸着法により前記遮光膜又は該遮光膜とは材料の異なる導電膜を成膜する工程と、を含むことを特徴とする。   Moreover, the manufacturing method of the mask blank board | substrate concerning another aspect of this invention is the state which clamped four corners on one main surface of the transparent substrate transparent with respect to exposure light, 4 on the one main surface of this board | substrate. A step of forming a light-shielding film made of a conductive material opaque to exposure light by sputtering or vapor deposition on a portion other than the corner and forming a pattern by a process including charged beam lithography; Using a shutter that shields a portion excluding the four corners on the main surface, with the two of the four corners clamped, the light shielding film or the light shielding film is formed by sputtering or vapor deposition on the two unclamped corners. In the state in which a conductive film made of a different material is formed, and the shutter is used and the clamping position is changed to two other corners, the two non-clamped corners are sputtered or deposited by sputtering. Characterized in that it comprises a and a step of forming a different conductive layer of material is a film or a light shielding film.

また、本発明の別の態様に係わるマスクブランクス基板の製造方法は、露光光に対して透明な透明基板の一主面上の4隅をクランプした状態で、該基板の一主面上の4隅を除く部分にスパッタ法又は蒸着法により、露光光に対して不透明な導電材料からなり、荷電ビームリソグラフィーを含むプロセスによりパターンを形成するための遮光膜を成膜し、且つ前記4隅の少なくとも1つに前記遮光膜からなるマークを形成する工程と、前記透明基板の一主面上の4隅を除く部分を遮蔽するシャッターを用い、前記4隅の内の2つをクランプした状態で、クランプされていない2隅にスパッタ又は蒸着法により透明導電膜を成膜する工程と、前記シャッターを用い、前記クランプする位置を別の2隅に変更した状態で、クランプされていない2隅にスパッタ又は蒸着法により透明導電膜を成膜する工程と、を含むことを特徴とする。   Moreover, the manufacturing method of the mask blank board | substrate concerning another aspect of this invention is the state which clamped four corners on one main surface of the transparent substrate transparent with respect to exposure light, 4 on the one main surface of this board | substrate. A light shielding film for forming a pattern by a process including charged beam lithography is formed on a portion excluding the corner by a sputtering method or a vapor deposition method, and is made of a conductive material opaque to exposure light, and at least the four corners are formed. In a state where two of the four corners are clamped using a step of forming a mark made of the light-shielding film in one and a shutter that shields a portion excluding the four corners on one main surface of the transparent substrate. A step of forming a transparent conductive film by sputtering or vapor deposition at two unclamped corners, and two unclamped corners using the shutter and changing the clamping position to another two corners. A step of forming a sputtering or transparent conductive film by a vapor deposition method, to include the features.

本発明によれば、透明基板の一主面上の4隅を含めて全面が導電性の膜で覆われているため、遮光膜パターン形成のための荷電ビーム照射によってレジストが帯電することはなく、放電破壊を未然に防止することができる。従って、ゴミの発生を抑制することができ、遮光膜パターンのパターン精度の向上、更には製造歩留まりの向上をはかることができる。   According to the present invention, since the entire surface including the four corners on one main surface of the transparent substrate is covered with the conductive film, the resist is not charged by the charged beam irradiation for forming the light shielding film pattern. , Discharge breakdown can be prevented in advance. Therefore, the generation of dust can be suppressed, the pattern accuracy of the light shielding film pattern can be improved, and the manufacturing yield can be improved.

以下、本発明の詳細を図示の実施形態によって説明する。   The details of the present invention will be described below with reference to the illustrated embodiments.

(第1の実施形態)
図1は、本発明の第1の実施形態に係わるマスクブランクス基板の概略構成を説明するためのもので、(a)は平面図、(b)は(a)の矢視A−A’断面図である。
(First embodiment)
1A and 1B are diagrams for explaining a schematic configuration of a mask blank substrate according to a first embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. FIG.

図中11は溶融石英からなる透明基板であり、この基板11の上面の全体はクロム(Cr)からなる遮光膜12が形成されている。また、この遮光膜12は、基板11の側面にも形成されている。   In the figure, reference numeral 11 denotes a transparent substrate made of fused quartz, and a light shielding film 12 made of chromium (Cr) is formed on the entire upper surface of the substrate 11. The light shielding film 12 is also formed on the side surface of the substrate 11.

ここでは代表的な構成として、152mmレチクルを考える。透明基板11は、パターン形成面が一片152mmの正方形、厚さ6.25mmの直方体構造に加工されている。パターン形成面への遮光膜形成は次のようにして行う。   Here, a 152 mm reticle is considered as a typical configuration. The transparent substrate 11 is processed into a rectangular parallelepiped structure with a pattern forming surface of a square having a piece of 152 mm and a thickness of 6.25 mm. The light shielding film is formed on the pattern forming surface as follows.

まず、通常の保持機構を有するスパッタ装置により、透明基板の一主面上に金属クロム膜(遮光膜)を200nm成膜する。この際に、図2(a)に示すように、基板11の4隅を保持機構21a〜21dでクランプする。このため、図2(b)に示すように、基板11の4隅11a〜11dにはクロム膜12は成膜されない。この状態は、従来のマスクブランクス基板と同様である。また、スパッタの回り込みを利用することにより、基板11の側面にもクロム膜12が成膜される。   First, a 200-nm-thick metal chromium film (light-shielding film) is formed on one main surface of the transparent substrate by a sputtering apparatus having a normal holding mechanism. At this time, as shown in FIG. 2A, the four corners of the substrate 11 are clamped by the holding mechanisms 21a to 21d. For this reason, as shown in FIG. 2B, the chromium film 12 is not formed at the four corners 11 a to 11 d of the substrate 11. This state is the same as that of a conventional mask blank substrate. Further, the chromium film 12 is also formed on the side surface of the substrate 11 by utilizing the wraparound of sputtering.

次に、図2(c)に示すように、4隅11a〜11dのうち、対角線の両端にある2対の隅うちのどちらか1対の隅のみ、ここでは11b,11dを保持機構21b,21dでクランプする。そして、基板11上のクロム膜形成領域と同じ形状のシャッター22を用いて、4隅以外には成膜材料が付かないようにする。この状態で、再度スパッタすることによりクロム膜を成膜する。すると、図2(d)に示すように、4隅の内の11a,11cにクロム膜12が成膜される。   Next, as shown in FIG. 2 (c), of the four corners 11a to 11d, only one of the two pairs of corners at both ends of the diagonal line, here the 11b and 11d are held by the holding mechanism 21b, Clamp with 21d. Then, using the shutter 22 having the same shape as the chromium film forming region on the substrate 11, no film forming material is attached to the corners other than the four corners. In this state, a chromium film is formed by sputtering again. Then, as shown in FIG. 2D, a chromium film 12 is formed on 11a and 11c in the four corners.

次に、図2(e)に示すように、残りの1対の隅11a,11cのみを保持機構21a,21cによりクランプし、先と同様にシャッター22を用いてクロム膜をスパッタ法により成膜する。すると、図2(f)に示すように、残りの2隅11b,11dにもクロム膜12が成膜されることになる。このようにしてマスクのパターン形成面全面に導体膜を成膜することができる。この後、必要があればシャッター22を開き、クロム膜12の表面に酸化クロム膜を成膜する。   Next, as shown in FIG. 2 (e), only the remaining pair of corners 11a and 11c are clamped by the holding mechanisms 21a and 21c, and a chromium film is formed by sputtering using the shutter 22 as before. To do. Then, as shown in FIG. 2F, the chromium film 12 is also formed at the remaining two corners 11b and 11d. In this way, a conductor film can be formed on the entire pattern formation surface of the mask. Thereafter, if necessary, the shutter 22 is opened, and a chromium oxide film is formed on the surface of the chromium film 12.

なお、4隅以外へのクロム膜12の成膜と4隅へのクロム膜12の成膜とは、同じスパッタ装置を用いてもよいし、異なるスパッタ装置を用いてもよい。また、4隅へのクロム膜の成膜を行うことにより、基板11の4隅に対応する側面にもクロム膜12が成膜されることになる。   The same sputtering apparatus or different sputtering apparatuses may be used for the formation of the chromium film 12 at the four corners and the formation of the chromium film 12 at the four corners. Further, by forming the chromium film at the four corners, the chromium film 12 is also formed on the side surfaces corresponding to the four corners of the substrate 11.

このように本実施形態によれば、透明基板11のパターン形成面に基板11の4隅を含んで全面にクロム膜12を形成することができ、基板表面全体が導体膜で覆われた状態となる。従って、このマスクブランクス基板を用いて電子ビームによりパターンを描画した場合、レジストの帯電や放電破壊が生じることはなく、パターン精度の向上及び製造歩留まりの向上をはかることができる。   As described above, according to this embodiment, the chromium film 12 can be formed on the entire surface including the four corners of the substrate 11 on the pattern forming surface of the transparent substrate 11, and the entire substrate surface is covered with the conductor film. Become. Therefore, when a pattern is drawn by an electron beam using this mask blank substrate, the resist is not charged or discharged, and the pattern accuracy can be improved and the manufacturing yield can be improved.

また、本実施形態では、スパッタリングの際の回り込みを利用することにより、透明基板11の上面のみならず側面にもクロム膜12を成膜することができる。このように側面にも導電膜を形成しておくことは、電子ビーム照射による帯電防止により有効となる。   In the present embodiment, the chromium film 12 can be formed not only on the upper surface of the transparent substrate 11 but also on the side surfaces by utilizing the wraparound at the time of sputtering. Forming a conductive film on the side surface in this way is effective for preventing charging by electron beam irradiation.

(第2の実施形態)
図3は、本発明の第2の実施形態に係わるマスクブランクス基板の概略構成を説明するためのもので、(a)は平面図、(b)は(a)の矢視B−B’断面図である。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
(Second Embodiment)
3A and 3B are diagrams for explaining a schematic configuration of a mask blank substrate according to the second embodiment of the present invention, in which FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line BB ′ in FIG. FIG. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.

本実施形態は、4隅の一部に目視による確認の可能なマークパターンを形成したものである。   In the present embodiment, mark patterns that can be visually confirmed are formed in part of four corners.

透明基板11の一主面上に4隅を除いてクロム膜12が形成され、4隅の一部にマーク13が形成されている。このマーク13は、マスクの特徴を表すものであり、後述するようにクロム膜の成膜時のクランプを工夫することにより形成できる。そして、4隅には、ITOからなる透明導電膜15が形成されている。   A chromium film 12 is formed on one main surface of the transparent substrate 11 except for the four corners, and a mark 13 is formed at a part of the four corners. This mark 13 represents the characteristics of the mask, and can be formed by devising a clamp when forming the chromium film, as will be described later. Transparent conductive films 15 made of ITO are formed at the four corners.

本実施形態では、先の実施形態と同様に、前記図2(a)(b)に示すように、通常の保持機構を有するスパッタ装置により、透明基板11の4隅をクランプした状態でスパッタすることにより該基板11上に金属クロム膜12を200nmの厚さに成膜する。これにより、4隅には遮光膜の形成されない領域が残り、4隅に透明基板11が露出することになる。このとき、4隅の内の1つに例えば三角形状のマーク13を付けておく。   In the present embodiment, as in the previous embodiment, as shown in FIGS. 2A and 2B, sputtering is performed with the four corners of the transparent substrate 11 clamped by a sputtering apparatus having a normal holding mechanism. As a result, a metal chromium film 12 is formed on the substrate 11 to a thickness of 200 nm. As a result, regions where no light shielding film is formed remain at the four corners, and the transparent substrate 11 is exposed at the four corners. At this time, for example, a triangular mark 13 is attached to one of the four corners.

マーク13は、マスクの特徴(種別,露光条件,その他)を表すものであり、例えば図4に示すように、保持機構21の一部に三角形状の切り欠き部23を設けておくことにより、透明基板11の上面全体への遮光膜形成と同時に形成される。このようなマーク13を形成する個数、或いは形成位置を適宜組み合わせることにより、マスクの特徴に応じたマーク形成を行うことができる。   The mark 13 represents the characteristics (type, exposure condition, etc.) of the mask. For example, as shown in FIG. 4, by providing a triangular notch 23 in a part of the holding mechanism 21, It is formed simultaneously with the formation of the light shielding film on the entire upper surface of the transparent substrate 11. By appropriately combining the number of the marks 13 to be formed or the formation position, marks can be formed according to the characteristics of the mask.

次に、上記のスパッタ装置とは別のスパッタ装置に上記の基板をセットし、透明基板11上の4隅のうち、対角線の両端にある2対の隅の片方である1対の隅のみを保持機構でクランプする。ここで、第1の実施形態と同様のシャッターを用いて、4隅以外には膜材料が付かないようにする。この状態で、導電性で且つ可視光を透過する膜、例えばITO膜15をスパッタリングにより成膜する。このITO膜15は、一部が先に形成したクロム膜と重なるようにする。   Next, the substrate is set in a sputtering apparatus different from the above-described sputtering apparatus, and only one pair of corners, which is one of two corners at both ends of the diagonal line, among the four corners on the transparent substrate 11 is formed. Clamp with holding mechanism. Here, the same shutter as in the first embodiment is used so that no film material is attached to the corners other than the four corners. In this state, a conductive film that transmits visible light, for example, an ITO film 15 is formed by sputtering. This ITO film 15 is partially overlapped with the previously formed chromium film.

次に、残りの1対の隅で透明基板11を支持し、先に支持されていた方の1対の隅にITO膜15を成膜する。このようにして、マスクのパターン形成面全面に導体膜を成膜することができる。なお、上記例ではクロム膜とITO膜との成膜には別のスパッタ装置を用いたが、同じスパッタ装置を用いてターゲットを変えるようにしてもよい。   Next, the transparent substrate 11 is supported by the remaining pair of corners, and the ITO film 15 is formed on the pair of corners that have been previously supported. In this manner, a conductor film can be formed over the entire pattern formation surface of the mask. In the above example, another sputtering apparatus is used for forming the chromium film and the ITO film, but the target may be changed using the same sputtering apparatus.

ここで、4隅を1辺が5mmの二等辺三角形と考える。マスクパターンの形成に使用される電子ビーム描画装置のビーム電流は高々3μAである。幅平均2.5mmで、長さ5mmの領域を3μAの電流が流れるときの電位差が5mmで10kV程度であるとすると、許される抵抗値は3GΩ程度となる。10倍の安全率をみると許される抵抗値は300MΩである。膜の厚さは通常0.1μm程度であるから、膜の体積抵抗率は6×10-2Ωm以下であることが必要である。ITO膜はこれよりも十分に低い抵抗率を有するため、4隅をカバーする導電膜として十分に使用可能である。 Here, it is considered that the four corners are isosceles triangles each having a side of 5 mm. The beam current of the electron beam lithography apparatus used for forming the mask pattern is at most 3 μA. If the potential difference when a current of 3 μA flows through a region having a width average of 2.5 mm and a length of 5 mm is about 10 kV at 5 mm, the allowable resistance value is about 3 GΩ. When the safety factor is 10 times, the allowable resistance value is 300 MΩ. Since the thickness of the film is usually about 0.1 μm, the volume resistivity of the film needs to be 6 × 10 −2 Ωm or less. Since the ITO film has a sufficiently lower resistivity, it can be sufficiently used as a conductive film covering the four corners.

このように本実施形態によれば、透明基板11のパターン形成面に基板11の4隅を除いてクロム膜12を形成し、4隅にITO膜15を形成することができ、基板表面全体が導体膜で覆われた状態となる。従って、先の第1の実施形態と同様の効果が得られる。   As described above, according to the present embodiment, the chromium film 12 can be formed on the pattern forming surface of the transparent substrate 11 except for the four corners of the substrate 11, and the ITO film 15 can be formed at the four corners. It will be in the state covered with the conductor film. Therefore, the same effect as in the first embodiment can be obtained.

(変形例)
なお、本発明は上述した各実施形態に限定されるものではない。実施形態では、電子ビーム描画により遮光膜にパターンが描画されるものとしたが、イオンビームで描画する場合にも適用できる。また、透明基板は必ずしも溶融石英に限るものではなく、露光光に対して透明若しくは十分に透過率が高い材料であればよい。さらに、遮光膜はクロムに限るものではなく、露光光を遮光するもので、且つ導電性の材料であればよい。
(Modification)
The present invention is not limited to the above-described embodiments. In the embodiment, the pattern is drawn on the light-shielding film by electron beam drawing, but the present invention can also be applied to drawing by an ion beam. In addition, the transparent substrate is not necessarily limited to fused quartz, and may be any material that is transparent or sufficiently high in transmittance with respect to exposure light. Furthermore, the light-shielding film is not limited to chromium, but may be any material that shields exposure light and is conductive.

また、遮光膜或いは導電膜を形成する手法としては、必ずしもスパッタ法に限るものではなく、蒸着法を利用しても良い。その他、本発明の要旨を逸脱しない範囲で、種々変形して実施することができる。   Further, the method for forming the light shielding film or the conductive film is not necessarily limited to the sputtering method, and an evaporation method may be used. In addition, various modifications can be made without departing from the scope of the present invention.

第1の実施形態に係わるマスクブランクス基板の概略構成を示す平面図と断面図。The top view and sectional drawing which show schematic structure of the mask blanks board | substrate concerning 1st Embodiment. 第1の実施形態のマスクブランクスの製造工程を示す平面図。The top view which shows the manufacturing process of the mask blank of 1st Embodiment. 第2の実施形態に係わるマスクブランクス基板の概略構成を示す平面図と断面図。The top view and sectional drawing which show schematic structure of the mask blanks board | substrate concerning 2nd Embodiment. 第2の実施形態に用いた保持機構の形状を示す平面図。The top view which shows the shape of the holding mechanism used for 2nd Embodiment.

符号の説明Explanation of symbols

11…溶融石英基板(透明基板)
11a〜11d…角部
12…クロム膜(遮光膜)
13…マーク
15…透明導電膜
21…(21a〜21d)…保持機構
22…シャッター
23…切り欠き部
11 ... Fused quartz substrate (transparent substrate)
11a to 11d ... corner 12 ... chromium film (light-shielding film)
DESCRIPTION OF SYMBOLS 13 ... Mark 15 ... Transparent electrically conductive film 21 ... (21a-21d) ... Holding mechanism 22 ... Shutter 23 ... Notch

Claims (5)

露光光に対して透明な透明基板と、
前記透明基板の一主面上に該基板の4隅を除いて形成され、露光光に対して不透明な導電性材料からなり、荷電ビームリソグラフィーを含むプロセスによりパターンを形成するための遮光膜と、
前記透明基板の一主面上の4隅の少なくとも1つに形成されたマークと、
前記4隅を覆うように形成された透明導電膜と、
を具備してなることを特徴とするマスクブランクス基板。
A transparent substrate transparent to the exposure light;
A light-shielding film that is formed on one main surface of the transparent substrate except for the four corners of the substrate, is made of a conductive material that is opaque to exposure light, and forms a pattern by a process including charged beam lithography;
Marks formed in at least one of the four corners on one main surface of the transparent substrate;
A transparent conductive film formed to cover the four corners;
The mask blank board | substrate characterized by comprising.
前記マークは、前記遮光膜と同じ材料からなり、該遮光膜と同時に形成されたものであることを特徴とする請求項記載のマスクブランクス基板。 The mark is made of the same material as the light shielding film, the mask blanks substrate according to claim 1, characterized in that formed at the same time as the light-shielding film. 露光光に対して透明な透明基板の一主面上の4隅をクランプした状態で、該基板の一主面上の4隅を除く部分にスパッタ又は蒸着法により、露光光に対して不透明な導電材料からなり、荷電ビームリソグラフィーを含むプロセスによりパターンを形成するための遮光膜を成膜する工程と、
前記透明基板の一主面上の4隅を除く部分を遮蔽するシャッターを用い、前記4隅の内の2つをクランプした状態で、クランプされていない2隅にスパッタ又は蒸着法により前記遮光膜又は該遮光膜とは材料の異なる導電膜を成膜する工程と、
前記シャッターを用い、前記クランプする位置を別の2隅に変更した状態で、クランプされていない2隅にスパッタ又は蒸着法により前記遮光膜又は該遮光膜とは材料の異なる導電膜を成膜する工程と、
を含むことを特徴とするマスクブランクス基板の製造方法。
With the four corners on one principal surface of the transparent substrate transparent to the exposure light clamped, the portion other than the four corners on the one principal surface of the substrate is opaque to the exposure light by sputtering or vapor deposition. A step of forming a light shielding film made of a conductive material and forming a pattern by a process including charged beam lithography,
The light-shielding film is formed by sputtering or vapor deposition at two unclamped corners in a state where two of the four corners are clamped using a shutter that shields a portion excluding the four corners on one main surface of the transparent substrate. Or forming a conductive film made of a material different from that of the light shielding film;
Using the shutter, the light-shielding film or a conductive film made of a material different from the light-shielding film is formed by sputtering or vapor deposition in two unclamped corners with the clamping position changed to two other corners. Process,
The manufacturing method of the mask blank board | substrate characterized by including.
露光光に対して透明な透明基板の一主面上の4隅をクランプした状態で、該基板の一主面上の4隅を除く部分にスパッタ法又は蒸着法により、露光光に対して不透明な導電材料からなり、荷電ビームリソグラフィーを含むプロセスによりパターンを形成するための遮光膜を成膜し、且つ前記4隅の少なくとも1つに前記遮光膜からなるマークを形成する工程と、
前記透明基板の一主面上の4隅を除く部分を遮蔽するシャッターを用い、前記4隅の内の2つをクランプした状態で、クランプされていない2隅にスパッタ又は蒸着法により透明導電膜を成膜する工程と、
前記シャッターを用い、前記クランプする位置を別の2隅に変更した状態で、クランプされていない2隅にスパッタ又は蒸着法により透明導電膜を成膜する工程と、
を含むことを特徴とするマスクブランクス基板の製造方法。
With the four corners on one principal surface of the transparent substrate transparent to the exposure light clamped, the portion other than the four corners on the one principal surface of the substrate is opaque to the exposure light by sputtering or vapor deposition. Forming a light shielding film made of a conductive material and forming a pattern by a process including charged beam lithography, and forming a mark made of the light shielding film in at least one of the four corners;
A transparent conductive film is formed by sputtering or vapor deposition at two unclamped corners in a state where two of the four corners are clamped using a shutter that shields a portion excluding the four corners on one main surface of the transparent substrate. Forming a film;
Using the shutter, with the clamping position changed to another two corners, forming a transparent conductive film by sputtering or vapor deposition at the two unclamped corners;
The manufacturing method of the mask blank board | substrate characterized by including.
前記透明基板の一主面上の4隅をクランプする際に、各々の隅と一部接触する保持機構をそれぞれ用い、これらの保持機構の少なくとも1つに前記マークに対応する切り欠きを設けたことを請求項記載のマスクブランクス基板の製造方法。 When clamping the four corners on one main surface of the transparent substrate, holding mechanisms partially contacting each corner were used, and at least one of these holding mechanisms was provided with a notch corresponding to the mark. The method for producing a mask blank substrate according to claim 4 .
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05341501A (en) * 1992-06-10 1993-12-24 Fujitsu Ltd Photomask and production thereof
JPH0667405A (en) * 1991-07-29 1994-03-11 Sony Corp Mask for exposure
JP2000235253A (en) * 1999-02-17 2000-08-29 Toppan Printing Co Ltd Blank for photomask and photomask
JP2001203160A (en) * 2000-12-11 2001-07-27 Sony Corp Manufacturing method of semiconductor device
JP2003173019A (en) * 2001-09-28 2003-06-20 Hoya Corp Mask blank, method of removing unnecessary film and system for the same, mask blank and method of manufacturing mask
JP2003255515A (en) * 2002-02-27 2003-09-10 Shin Etsu Chem Co Ltd Photomask blank and method for reducing generation of particle in photomask blank
JP2003344989A (en) * 2002-05-29 2003-12-03 Shin Etsu Chem Co Ltd Method for producing photomask blank

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0667405A (en) * 1991-07-29 1994-03-11 Sony Corp Mask for exposure
JPH05341501A (en) * 1992-06-10 1993-12-24 Fujitsu Ltd Photomask and production thereof
JP2000235253A (en) * 1999-02-17 2000-08-29 Toppan Printing Co Ltd Blank for photomask and photomask
JP2001203160A (en) * 2000-12-11 2001-07-27 Sony Corp Manufacturing method of semiconductor device
JP2003173019A (en) * 2001-09-28 2003-06-20 Hoya Corp Mask blank, method of removing unnecessary film and system for the same, mask blank and method of manufacturing mask
JP2003255515A (en) * 2002-02-27 2003-09-10 Shin Etsu Chem Co Ltd Photomask blank and method for reducing generation of particle in photomask blank
JP2003344989A (en) * 2002-05-29 2003-12-03 Shin Etsu Chem Co Ltd Method for producing photomask blank

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