JP4668301B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion apparatus using a semiconductor module including a pair of semiconductor switching elements on a positive electrode side and a negative electrode side connected in series.

  Power conversion devices using high-speed semiconductor switching elements such as insulated gate bipolar transistors (IGBTs) are used in various fields. In recent years, a semiconductor module having a large capacity has been realized by the advancement of semiconductor technology, and a pair of semiconductor switching elements on the positive electrode side and the negative electrode side constituting the upper and lower arms, which is one phase of an inverter for driving a variable frequency and variable voltage load. Integrated semiconductor modules are also widely used.

  Furthermore, in order to increase the capacity, a plurality of semiconductor modules may be connected in parallel. In this case, equalization of current sharing among the semiconductor modules becomes an issue. For example, as described in Non-Patent Document 1 and the like, factors that cause current sharing during switching transients to be uneven include differences in switching element characteristics, differences in main circuit wiring inductance, temperature differences, and gate drive circuit The difference is known.

  As a configuration for equalizing the current sharing due to the difference in the gate drive circuit, as illustrated in Patent Documents 1 and 2, for example, so that individual differences of components (for example, photocouplers and transistors) are not affected, A configuration in which one drive circuit is connected to a control terminal of a parallel switching element via a resistor is common.

  It is also important to equalize the gate wiring inductance from the gate drive circuit to the gate terminal of the switching element. In Patent Document 1, attention is paid to the gate wiring mounting, and each semiconductor module is placed near the semiconductor module. A circuit board on which a gate resistor connected to the gate terminal is mounted is disposed.

  Further, in Patent Document 3, it is considered that the gate circuit is not affected by the change in the magnetic field due to the change in the main current.

  Further, in Patent Document 4, by adding a common mode coil to each of gate circuits connected in parallel, current sharing due to the influence of a magnetic field change due to a change in main current is suppressed.

  Furthermore, in patent document 7, the nonuniformity is suppressed by connecting between the gates connected in parallel with a resistor having a relatively low resistance value.

JP 2003-18860 A JP 2003-88098 A JP-A-7-170723 JP-A-8-19246 JP 2003-197858 A JP 2007-151286 A JP-A-10-201243 JP 2004-135444 A CQ Publisher, Transistor Technology Special No.85 “Revised * Introduction to Practical Power Electronics”, p.85

  However, since the above-described conventional technology does not necessarily correspond to the miniaturization of the semiconductor module due to the recent advancement of the semiconductor technology, there is a concern that the power conversion device as a whole cannot be miniaturized even if the semiconductor module is miniaturized. .

  The problem to be solved by the present invention is to provide a semiconductor module mounting structure suitable for miniaturization of a power converter.

  In order to solve the above-described problems, a first aspect of the present invention is configured by connecting first and second semiconductor modules having the same configuration in parallel to each other, and the semiconductor module includes a positive electrode side and a negative electrode connected in series. A pair of semiconductor switching elements on the side, a positive terminal and a negative terminal provided at an edge of each semiconductor module and connected to the pair of semiconductor switching elements, and an opposing edge different from the positive terminal and the negative terminal A power conversion device is provided that includes a positive electrode control terminal and a negative electrode control terminal that are provided and respectively control the pair of semiconductor switching elements. In particular, a control circuit board on which a control circuit for controlling each switching element of the first and second semiconductor modules is mounted is disposed in the projection area of one semiconductor module.

  As described above, since the control circuit boards are combined into one for two semiconductor modules and arranged in the projection area of one semiconductor module, other components of the power conversion device are arranged in the projection area of the other semiconductor module. Therefore, it is possible to increase the degree of freedom of design related to the downsized mounting structure of the power conversion device.

  In this case, a switching signal (for example, a gate signal) to be supplied to a control terminal (for example, a gate) of the semiconductor switching elements connected in parallel is generated by one driving circuit to eliminate the difference, and the parallel semiconductor switching is performed from the driving circuit. The part of the gate resistance circuit supplied to each gate of the element can be mounted on the control circuit board as a control circuit.

  In the first aspect, the control circuit includes a positive electrode control circuit that controls a switching element on a positive electrode side of the first and second semiconductor modules, and a switching on a negative electrode side of the first and second semiconductor modules. It is mounted on the control circuit board separately from a negative electrode control circuit for controlling elements, the positive electrode control circuit is on the negative electrode control terminal side of the semiconductor module on which the control circuit board is disposed, and the negative electrode control circuit is It can be set as the structure formed by arrange | positioning to the positive electrode control terminal side of the semiconductor module with which the control circuit board is arrange | positioned.

  In this case, by arranging the two semiconductor modules so that the edge portions of the semiconductor modules having the positive electrode terminal and the negative electrode terminal are close to each other, the positive electrode conductor connected to the positive electrode terminal or the negative electrode conductor connected to the negative electrode terminal is simplified. It is preferable because In that case, the positive electrode control terminal of the first semiconductor module and the positive electrode control terminal of the second semiconductor module are not the same edge portion. Similarly, the negative electrode control terminal of the first semiconductor module and the negative electrode control terminal of the second semiconductor module are not edge portions on the same side. Therefore, by arranging the control output terminal of the gate resistor circuit supplied to each gate of the semiconductor switching element so as to be located on the semiconductor module side far from the control circuit board, the gate wiring length can be shortened, and the near semiconductor module The difference from the gate wiring length can be reduced.

  In order to solve the above-described problem, a second aspect of the present invention includes a pair of semiconductor switching elements connected in series on the positive electrode side and the negative electrode side, and a positive electrode terminal and a negative electrode terminal connected to the pair of semiconductor switching elements. And a power conversion device comprising a semiconductor module having a positive electrode control terminal and a negative electrode control terminal that are provided at opposite edges different from the positive electrode terminal and the negative electrode terminal and respectively control the pair of semiconductor switching elements, that is, A power conversion device including semiconductor modules that are not connected in parallel is an object. In particular, a control circuit board on which a control circuit for controlling each switching element of the semiconductor module is mounted is disposed in the projection area of the semiconductor module.

  Also in the second aspect, since the control circuit board is arranged in the projection area of the semiconductor module, the degree of freedom in design related to the downsized mounting structure of the power conversion device can be increased.

  In the power conversion device according to the first or second aspect described above, the control circuit board is disposed in a projected area of the semiconductor module at a position affected by electromagnetic induction noise due to an internal current of the semiconductor module, and the control The circuit can be configured to reduce the area of the loop circuit where the magnetic flux related to the electromagnetic induction noise is linked. According to this, even if the control circuit board is arranged close to the semiconductor module, the influence of electromagnetic induction noise due to the internal current can be reduced. Therefore, even if the control circuit board is within the projection area of the semiconductor module, it is not necessary to dispose the control circuit board away from the semiconductor module, so that the degree of design freedom can be further improved. For example, if two semiconductor modules are connected in parallel and a smoothing capacitor is placed in the projection area of one semiconductor module, the snubber circuit for each semiconductor module can be omitted, so the control circuit board is placed close to the other semiconductor module. Can be arranged. Thereby, size reduction of a power converter device can be achieved further.

  In this case, in addition to this, or alone, the control circuit arranges the direction of the loop circuit where the magnetic flux related to the electromagnetic induction noise is linked so that the control circuit does not malfunction due to the change of the magnetic flux. be able to. According to this, even if the control circuit board is arranged close to the semiconductor module, the influence of electromagnetic induction noise due to the internal current can be reduced. Furthermore, in addition to these, the control circuit may be configured such that the direction of the loop circuit where the magnetic flux related to the electromagnetic induction noise is linked is such that the control circuit does not malfunction due to a change in the residual magnetic flux. it can.

  Further, in the first aspect, the first portion in which the positive electrode conductor and the negative electrode conductor respectively connected to the positive electrode terminal and the negative electrode terminal of the first and second semiconductor modules are disposed in close proximity to each other; A positive electrode conductor and a second portion where the negative electrode conductor is not disposed in close proximity to each other are formed, and the control circuit board reaches a control terminal of the other semiconductor module in a region near the first portion. It can be set as the structure which lets wiring pass. According to this, since the influence of the magnetic field formed by the main circuit current flowing in the positive electrode conductor and the negative electrode conductor is small in the vicinity of the first portion in which the positive electrode conductor and the negative electrode conductor are disposed in close proximity to each other, control is performed. Electromagnetic noise received by the wiring from the circuit board to the control terminal of another semiconductor module can be reduced.

  Furthermore, in the first aspect, the control circuit includes two positive control circuits that control switching elements on the positive side of the first and second semiconductor modules, and the negative side of the first and second semiconductor modules. The two negative electrode control circuits for controlling the switching elements are mounted on the control circuit board, and the wiring patterns of the two positive electrode control circuits and the two negative electrode control circuits can be the same. According to this, even when the two semiconductor modules are not connected in parallel, the control circuit board can be shared, so that the types of components can be reduced.

  Furthermore, in the first aspect, the control circuit includes two positive control circuits that control switching elements on the positive side of the first and second semiconductor modules, and the negative side of the first and second semiconductor modules. Are mounted on the control circuit board, and the two positive electrode control circuits and the two negative electrode control circuits are respectively connected between the control terminals of the corresponding semiconductor switching elements. And a circuit related to the gate sensitivity correction resistor has a configuration in which the area of a loop circuit where magnetic flux related to electromagnetic induction noise due to the internal current of the semiconductor module is linked is reduced. it can. According to this, a gate sensitivity correction resistor generally provided in the vicinity of the positive control terminal or negative control terminal on the semiconductor module side can be provided on the control circuit board.

  ADVANTAGE OF THE INVENTION According to this invention, the mounting structure of the semiconductor module suitable for size reduction of a power converter device can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a perspective configuration diagram of a power converter according to a first embodiment of the present invention, FIG. 2 is a top view thereof, and FIG. 3 is a side view thereof. The present embodiment is a mounting configuration in which two semiconductor modules 11 and 12 having substantially the same shape are connected in parallel. The basic configuration is the same as that described in Patent Document 5.

  This embodiment can be applied to the general three-phase inverter circuit shown in FIG. Here, an example in which an insulated gate bipolar transistor IGBT is applied will be described as an example of the semiconductor switching element. In FIG. 4, a load 7 is driven via a three-phase inverter circuit from a DC power source or a smoothing capacitor (not shown). A pair of semiconductor switching elements (for example, UP and UN in the figure) connected in series, which constitute one phase, alternately turn on and off alternately, so that AC power of an arbitrary frequency and voltage can be obtained. Supply to load 7. When the required power is large, a structure in which a plurality of semiconductor switching elements are arranged in parallel for one phase may be used.

  FIG. 5 shows a circuit configuration for one phase in which two switching elements are connected in parallel. Here, one semiconductor module 11 is constituted by a pair of semiconductor switching elements 111 and 112, and one semiconductor module 12 is similarly constituted by switching elements 121 and 122. That is, the semiconductor modules 11 and 12 are respectively called so-called 2 in 1 modules.

  The semiconductor module 11 has a positive terminal 11P through which a main current flows, a negative terminal 11N, an AC terminal 110, a control terminal 11GP for inputting a control signal for turning on / off the positive semiconductor switching element 111, and a negative semiconductor. There is a control terminal 11GN for the switching element 112. Similarly, the semiconductor module 12 includes a positive terminal 12P, a negative terminal 12N, an AC terminal 120 through which a main current flows, a control terminal 12GP for the semiconductor switching element 121 on the positive side, and a control terminal 12GN for the semiconductor switching element 122 on the negative side. There is. For example, the semiconductor switching element 111 is controlled by applying a gate signal between the gate terminal 11GP1 of the control terminal 11GP and the control emitter terminal 11GP2.

  The semiconductor modules 11 and 12 of the present embodiment have the same shape and structure and are formed in a flat rectangular parallelepiped shape. The positive terminals 11P and 12P of the main current and the negative terminals 11N and 12N are provided on the upper surfaces of the long edges of the semiconductor modules 11 and 12, respectively, and the AC terminal 110 is provided on the upper surfaces of the long edges facing the main modules. ing. In addition, control terminals 11GP and 12GP, and 11GN and 12GN are provided on the upper surfaces of the edges of the two opposing short sides of the semiconductor modules 11 and 12, respectively.

  The positive terminals 11P and 12P and the negative terminals 11N and 12N of the two semiconductor modules 11 and 12 are connected in parallel by a positive conductor and a negative conductor having terminals 42, 43, 411, and 412 shown in FIG. The positive electrode conductor has a bent terminal connected to the positive electrode terminal 11P, a conductor bar extending along opposite long side edges of the semiconductor modules 11 and 12, and a bent terminal connected to the positive electrode terminal 12P. Two conductor bars extending along the edge of the long side of the semiconductor module 12 are provided. On the other hand, the negative electrode conductor has bent terminals connected to the negative electrode terminals 11N and 12N, respectively, and is formed with a conductor bar extending along edges of opposing long sides of the semiconductor modules 11 and 12. ing. These conductor bars are arranged in a stacked manner at intervals, and are used for connection to the parallel semiconductor module of the other phase of the three-phase inverter.

  These connection conductors are formed in a shape similar to that described in Patent Document 6. That is, the negative conductor connected to the negative terminals 11N and 12N is connected to the DC power source (not shown) or the negative terminal of the smoothing capacitor (N in FIG. 5) via the terminals 411 and 412. The positive conductor connected to the positive terminal 11P of the semiconductor module 11 is connected to the DC power supply or the positive terminal of the smoothing capacitor (P in FIG. 5) via the terminal 43. The positive conductor connected to the positive terminal 12P of the semiconductor module 12 is connected to the DC power supply or the positive electrode of the smoothing capacitor (P in FIG. 5) via the terminal 42.

  The switching element in the semiconductor module is driven from a gate drive circuit (not shown) through a gate resistor, a gate circuit output terminal, and a gate wiring mounted on the gate resistor circuit board 2. That is, a drive signal is input from the gate drive circuit to the gate resistor circuit substrate 2 through the common gate wirings 31P and 31N and the gate resistor circuit input terminals 21P and 21N.

  As shown in FIG. 6, from the positive input terminal 21P of the gate resistor circuit board 2 to the positive output terminals 22P1, 22P2 through the individual gate resistors 243, 244, and further through the gate wirings 32P1, 32P2, the semiconductor module 11, A gate drive signal is applied to the 12 positive-side gate terminals 11GP and 12GP.

  The same applies to the negative electrode side. From the negative electrode side input terminal 21N of the gate resistor circuit board 2 to the negative electrode side output terminals 22N1, 22N2 through the individual gate resistors 241, 242, and further via the gate wirings 32N1, 32N2, the semiconductor module 11 , 12 are applied with a gate drive signal to the negative side gate terminals 11GN, 12GN.

  In FIG. 1, the gate terminal (for example, 11GP) is simplified, but actually, as shown in FIG. 5, the gate terminal (for example, 11GP1) and the control emitter terminal (for example, 11GP2) form one set. Similarly, two gate wirings (for example, 32P1) are required and are often used in a twisted state. In FIG. 2, the twisted portion is displayed with a single thick line for the sake of simplicity. A twisted wire with a shield may be used to suppress malfunction due to noise, and in that case, the appearance is exactly as shown in FIG.

  In FIG. 2, the positive side gate terminal 12GP of the semiconductor module 12 covered by the gate resistance circuit board 2 is on the left side in the figure, and the negative side gate terminal 12GN is on the right side in the figure. On the other hand, the positive-side gate terminal 11GP of the semiconductor module 11 not covered with the gate resistor circuit board 2 is on the right side in the figure, and the negative-side gate terminal 11GN is on the left side in the figure.

  Therefore, the gate circuit output terminals 22P1 and 22P2 to which the gate wirings 32P1 and 32P2 connected to the gate terminals 11GP and 12GP of the positive side switching element and the gate resistance circuit board 2 are connected are on the right side of the gate resistance circuit board 2 and the negative electrode Gate circuit output terminals 22N1, 22N2 to which the gate wirings 32N1, 32N2 connected to the gate terminals 11GN, 12GN of the side switching element and the gate resistance circuit board 2 are connected are arranged on the left side of the gate resistance circuit board 2. By arranging in this way, the gate wirings 32P1 and 32N1 to the gate terminals 11GP and 11GN far from the gate resistor circuit board 2 and the gate terminals 12GP and 12GN immediately covered by the gate resistor circuit board 2 are covered. It is easy to make the gate wirings 32P2 and 32N2 uniform in length.

  If the positive side gate circuit output terminals 22P1 and 22P2 are on the left side and the negative side gate circuit output terminals 22N1 and 22N2 are on the right side, the distance from the gate circuit output terminal to the gate terminal is extremely different. It is difficult to make it long. This is because the wiring on the side closer to the uniform length has a surplus in length, and there is a concern that noise will be received at that portion.

  FIG. 3 is a view of the two semiconductor modules 11 and 12 when viewed from the right side. The semiconductor modules 11 and 12 are attached to the radiator 6 or the like. The portions surrounded by the two-dot chain line in FIG. 3 are the snubber circuits 51 and 52. In FIG. 1 and FIG. 2, the description is omitted to make it easy to see each terminal of the semiconductor module. Note that the snubber circuits 51 and 52 play a role of suppressing a jump voltage at the time of switching transient of the semiconductor switching element, and the simplest one is a capacitor connected thereto. In addition, there is a configuration including a series body of a capacitor and a diode and a resistor for discharging the capacitor.

  A broken line portion 20P in FIG. 3 is a part portion of the gate resistance circuit, and an example of the circuit configuration is shown in FIG. In FIG. 6, the upper part shows the circuit of FIG. 5 in an arrangement close to the mounting structure of FIG. The lower part shows a configuration example of the gate resistance circuit board 2. From the gate drive circuit board 29 at the bottom of the figure, a positive control signal is sent to the input terminals 21P1, 21P2 of the gate resistor circuit board 2 via the gate wiring 31P, and a negative control signal is sent via the gate wiring 31N. This is transmitted to the input terminals 21N1 and 21N2 of the gate resistance circuit board 2. The input terminal 21P1 branches to output terminals 22P11 and 22P21 through individual gate resistors 243 and 244, respectively. The input terminal 21P2 branches to output terminals 22P12 and 22P22.

  Here, in order to prevent the gate circuit from being affected by external noise, a loop circuit including an input terminal 21P1 to an output terminal 22P11, an output terminal 22P12 to an input terminal 21P2, and an input, as in an embodiment described later. The loop area constituted by the terminal 21P1 to the output terminal 22P21 and the output terminal 22P22 to the input terminal 21P2 has a structure in which the loop area is reduced as much as possible. Between the output terminals 22P11 and 22P12, a resistor 263 having a relatively high resistance value and Zener diodes 2531 and 2532 for suppressing gate overvoltage are connected. Since the circuit configuration is the same for the negative electrode sides 20N1 and 20N2, the description thereof is omitted.

  As described above, according to the present embodiment, the gate resistor circuit board 2 which is the control circuit board is combined into one for the two semiconductor modules 11 and 12 and is within the projection region of one semiconductor module 12. Since the other components of the power conversion device can be arranged in the projection region of the other semiconductor module 11 because of the arrangement, the degree of freedom of design related to the downsized mounting structure of the power conversion device can be increased. .

  In addition, since the gate signals supplied to the control terminals 11GP and 12GP and 11GN and 12GN of the two semiconductor switching elements 111 and 121, 112 and 122 connected in parallel are generated by one gate driving circuit 29, they are connected in parallel. Differences in element control timing can be eliminated.

  The gate circuit controls the positive-side gate circuits 20P1 and 20P2 that control the positive-side switching elements 111 and 121 of the semiconductor modules 11 and 12, and the negative-side switching elements 112 and 122 of the semiconductor modules 11 and 12, respectively. The gate circuits 20N1 and 20N2 on the negative electrode side are divided and mounted on the gate resistor circuit board 2, and the gate circuits 20P1 and 20P2 on the positive electrode side are arranged on the negative electrode side of the semiconductor module 2 on which the gate resistor circuit board 2 is stacked. Since the negative gate circuits 20N1 and 20N2 are arranged on the positive control terminal 12GP side of the semiconductor module in which the gate resistor circuit board 2 is placed on the control terminal 12GN side of the semiconductor module 11, , 12 substantially equalize the gate wiring length on the positive electrode side and the gate wiring length on the negative electrode side. It is possible. In particular, the positive electrode side output terminals 22P1 and 22P2 and the negative electrode side output terminals 22N1 and 22N2 of the gate resistor circuit supplied to each gate of the semiconductor switching element are arranged on the semiconductor module 11 side, so that the gate wiring length is increased. It can be made even shorter.

  The positive output terminals 22P1 and 22P2 and the negative output terminals 22N1 and 22N2 are arranged so that the positive output terminal 22P1 and the negative output terminal 22N1 of the semiconductor module 11 are outside the gate resistance circuit board 2 and the gate resistance circuit board 2 is By arranging the positive electrode side output terminal 22P2 and the negative electrode side output terminal 22N2 of the arranged semiconductor module 12 inside, it is possible to further equalize the gate wiring length.

  A second embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a perspective configuration diagram of the present embodiment, and FIG. 8 is a right side view of the present embodiment.

  This embodiment differs from the first embodiment in that the smoothing capacitor 50 is directly connected to the positive conductor terminals 42 and 43 and the negative conductor terminals 411 and 412, and the snubber circuits 51 and 52 are removed accordingly. is there. That is, since the stray inductance of the wiring can be reduced by bringing the semiconductor module and the smoothing capacitor close to each other, it is possible to remove the snubber circuit for suppressing the jump voltage at the time of switching.

  In this embodiment, since the snubber circuit 52 is eliminated, the gate resistor circuit substrate 2 is disposed close to the upper surface of the semiconductor module 12. As a result, the distance from the gate resistor circuit board 2 to the gate terminal (for example, 12GN) of the semiconductor module is reduced, and the gate wiring (for example, 32N2) can be shortened, so that it is less susceptible to noise and uses less wiring. There is an advantage that it can be done.

  In addition, the gate drive circuit 29 is arranged in a vacant space thereby further reducing the size.

  However, since the gate resistance circuit board 2 is close to the semiconductor module, it is easily affected by the current flowing through the semiconductor module. 9 and 10 schematically show the internal current of the semiconductor module and the magnetic field generated by the current. FIG. 9 is when the positive side switching element is conducting, and FIG. 10 is when the negative side switching element is conducting. FIG. 9 (a) is from the top of the module, FIG. 9 (b) is from the side, and FIG. It is the figure seen from. An outline of these magnetic fields is described in Patent Document 5.

  As shown in FIG. 9C, when the semiconductor switching element on the positive electrode side is conductive, current flows from the module internal positive conductor 120P to the output conductor 1200 via the bonding wire 1211, the semiconductor element portion 122P, and the bonding wire 1212. The magnetic field generated by this current is directed from the front to the back of the paper in the region surrounded by the bonding wires 1211 and 1212 and from the back to the front of the paper at the top of the bonding wire 1212. The outline of the magnetic force lines is shown by a solid line in FIG. 9A and 9B, the portion of the gate resistance circuit substrate 2 is directed from the top to the bottom, that is, from the output terminals 22N1 and 22N2 to the input terminal 20N.

  On the other hand, when the semiconductor switching element on the negative electrode side is conductive as shown in FIG. 10C, a current flows from the output conductor 1200 to the module internal negative electrode conductor 120N via the bonding wire 1213, the semiconductor element portion 122N, and the bonding wire 1214. The magnetic field generated by this current is directed from the back to the front of the paper in the region surrounded by the bonding wires 1213 and 1214 and from the front to the back of the paper at the top of the bonding wire 1214. The outline of the magnetic force lines is shown by a solid line in FIG. 10A and 10B, the portion of the gate resistance circuit substrate 2 is directed from the bottom to the top, that is, from the input terminal 21P to the output terminals 22P1 and 22P2.

  Since these magnetic fields fluctuate due to current changes during switching, there is a concern that they may cause noise such as electromagnetic induction noise. Therefore, the structure of the gate resistance circuit board 2 is as shown in FIGS. FIG. 11A shows the back surface wiring pattern seen through from the front side of the gate resistance circuit board 2 and FIG. 12A shows the wiring pattern on the front surface, and FIG. 12B shows the wiring pattern on the back surface. FIG. 12B is a view as seen from the back side. 11 and 12, the positive electrode side gate resistor circuit board 200P and the negative electrode side gate resistor circuit board 200N have the same component arrangement and wiring pattern. Therefore, when the gate resistance circuit board 2 is divided into left and right parts in FIGS. 11 and 12, the same circuit board is obtained. Therefore, in some cases, two identical circuit boards divided in two may be arranged.

  FIG. 13 is an arrow A-A ′ view in FIG. 11. The dotted line in the figure shows the lines of magnetic force due to the current when the semiconductor switching element on the positive electrode side inside the semiconductor module is conducted. The magnetic field passing between the front side pattern and the back side pattern of the gate resistor circuit board 2 is in the vertical direction in the figure. On the other hand, since the resistors 241 and 261 are mounted in the direction of the magnetic field, the magnetic field penetrating the loop circuit composed of the resistor, the resistance lead portion and the wiring pattern can be reduced, and the mounting is not easily affected by the magnetic field. It has become. That is, since the extending direction of the entire loop circuit composed of the resistor, the resistance lead portion, and the wiring pattern is configured in parallel to the direction of the magnetic field lines due to the current when the semiconductor switching element is conducted, the magnetic flux related to electromagnetic induction noise is reduced. The number of linkages can be reduced.

  As described above, according to the present embodiment, the gate resistor circuit board 2 can be disposed in the projection region of the semiconductor module 12 at a close position that receives electromagnetic induction noise due to the internal current of the semiconductor module 12. Since the resistors 241 and 261 are mounted in the direction of the magnetic field, the magnetic field penetrating the loop circuit composed of the resistor, the resistance lead portion, and the wiring pattern can be reduced, and mounting that is not easily affected by the magnetic field can be achieved. . That is, a circuit configuration in which the loop circuit through which the magnetic flux related to electromagnetic induction noise passes is reduced, in other words, the number of magnetic flux linkages related to electromagnetic induction noise linked to the loop circuit is reduced.

  According to this embodiment, even if the gate resistor circuit board 2 is arranged close to the semiconductor module 12, the influence of electromagnetic induction noise due to the internal current can be reduced. Therefore, even if the gate resistor circuit board 2 is within the projection region of the semiconductor module 12, it is not necessary to dispose the gate resistor circuit board 2 away from the semiconductor module 12, so that the degree of freedom in design can be further improved.

  As shown in FIG. 8, since the gate drive circuit 29 is separated from the surface of the semiconductor module 12, it is hardly affected by the magnetic field generated by the internal current of the semiconductor module 12, and there is no problem even if it is arranged here.

  Therefore, as in this embodiment, the snubber circuit can be omitted by connecting two semiconductor modules in parallel and arranging a smoothing capacitor in the projection region of one of the semiconductor modules. Therefore, the power conversion device can be further downsized.

  A third embodiment of the present invention will be described with reference to FIGS. FIG. 14 shows a circuit configuration of the gate resistance circuit board 2. Since this embodiment is different from the gate resistor circuit board 2 of FIG. 6 in that the Zener diodes (for example, 2511 and 2512) are excluded, description of other configurations is omitted. The Zener diode of this embodiment is provided on the side of the gate drive circuit substrate 29 before branching of the gate resistor circuit that is branched corresponding to each semiconductor switch. This is the same as in the case of Patent Document 2.

  15 and 16 show a mounting configuration and a wiring pattern of the gate resistor circuit board 2. Here, the resistors 241 to 244 and 261 to 264 are mounted extending in the horizontal direction in the drawing. Further, the configuration is symmetrical with respect to the center line C-C '. When the gate resistor circuit board 2 is installed in the same manner as in FIG. 7, the magnetic field due to the internal current of the semiconductor module 12 becomes the same as in FIGS.

  In the case of this embodiment, the state of the magnetic field received by the resistor 261 is shown in FIG. 17, and the state of the magnetic field received by the resistor 263 is shown in FIG. Since the semiconductor switching element on the positive electrode side is turned on, the magnetic field due to the internal current of the semiconductor module is oriented as shown in FIG. 9, and the magnetic field in the direction shown by the arrow in FIG. 17 is increased. In FIG. 17, one lead of the resistor 261 is connected to the surface pattern 271 at a connection point (through hole or the like) 2712 and connected to the connection point 2711 via the wiring pattern 271. The other is connected to the back surface pattern 281 at the connection point 2812 and connected to the connection point 2811 through the wiring pattern 281. At this time, due to the magnetic field change due to the internal current of the semiconductor module, the loop composed of the resistor 261 and its lead and wiring pattern can be regarded as a one-turn coil and induced in a direction in which the terminal 2711 is negative and the terminal 2811 is positive as shown. Voltage is generated. The terminal 2711 is connected to the gate terminal 11GN1 of the negative semiconductor switching element via the output terminal 22N1, and the terminal 2811 is connected to the control emitter terminal 11GN2 of the negative switching element via the output terminal 22N1. For this reason, it acts in the direction to turn off the semiconductor switching element (112 in FIG. 5) on the negative electrode side, that is, the direction to suppress malfunction. Although not shown, the same applies to the other semiconductor switching element on the negative electrode side.

  In addition, when the semiconductor switching element on the positive electrode side is turned off, the magnetic field in the direction indicated by the arrow in FIG. 17 is reduced, and an induced voltage is generated with a polarity opposite to the sign shown in the figure. There is no problem because it does not affect the turn-off.

  On the other hand, when the semiconductor switching element on the negative electrode side is turned on, the magnetic field due to the internal current of the semiconductor module is oriented as shown in FIG. 10, and the magnetic field in the direction shown by the arrow in FIG. 18 increases. Due to the change in the magnetic field, a loop composed of the resistor 263 and its lead and wiring pattern can be regarded as a one-turn coil, and an induced voltage is generated in a direction in which the terminal 2821 is positive and the terminal 2731 is negative as shown in the figure. The terminal 2731 is connected to the gate terminal 11GP1 of the positive semiconductor switching element via the output terminal 22P1, and the terminal 2821 is connected to the control emitter terminal 11GP2 of the positive semiconductor switching element via the output terminal 22P1. Therefore, it acts in a direction to turn off the semiconductor switching element on the positive electrode side (111 in FIG. 5), that is, in a direction to suppress malfunction. Although not shown, the same applies to the other positive-side semiconductor switching element.

  Further, when the semiconductor switching element on the negative electrode side is turned off, the magnetic field in the direction indicated by the arrow in FIG. 18 is reduced, and an induced voltage is generated in the opposite polarity to the illustrated sign. There is no problem because it does not affect.

  As described above, according to the third embodiment, the extending direction of the loop circuit composed of the resistance of the gate resistor circuit board 2, the lead wire, and the wiring pattern is orthogonal to the direction of the magnetic field generated by the semiconductor module internal current. However, since the direction of the current induced in the resistance circuit due to the change of magnetic flux related to electromagnetic induction noise is the direction that does not cause the gate resistance circuit to malfunction, the gate resistance circuit board 2 is arranged close to the semiconductor module. Even so, the influence of electromagnetic induction noise due to the internal current can be reduced.

  A fourth embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 19, the present embodiment shows a mounting example in which each switching element portion of the three-phase inverter shown in FIG. 4 has a two-parallel connection configuration.

  The semiconductor modules 11U and 12U constitute a U phase in parallel, 11V and 12V constitute a V phase, and 11W and 12W constitute a W phase in parallel. In the figure, the positive conductors connecting the positive terminals 12UP, 12VP, and 12WP of the semiconductor modules 12U, 12V, and 12W on the near side, the negative terminals of the semiconductor modules 11U to 12W (shown in the figure are 12UN, 12VN, and 12WN ) And the back side positive conductor connecting the positive terminals (not shown because they are hidden in the figure) of the semiconductor modules 11U, 11V, and 11W on the opposite side straddle long horizontally.

  Of these, the V-phase portion is enlarged and shown in FIG. Although it is almost the same as the mounting of the first embodiment of FIG. 1, since the negative electrode conductor and the two positive electrode conductors are horizontally long as described above, from the gate resistance circuit board 2 to the control terminals 11GPV and 11GNV on the back side. The gate wiring passes through a space formed by the positive terminal 12PV and the negative terminal 12NV of the semiconductor module 12V on the front side. The reason why the gate wiring is passed through this space will be described with reference to FIGS.

  First, FIG. 21 shows an operating current for one phase connected in parallel. At the beginning, the upper switching elements 111 and 121 are turned off, and the upper switching elements 111 and 121 are switched from the state in which current flows through the freewheeling diodes on the lower sides 112 and 122 as indicated by a two-dot chain line in the drawing. Will be described in a state where the turn-on turns into a solid flow path in the figure.

  At first, current flows from the negative electrode terminals 411 and 412 to the negative terminals 11N and 12N, and the positive-side semiconductor switching element is turned on, so that the path of the solid line, that is, the connection terminal 43 of one positive conductor is one side. The positive electrode terminal 11P changes so that a current flows from the terminal 42 of the other positive electrode conductor to the positive electrode terminal 12P.

  Current paths on mounting at this time are shown in FIGS. FIG. 23 is an exploded view of three stacked conductors. In both figures, (1) the negative side reflux is a two-dot chain line path in FIG. 21, and (2) the positive side conduction is a solid line path in FIG.

  FIG. 24 shows the change of the magnetic field due to the current at this time. (1) At the time of negative side circulation, since current flows downward from the terminals 411 and 412 of the negative conductor in the figure, in the area A and area C in the figure, the magnetic field from the back to the front of the paper is dominant. On the other hand, in the region B, the magnetic field from the front of the page to the back is dominant. Further, a downward current indicated by a dotted line flows to the negative electrode terminal 11N of the semiconductor module 11 on the back side, and a downward current also flows to the negative electrode terminal 12N of the semiconductor module 12 on the near side. If both currents connected in parallel are substantially equal, in the region D, the magnetic field in the direction perpendicular to the paper surface is substantially zero.

  Next, (2) at the time of positive-side conduction, current flows from the terminals 42 and 43 of the positive conductor, so that the magnetic field from the front to the back of the paper is dominant in the region A and the region C, and the back of the paper in the region B. The magnetic field from the front to the front is dominant. For this reason, in the region A, the region B, and the region C, the magnetic field changes greatly during switching. If the gate wiring passes through this part, it may be affected by the magnetic field. The gate wiring is generally less susceptible to changes in the external magnetic field, such as twisted, but it may not be completely affected by the roughness of the twist, etc. Larger locations are preferably avoided as wiring paths.

  On the other hand, since there is almost no change in the region D even when (2) it is on the positive side, this region is used as a gate wiring path in this embodiment. Note that the magnetic field is not zero in the regions E and F on both sides of the region D, but not in the region D, but the direction of the magnetic field does not change greatly by switching, so this portion may be used as a gate wiring path, and the gate wiring 32P1 in FIG. In the region F, the gate wiring 32N1 passes through the region E.

  In other words, according to the present embodiment, when the three-phase inverter circuit is configured by two parallel semiconductor modules per phase, the gate resistor circuit board 2 disposed on one semiconductor module 12 is superposed on the other semiconductor module. Since the gate wiring connected to the 11 control terminals 11GP and 11GN passes through the gap (area D) formed by the positive terminals 11P and 12P and the negative terminals 11N and 12N of the two parallel semiconductor modules 11 and 12, the main circuit Wiring can be performed without being affected by the magnetic field due to the current flowing in the circuit.

  That is, when a three-phase inverter is configured as in this embodiment, the power conversion device is configured by arranging two or two semiconductor modules connected in parallel. In these cases, a plate-like positive electrode conductor and a negative electrode conductor that commonly connect the positive electrode terminal and the negative electrode terminal of each semiconductor module are required. In this case, as shown in FIG. 23 and the like, two common positive electrode conductors are arranged at intervals with a common negative electrode conductor interposed therebetween, and are arranged across a plurality of semiconductor modules in which the common conductors are arranged. It will be. In this case, the terminals 42, 43, 411, 412 connected to the DC power supply are formed so as to protrude from the common positive electrode conductor and negative electrode conductor which are arranged in an overlapping manner.

  Therefore, the positive electrode conductor and the negative electrode conductor are the first part in which the positive electrode conductor and the negative electrode conductor respectively connected to 11P and 12P of the semiconductor modules 11 and 12 and the negative electrode terminals 11N and 12N are disposed in close proximity to each other. A second portion (a conductor portion defining the regions A, B, and C) that is not disposed in close proximity to each other is formed. In this case, it is preferable to pass the gate wirings 32P1 and 32N1 extending from the control circuit board 2 to the control terminals 11GP and 11GN of the semiconductor module 11 through the regions E, D and F in the vicinity of the first portion. Thereby, the gate wiring can be made without being affected by the magnetic field due to the current flowing in the main circuit.

  A fifth embodiment of the present invention will be described with reference to FIGS.

  FIG. 25 is an example in which gate sensitivity correction resistors 240P and 240N are connected between gate terminals connected in parallel in a gate resistance circuit, and this point is known as described in Patent Document 7. Here, the gate sensitivity correction resistor is preferably connected between the gate terminals of the semiconductor module. However, in this embodiment, it is decided to mount the gate sensitivity correction resistor on the gate resistor circuit board 2 because of the problem of the location where the resistor is mounted.

  The mounting of the gate resistor circuit board 2 at this time is shown in FIG. 26, the circuit wiring pattern is shown in FIG. 27, and the side surface in FIG. 26 is shown in FIG. As an overall implementation, consider the same case as shown in FIG.

  The gate sensitivity correction resistors 240P and 240N are mounted in the vertical direction in FIGS. 26 and 28, that is, the direction (cross section) of the resistance loop circuit is the same as described in the second embodiment of FIG. Since it is arranged in parallel with the direction of the magnetic field due to the circuit current, it is difficult to be affected by the magnetic field shown in FIG. Therefore, there is no influence between the gate terminals connected in parallel. 26 and 27, the gate sensitivity correction resistor 240P is placed beside the gate resistor 244. However, the gate sensitivity correction resistor 240P may be placed beside the gate resistor 243 to have a wiring pattern corresponding thereto. 240N may be a wiring pattern corresponding to the gate resistor 242 instead of the gate resistor 241.

  According to the present embodiment, the gate sensitivity correction resistors 240P and 240N can be mounted on the gate resistance circuit board 2, and the direction of the loop circuit of these resistors is arranged in parallel to the direction of the magnetic field by the main circuit current. Therefore, it is possible to realize a mounting structure that is not affected by electromagnetic noise due to the main circuit current.

  A sixth embodiment of the present invention will be described with reference to FIGS.

  FIG. 29 shows a circuit configuration when power is supplied from the AC power supply 8 via the PWM rectifier circuit, and is generally used for power factor improvement or power regeneration. Although only the AC power supply 8 is shown in FIG. 29, a filter or a boost reactor may be connected to the subsequent stage of the power supply. Here, each phase of the PWM rectifier circuit is composed of one semiconductor module 1R, 1S, 1T, and is not connected in parallel. Similarly, the inverter connected to the load 7 is not connected in parallel but is constituted by three semiconductor modules 1U, 1V, and 1W. Each semiconductor module is connected to the control terminal from the gate resistor circuit boards 2R, 2S, 2T, 2U, 2V and 2W.

  FIG. 30 shows a mounting example of this embodiment. Each gate resistor circuit board (for example, 2U) is mounted so as to cover each semiconductor module (for example, 1U), and is connected to the control terminal (for example, 1UGP) from its output terminal (for example, 22PU) through a gate wiring. . As a feature at this time, the output terminal 22N1 connected to the negative control terminal 11GN of the semiconductor module 11 which is not the semiconductor module 12 covered in FIG. 1 is replaced with the semiconductor module 1U covered in the case of FIG. The gate wiring length can be shortened by using it as the output terminal 22PU connected to the positive control terminal 1UGP.

  From the viewpoint of maintenance management, it is not a good idea to prepare the gate resistance circuit board 2 for the semiconductor modules of the same shape separately in two types for parallel connection and non-parallel connection. In addition, what needs to be connected in parallel is for a very high power, so its application is limited. Therefore, it is considered that by unifying to one type of gate resistance circuit board, the types of maintenance management parts are reduced, and the response at the time of failure becomes quick, so that it is possible to minimize the degradation of service.

  Since the positive circuit board 200P and the negative circuit board 200N have the same structure in the gate resistor circuit board shown in FIGS. 11 and 12, the positive and negative circuits may be used in reverse. In this way, by setting the positive side circuit and the negative side circuit to the same structure, it can be used even when they are not connected in parallel as shown in FIGS. 29 to 30, and the types of maintenance management parts can be reduced. Become.

  FIG. 31 shows only the components necessary for the same circuit pattern shown in FIG. 11 and FIG. In FIG. 11 and FIG. 12, the right side of the figure is the positive circuit board 200P and the left side is the negative circuit board 200N, so that the gate wiring length can be equalized. However, in FIG. 31, the positive circuit on the left side and the negative circuit on the right side make it possible to shorten the wiring with the control terminal of the semiconductor module as shown in FIG.

  In FIG. 31, only the necessary parts are mounted using the same wiring pattern as that of FIG. 12 as the gate resistor circuit board 2U. If it is certain that the object to be used is not diverted when connected in parallel, unnecessary parts can be removed.

  In FIG. 31, since the resistors 241 and 261 are mounted in the vertical direction in the drawing, it is not affected by the change of the magnetic field due to the internal current of the semiconductor module.

  A seventh embodiment of the present invention will be described with reference to FIGS.

  The present embodiment of FIG. 32 differs in the configuration of the connection conductors of the main circuit of the first and fourth embodiments. In this embodiment, the conductor of the main circuit wiring that connects the semiconductor modules 11 and 12 in parallel is provided in parallel with the terminal surfaces of the positive terminals 11P and 12P and the negative terminals 11N and 12N of the semiconductor modules 11 and 12. Therefore, the distance between the two semiconductor modules 11 and 12 is increased, and the distance from the output terminal 22P1 of the gate resistor circuit board 2 to the control terminal 11GP, as well as the distance from the output terminal 22N1 to the control terminal 11GN is further increased. . Such a mounting structure is similar to the structure described in Patent Document 8.

  FIG. 33 shows the mounting structure of the gate resistor circuit board 2 of this embodiment. In the present embodiment, the negative side input terminal 21N is closer to the left side in the figure than in FIG. 11, and the current path to the output terminal 22N1 is shorter than the current path to the other output terminal 22N2. Similarly, the positive input terminal 21P is shifted to the right side of the drawing, and the current path to the output terminal 22P1 is shorter than the current path to the other output terminal 22P2.

  That is, since the difference in distance between the gate wirings 32P1 and 32P2 from the output terminal to the control terminal is large, the gate wiring 32P2 on the near side is considerably left when the wiring lengths are made uniform. If the magnetic field is linked to the remaining portion, it may cause a malfunction or the like, which is not preferable. Therefore, in this embodiment, the difference between the parallel wirings is reduced by making a difference in the wiring path inside the gate resistance circuit board 2 and reducing the difference in the length of the gate wiring.

  An eighth embodiment of the present invention is shown in FIGS. In this embodiment, the two parallel connection configurations shown in FIG. 1 are further arranged side by side to form a total of four parallel connection configurations. Gate wiring is connected to the semiconductor modules 11 and 12 from the gate resistance circuit board 2A, and gate wiring is connected to the semiconductor modules 13 and 14 from the other gate resistance circuit board 2B.

  For the four parallel-connected semiconductor modules 11, 12, 13, and 14, the common gate drive circuit branches from the wiring 31P to the gate wirings 31P1 and 31P2 via the branch point 31P0, and the gate resistance circuit substrates 2A and 2B are positively connected. Connect to side input terminals 2A1P and 2B1P. Similarly, the wiring 31N branches to the gate wirings 31N1 and 31N2 via the branch point 31N0, and is connected to the negative side input terminals 2A1N and 2B1N of the gate resistance circuit boards 2A and 2B. The branch points 31P0 and 31N0 connect three sets of wirings by caulking connection or soldering connection.

  The gate wiring from the two gate resistance circuit boards 2A and 2B to the two semiconductor modules 11, 12, 13 and 14 is the same as in FIG.

  Thus, by providing a plurality of sets based on the structure of two parallel connections, it is possible to increase the converter capacity by increasing the number of parallels to 2, 4, 6 parallel. When the number of parallel increases, the number of wiring branches at the branch point 31P0 increases. Therefore, a plurality of sets of wirings can be directly connected from the output terminal of the gate driving circuit (not shown), or a plurality of output terminals of the gate driving circuit can be connected. A set can also be provided.

  As described above, the present invention has been described based on the first to eighth embodiments. According to the present invention, it is possible to suppress current sharing unevenness during parallel connection while reducing the size of the power conversion device. .

  In addition, this invention is not limited to those Examples, For example, as a semiconductor switching element, it cannot be overemphasized that it is applicable not only to IGBT but another known switching element.

It is a perspective view which shows the structure of Example 1 of the power converter device of this invention. 3 is a top view of Example 1. FIG. 1 is a side view of Example 1. FIG. It is a block diagram of the circuit of the three-phase inverter to which Example 1 is applied. 1 is a diagram illustrating a main circuit configuration of Example 1. FIG. FIG. 3 is a diagram illustrating a detailed configuration of a gate circuit according to the first embodiment. It is a perspective view which shows the structure of Example 2 of the power converter device of this invention. 6 is a side view of Example 2. FIG. FIG. 6 is a schematic diagram illustrating a magnetic field due to a main circuit current of Example 2. FIG. 6 is a schematic diagram illustrating a magnetic field due to a main circuit current of Example 2. It is a figure which shows the mounting structure of the gate resistance circuit in Example 1 or 2. FIG. 6 is a diagram illustrating a wiring pattern of a gate resistance circuit in Example 1 or 2. FIG. FIG. 12 is an arrow view of the gate resistance circuit board as viewed from line A-A ′ in FIG. 11. FIG. 10 is a diagram illustrating a configuration of a gate resistance circuit in Example 3. FIG. 10 is a diagram illustrating a mounting configuration of a gate resistance circuit in Example 3. It is a figure which shows the wiring pattern of the gate resistance circuit in Example 3. FIG. It is a figure explaining the electromagnetic induction noise reduction effect by Example 3. FIG. It is a figure explaining the electromagnetic induction noise reduction effect by Example 3. FIG. It is a perspective view which shows the structure of Example 4 of the power converter device of this invention. It is a figure explaining the electromagnetic induction noise reduction effect in Example 4. FIG. It is a figure explaining the flow of the electric current at the time of switching of two parallel semiconductor modules. It is a figure explaining the change of the current path at the time of switching in Example 4. FIG. It is a figure explaining the change of the current path of the connection conductor at the time of switching in Example 4. FIG. It is a figure explaining the change of the magnetic field by the electric current around the connection conductor at the time of switching in Example 4. FIG. It is a figure which shows the structure of the gate circuit in Example 5 of this invention. FIG. 10 is a diagram illustrating a mounting configuration of a gate resistance circuit in Example 5. It is a figure which shows the wiring pattern of the gate resistance circuit in Example 5. FIG. FIG. 10 is a schematic diagram for explaining a magnetic field caused by a main circuit current of Example 5. It is a figure which shows the circuit structure of the power converter device of Example 6 of this invention. 10 is a perspective view showing a configuration of Example 6. FIG. FIG. 10 is a diagram illustrating a mounting configuration of a gate resistance circuit in Example 6. It is a perspective view which shows the structure of the power converter device of Example 7 of this invention. FIG. 10 is a diagram illustrating a mounting configuration of a gate resistance circuit in Example 7. It is a perspective view which shows the structure of the power converter device of Example 8 of this invention. FIG. 10 is a diagram showing a top view of Example 8.

Explanation of symbols

2 Gate resistance circuit board 6 Radiator 7 Load 8 Power supply 11, 12 Semiconductor module 31P, 31N, 32P1, 32P2, 32N1, 32N2 Gate wiring 42, 43, 411, 412 Terminal 50 Smoothing capacitor 51, 52 Snubber circuit

Claims (9)

The first and second semiconductor modules having the same configuration are connected in parallel to each other, and the semiconductor module is provided in a pair of positive and negative semiconductor switching elements connected in series and at the edge of each semiconductor module. A positive electrode terminal and a negative electrode terminal connected to the pair of semiconductor switching elements, and a positive electrode that is provided at an opposite edge different from the edge where the positive electrode terminal and the negative electrode terminal are located and controls the pair of semiconductor switching elements, respectively. In the power converter configured to have a control terminal and a negative electrode control terminal,
A control circuit board on which a control circuit for controlling each switching element of each of the first and second semiconductor modules is mounted is disposed in a projection region of one semiconductor module,
The control circuit includes: a positive control circuit that controls switching elements on the positive side of the first and second semiconductor modules; a negative control circuit that controls switching elements on the negative side of the first and second semiconductor modules; Is mounted on the control circuit board,
The positive electrode control circuit, the negative electrode control terminal of the semiconductor module, wherein the control circuit board is arranged, the negative electrode control circuit is arranged to the positive control terminal of the semiconductor module, wherein the control circuit board is arranged The power converter characterized by the above-mentioned. The first and second semiconductor modules having the same configuration are connected in parallel to each other, and the semiconductor module is provided in a pair of positive and negative semiconductor switching elements connected in series and at the edge of each semiconductor module. A positive electrode terminal and a negative electrode terminal connected to the pair of semiconductor switching elements, and a positive electrode that is provided at an opposite edge different from the edge where the positive electrode terminal and the negative electrode terminal are located and controls the pair of semiconductor switching elements, respectively. In the power converter configured to have a control terminal and a negative electrode control terminal,
A control circuit board on which a control circuit for controlling each switching element of the first and second semiconductor modules is mounted is disposed in the projection region of one semiconductor module,
The control circuit board is disposed at a position affected by electromagnetic induction noise due to an internal current of the semiconductor module in the projection area of the semiconductor module,
Wherein the control circuit, power conversion device, wherein a circuit component is mounted in the direction of the magnetic field such that the area of the loop circuit flux according to the electromagnetic induction noise interlinked is reduced. The first and second semiconductor modules having the same configuration are connected in parallel to each other, and the semiconductor module is provided in a pair of positive and negative semiconductor switching elements connected in series and at the edge of each semiconductor module. A positive electrode terminal and a negative electrode terminal connected to the pair of semiconductor switching elements, and a positive electrode that is provided at an opposite edge different from the edge where the positive electrode terminal and the negative electrode terminal are located and controls the pair of semiconductor switching elements, respectively. In the power converter configured to have a control terminal and a negative electrode control terminal,
A control circuit board on which a control circuit for controlling each switching element of each of the first and second semiconductor modules is mounted is disposed in a projection region of one semiconductor module,
The control circuit board is disposed at a position affected by electromagnetic induction noise due to an internal current of the semiconductor module in the projection area of the semiconductor module;
The power converter according to claim 1, wherein the control circuit is arranged such that a direction of a loop circuit in which a magnetic flux related to the electromagnetic induction noise is linked is a direction in which the control circuit does not malfunction due to a change in the magnetic flux. A pair of positive and negative semiconductor switching elements connected in series, a positive terminal and a negative terminal connected to the pair of semiconductor switching elements, and edges having the positive terminal and the negative terminal are different from each other . In a power conversion device including a semiconductor module having a positive electrode control terminal and a negative electrode control terminal that are provided at an edge and respectively control the pair of semiconductor switching elements.
A control circuit board on which a control circuit for controlling each switching element of the semiconductor module is mounted is disposed in the projection area of the semiconductor module ,
The control circuit board is disposed at a position affected by electromagnetic induction noise due to an internal current of the semiconductor module in the projection area of the semiconductor module,
The power converter according to claim 1, wherein the control circuit has circuit components mounted in a magnetic field direction so as to reduce an area of a loop circuit in which magnetic flux related to the electromagnetic induction noise is linked . A pair of positive and negative semiconductor switching elements connected in series, a positive terminal and a negative terminal connected to the pair of semiconductor switching elements, and edges having the positive terminal and the negative terminal are different from each other. In a power conversion device including a semiconductor module having a positive electrode control terminal and a negative electrode control terminal that are provided at an edge and respectively control the pair of semiconductor switching elements.
A control circuit board on which a control circuit for controlling each switching element of the semiconductor module is mounted is disposed in the projection area of the semiconductor module,
The control circuit board is disposed at a position affected by electromagnetic induction noise due to an internal current of the semiconductor module in the projection area of the semiconductor module,
The power converter according to claim 1, wherein the control circuit is arranged such that a direction of a loop circuit in which a magnetic flux related to the electromagnetic induction noise is linked is a direction in which the control circuit does not malfunction due to a change in the magnetic flux. The power conversion device according to claim 2 ,
Wherein the control circuit, the orientation of the loop circuit flux interlinked according to electromagnetic induction noise, power conversion apparatus characterized by the control circuit is arranged in a direction that does not malfunction by a change in the magnetic flux. The first and second semiconductor modules having the same configuration are connected in parallel to each other, and the semiconductor module is provided in a pair of positive and negative semiconductor switching elements connected in series and at the edge of each semiconductor module. A positive electrode terminal and a negative electrode terminal connected to the pair of semiconductor switching elements, and a positive electrode that is provided at an opposite edge different from the edge where the positive electrode terminal and the negative electrode terminal are located and controls the pair of semiconductor switching elements, respectively. In the power converter configured to have a control terminal and a negative electrode control terminal,
A control circuit board on which a control circuit for controlling each switching element of the first and second semiconductor modules is mounted is disposed in the projection region of one semiconductor module,
A first portion in which a positive electrode conductor and a negative electrode conductor connected to a positive electrode terminal and a negative electrode terminal of the first and second semiconductor modules, respectively, are disposed in close proximity to each other; and the positive electrode conductor and the negative electrode conductor are adjacent to each other And a second portion that is not arranged, and a wiring from the control circuit board to a control terminal of the other semiconductor module is passed through a region in the vicinity of the first portion. Conversion device. The first and second semiconductor modules having the same configuration are connected in parallel to each other, and the semiconductor module is provided in a pair of positive and negative semiconductor switching elements connected in series and at the edge of each semiconductor module. A positive electrode terminal and a negative electrode terminal connected to the pair of semiconductor switching elements, and a positive electrode that is provided at an opposite edge different from the edge where the positive electrode terminal and the negative electrode terminal are located and controls the pair of semiconductor switching elements, respectively. In the power converter configured to have a control terminal and a negative electrode control terminal,
A control circuit board on which a control circuit for controlling each switching element of the first and second semiconductor modules is mounted is disposed in the projection region of one semiconductor module,
The control circuit includes two positive control circuits that control the switching elements on the positive side of the first and second semiconductor modules, and two that control the switching elements on the negative side of the first and second semiconductor modules. A negative electrode control circuit is mounted on the control circuit board,
The power converter according to claim 1, wherein the two positive electrode control circuits and the two negative electrode control circuits have the same wiring pattern. The first and second semiconductor modules having the same configuration are connected in parallel to each other, and the semiconductor module is provided in a pair of positive and negative semiconductor switching elements connected in series and at the edge of each semiconductor module. A positive electrode terminal and a negative electrode terminal connected to the pair of semiconductor switching elements, and a positive electrode that is provided at an opposite edge different from the edge where the positive electrode terminal and the negative electrode terminal are located and controls the pair of semiconductor switching elements, respectively. In the power converter configured to have a control terminal and a negative electrode control terminal,
A control circuit board on which a control circuit for controlling each switching element of the first and second semiconductor modules is mounted is disposed in the projection region of one semiconductor module,
The control circuit includes two positive control circuits that control the switching elements on the positive side of the first and second semiconductor modules, and two that control the switching elements on the negative side of the first and second semiconductor modules. A negative electrode control circuit is mounted on the control circuit board,
The two positive electrode control circuits and the two negative electrode control circuits each include a gate sensitivity correction resistor that connects between control terminals of the corresponding semiconductor switching elements, and the circuit related to the gate sensitivity correction resistor includes the semiconductor module. A power conversion device , wherein circuit components are mounted in a magnetic field direction so that an area of a loop circuit where magnetic flux related to electromagnetic induction noise due to an internal current is linked is reduced.

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