JP4593236B2 - Dimensional measurement scanning electron microscope system, circuit pattern shape evaluation system and method - Google Patents

Description

  The present invention relates to a dimension measurement scanning electron microscope system and a circuit pattern shape evaluation system and method for evaluating a finished state of a circuit pattern formed on a semiconductor wafer in a semiconductor lithography process. The present invention relates to a system and method for evaluating a finished state of a formed circuit pattern by comparing a circuit pattern actually formed on a semiconductor wafer with a target design circuit pattern shape.

  In the semiconductor manufacturing process, various semiconductor devices are manufactured by transferring a circuit pattern shape such as an element pattern or wiring pattern designed using a CAD apparatus onto a wafer using a photomask (reticle). However, with the recent development of high integration technology, elements and wirings are becoming finer. With this miniaturization, the size of the circuit pattern transferred onto the wafer becomes smaller than the wavelength of the light source that exposes the circuit pattern, making it difficult to transfer the fine circuit pattern formed on the photomask to the resist with the desired resolution. It is becoming. As a result, as shown in FIG. 1, the difference in shape between the circuit pattern (101) formed on the photomask and the resist pattern (102) formed by exposure is significant. For example, a resist pattern (103) based on a square circuit pattern formed on a photomask has a circular shape (104), or a corner portion (105) that bends at a right angle of the photomask has a round shape (106). It becomes. Furthermore, a pattern in which rectangular line portions and rectangular space portions are regularly and alternately formed in the photomask and the line portions and the space portions have a predetermined size is formed in the resist pattern. There are also phenomena in which the images are not correctly transferred alternately or the line portion and the space portion deviate from a predetermined size. The pattern shape deterioration in these resist patterns is caused by a physical phenomenon called optical proximity effect (OPE). Such pattern shape deterioration of the resist pattern causes a malfunction of the semiconductor product. In view of this, the pattern shape deterioration of the resist pattern to be formed is corrected by correcting the pattern formed on the photomask in advance. For example, it can improve the shape of the resist pattern, but its own shape is not transferred. A fine correction pattern is placed in contact with, close to, or adjacent to the photomask circuit pattern. There is a method of appropriately providing a large size portion or a small size portion in the circuit pattern of the photomask. Such a correction technique is called an optical proximity correction (OPC (Optical Proximity Correction)) technique. The resist pattern formed in this way is used in places where the miniaturization is remarkable, and the difference between the design shape of the photomask pattern and the resist pattern transfer shape actually formed on the wafer has been completed. As a result, the performance is greatly affected, which is an important problem in quality control. In order to solve this problem, conventionally, the line width of the pattern formed on the wafer is measured using a measuring SEM that can be measured with high accuracy, and the mask design, exposure, and other process conditions are optimized. I went. However, in the future, along with further miniaturization of the design pattern that is further accelerated, not only the measurement of the line width dimension but also a measurement / evaluation method capable of grasping the detailed formation state of the resist pattern will be required.

  The semiconductor wafer pattern shape evaluation technique is known in Japanese Patent Laid-Open Nos. 2002-31525, 2002-353280, and 2004-228394. In addition, JP-A-8-160598, JP-A-2000-58410, JP-A-2002-81914, JP-A-2003-16463, and JP-A-2003-21605 are known as conventional techniques. Yes.

JP 2002-31525 A JP 2002-353280 A JP 2004-228394 A JP-A-8-160598 JP 2000-58410 A JP 2002-81914 A JP 2003-16463 A JP 2003-21605 A

  As described above, with the miniaturization of elements and wiring due to the development of high integration technology in the semiconductor manufacturing process, circuit patterns are formed using optical proximity correction (OPC) technology, which is a miniaturization technology. It was. When the circuit pattern formed in this way becomes finer, detailed geometric features of the circuit pattern such as the position of the edge of the circuit pattern, the degree of rounding of the circuit pattern corners, and the distance between adjacent circuit patterns contribute to semiconductor device performance. As a result, the finished state of the resist pattern cannot be sufficiently evaluated only by the conventional line width measurement.

  An object of the present invention is to solve the above-described problems, and evaluate the finished state of a fine pattern even if a circuit pattern is formed using an optical proximity correction (OPC) technique which is a miniaturization technique in a semiconductor lithography process. Another object of the present invention is to provide a dimension measurement scanning electron microscope system, a circuit pattern shape evaluation system, and a method thereof.

  In order to achieve the above object, the present invention provides an electronic device for acquiring observation data of an exposure circuit pattern in which a circuit pattern actually formed on a mask is exposed on an exposed substrate using an exposure apparatus having a predetermined exposure condition. Type or optical observation microscope, input means for inputting the design data of the exposure circuit pattern obtained from a CAD device, etc., exposure circuit pattern design data input by the input means and exposure acquired by the observation microscope Evaluation for the optical proximity correction evaluation of the exposure by superimposing the observation data of the circuit pattern, and quantifying the one-dimensional or two-dimensional geometric feature indicating the difference between the superposed processes. An evaluation system and method for a circuit pattern shape, comprising an evaluation index calculation means for calculating an index.

  Further, according to the present invention, in the evaluation index calculation means, the geometric feature to be quantified includes a line width dimension value of the circuit pattern, a receding dimension from the design position of the circuit pattern end, and between adjacent circuit patterns. It is characterized in that it is all or a part of the distance, the degree of rounding of the circuit pattern corner, the radius or the ratio of the minor axis to the major axis of the circular or elliptical circuit pattern, and the area of the circuit pattern.

  The present invention further includes input means for inputting design data of the circuit pattern of the mask created by the mask design processing unit and the predetermined exposure condition, and the circuit of the mask inputted by the input means. An exposure simulator for calculating and calculating the evaluation index by calculating transfer circuit pattern data when the mask circuit pattern design data is exposed on the substrate to be exposed based on the pattern design data and the predetermined exposure condition; In the means, the transfer circuit pattern data obtained by the exposure simulator and the exposure circuit pattern observation data are matched to calculate the position of the transfer circuit pattern data that can be correlated, and the calculated transfer circuit pattern data The exposure is performed by replacing the design data of the exposure circuit pattern at the data position. Characterized by being configured to process the overlay and the design data of the road pattern and observation data of the exposure circuit pattern.

  Further, in the exposure simulator according to the present invention, the calculated transfer circuit pattern data is obtained by cutting the light intensity distribution with an appropriate light intensity or by cutting the light intensity distribution. Of the cross-sectional shape data obtained by varying the light intensity, the cross-sectional shape data obtained is the selected cross-sectional shape data that is close in shape to the observation data of the exposure circuit pattern.

  Further, the present invention is characterized in that the evaluation index calculation means includes a display means for displaying the observation data of the exposure circuit pattern and the design data of the exposure circuit pattern in an overlapped manner.

  In the present invention, the evaluation index calculation means includes display means for displaying all or part of the quantified geometric feature value.

  Further, the present invention is characterized in that the exposure simulator further comprises display means for displaying the design data of the circuit pattern of the mask and the data of the transfer circuit pattern in an overlapped manner.

  Further, according to the present invention, when the evaluation index calculation means determines that the calculated evaluation index is outside the allowable range, the evaluation index is within the allowable range for the mask design processing unit or the exposure apparatus. It is characterized by having means for feeding back the position information of the critical location outside, the kind of evaluation index, and the evaluation index value.

  Further, the present invention is characterized in that the evaluation index calculation means has means for outputting a warning when it is determined that the calculated evaluation index is out of an allowable range.

  Further, the present invention provides a dimension measurement scanning electron microscope for acquiring SEM observation data of an exposure circuit pattern in which a circuit pattern actually formed on a mask is exposed on an exposed substrate using an exposure apparatus having predetermined exposure conditions. An input unit for inputting design data of the exposure circuit pattern obtained from a CAD apparatus or the like, a design data of the exposure circuit pattern input by the input unit, and the acquired exposure By superimposing the SEM observation data of the circuit pattern, and quantifying the one-dimensional or two-dimensional geometric feature indicating the difference between the two subjected to the superimposition processing, the optical proximity correction evaluation for the exposure is performed. An evaluation index calculating means for calculating an evaluation index is provided.

  In the length measurement SEM system, the present invention further includes input means for inputting design data of a circuit pattern of a mask created by a mask design processing unit and the predetermined exposure condition, and the input means An exposure simulator that calculates and calculates transfer circuit pattern data when the mask circuit pattern design data is exposed on the substrate to be exposed based on the input mask circuit pattern design data and the predetermined exposure conditions. In the evaluation index calculation means, the transfer circuit pattern data obtained by the exposure simulator and the SEM observation data of the exposure circuit pattern are matched to calculate the position of the transfer circuit pattern data that can be correlated. The design data of the exposure circuit pattern at the calculated transfer circuit pattern data position Replaced by characterized by being configured to process superimposing the SEM observation data of the exposure circuit pattern and the design data of the exposure circuit pattern by positioning.

  According to the present invention, a high-precision and detailed evaluation index value necessary for optical proximity correction (OPC) evaluation is calculated from an observation image of an exposure circuit pattern (resist pattern), thereby making it possible to obtain a detailed pattern shape that could not be achieved in the past Evaluation is possible and the efficiency of mask design can be improved.

  Further, according to the present invention, each evaluation index value is expressed quantitatively, so that the evaluation can be performed efficiently.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a dimension measurement scanning electron microscope system, a circuit pattern shape evaluation system, and a method thereof, which can evaluate a fine pattern finished state in a resist pattern obtained in a semiconductor lithography process according to the present invention Will be described.

  That is, the present invention quantifies the difference between the image data obtained by observing the circuit pattern formed in the semiconductor lithography process with an electronic or optical observation microscope and the design data of the circuit pattern, and expresses the geometric state representing the pattern shape state. The feature amount is to be calculated.

  In particular, in a fine circuit pattern, a slight difference in circuit pattern shape affects device performance. Therefore, it is necessary to obtain the above geometric feature value with high accuracy. It is also necessary to perform the overlay processing of both data for obtaining the difference from the observation data of (resist pattern) with high accuracy. However, since the design data and the resist pattern may be largely different from each other due to the above-mentioned OPE (optical proximity effect), it is difficult to accurately perform the overlay process using both patterns as they are.

  Therefore, the present invention proposes a method for performing high-precision overlay processing between design data and resist pattern observation data, and calculates high-precision geometric features for evaluating the finished state of a fine pattern. Made it possible.

(1) Overall Flow of Embodiment FIG. 2 is a schematic diagram of an OPC (optical proximity correction) evaluation flow in a semiconductor lithography process according to the present invention.

  The flow will be briefly described below. In the first step (Step 1) 201 of this flow, for example, in the mask design processing unit 517 shown in FIG. 5, based on the design data (200) of the exposure circuit pattern that realizes a desired operation, the optical proximity effect (OPE) (Optical Proximity Effect)) is taken into consideration, and a mask pattern (mask exposure pattern) is manufactured. Next, in the second step (Step 2) 202, the exposure apparatus 519 shown in FIG. 5 performs exposure based on the mask pattern manufactured in the first step 201, and a resist pattern (exposure circuit) is formed on the semiconductor wafer. Pattern). Next, in a third step (Step 3) 203, the formed resist pattern is measured by, for example, a dimension measurement scanning electron microscope (hereinafter, length measurement SEM) shown in FIG. 5 to obtain SEM image data. In this way, the resist pattern is measured by the length measuring SEM, and the SEM image is obtained because the resist pattern formed on the semiconductor wafer is 100 nm to 80 nm and further reduced to 65 nm to 30 nm. It is because it is in a tendency. If the resist pattern is about 100 nm to 80 nm or more, it is possible to acquire the data of the dimension measurement image even with an optical microscope, for example, an ultraviolet optical microscope. Next, in a fourth step (Step 4) 204, for example, the image processing unit 511 shown in FIG. 5 obtains the exposure simulation processing 206 based on the initial design data 200 obtained from, for example, the mask design processing unit 517 or the CAD apparatus. The transfer pattern and the SEM image obtained from the length measurement SEM in the third step 203 are searched and collated to superimpose them (matching processing). In the fifth step (Step 5) 205, the fourth step The difference between the circuit pattern design data superimposed in step 204 and the SEM image of the resist pattern is evaluated, the quality of the resist pattern is evaluated, and the evaluation result (the OPC evaluation index calculation result for the OPC evaluation point) is sent to the workstation ( Provided to the overall control unit) 515 on the GUI screen etc. Forces. If the formed resist pattern satisfies the evaluation criteria in the output evaluation result, the semiconductor wafer is advanced to the next semiconductor process step (209). On the other hand, if the quality of the formed resist pattern does not satisfy the evaluation criteria, the information is fed back to the mask design / creation step (first step) 201 in the mask design processing unit 517 (208), and the mask design is performed. Then, the mask pattern is created again. This process is repeated until a desired resist pattern can be formed. The evaluation criterion here is a criterion for determining whether or not the degree of deviation between the formed resist pattern and the design data is within an allowable range in which the target circuit operates normally. This evaluation reference value is set at the circuit design stage (200) or the mask pattern design stage (201) in consideration of the operating characteristics of the design circuit. As described above, optical proximity correction (OPC) evaluation is performed to obtain a mask pattern for obtaining a desired resist pattern.

  Details of the OPC (optical proximity correction) evaluation according to the present invention will be described below.

(2) CAD-SEM overlay processing In general measurement point alignment in the length measurement SEM, the positional relationship (direction and distance) between the evaluation point and the alignment pattern is determined in advance with reference to the alignment pattern on the wafer. When storing and measuring, the length measurement SEM stage shift or beam shift from the alignment pattern to the evaluation point is performed. However, when measurement is performed at a high magnification (for example, measurement field of view 5 μm to 0.5 μm) as in OPC evaluation, the CAD data and the resist pattern are overlaid due to the influence of the movement error from the alignment pattern to the evaluation point. The accuracy of is worse. Therefore, the following overlay processing is performed in order to perform overlay accuracy of about several nanometers necessary for performing detailed OPC evaluation.

  That is, an overlay process of design data and an SEM image of a resist pattern will be described. The resist pattern completion evaluation in the fifth step 5 of the above evaluation flow is realized by evaluating the difference between the design data (300) and the SEM image (303) of the resist pattern. Therefore, as shown in FIG. 3, the exposure circuit pattern design data (300) and the resist pattern SEM image (303) are superimposed (304), and the difference between them is quantified (quantified) (quantified). How to do this will be described later). The superimposing process is realized by matching the two (details will be described later). However, when the matching process is performed between the design data itself (300) and the SEM image (303) of the resist pattern, the shapes of the two are often greatly separated by OPE (optical proximity effect) in the exposure process. There are cases where the overlaying fails or the accuracy of the overlaying deteriorates.

  By the way, in order to perform highly accurate OPC evaluation, it is necessary to perform overlay processing of design data (300) and an SEM image (303) of a resist pattern with high accuracy. Therefore, in the present invention, the transfer pattern (302) formed when exposed with the designed max pattern is calculated using an exposure simulator (workstation (overall control unit) 515 shown in FIG. 5) (206 shown in FIG. 2). Then, the matching process (305) is performed on the transfer pattern (302) and the resist pattern (303) obtained by the simulation, thereby improving the alignment accuracy. This is because the accuracy of alignment is improved because the transfer pattern is closer to the actual resist pattern shape than the design data.

  The outline of this method will be described with reference to FIG. The exposure simulator 515 calculates the transfer pattern of the resist formed on the semiconductor wafer based on the mask pattern data (301) created by calculation based on the design data (300) in the mask design processing unit 517 (details). Will be described later). A matching process is performed between the calculated transfer pattern (302) and the actual resist pattern (303), and the two patterns are superimposed (305). Here, since the positional relationship between the transfer pattern (302) calculated based on the mask pattern (301) and the design data (300) is known in the simulation process, for example, in the OPC evaluation in the image processing unit 511, the design is performed. By replacing the data (300) with the transfer pattern (302) and positioning it, a result of superimposing the design data (300) and the resist pattern (303) can be obtained (304).

  An outline of a transfer pattern calculation method using the above-described exposure simulation will be described with reference to FIG. By inputting max data (401) and exposure conditions (light wavelength λ, numerical aperture NA, apparent size σ (partial coherence), defocus, etc.) to the exposure simulation (exposure simulator 515). The light intensity distribution (403) when exposed with the designed mask data can be calculated. Naturally, the exposure simulator 515 has input means for inputting the max data (401) and the exposure conditions. As shown in FIG. 5, for example, the mask data 401 may be input from the mask design processing unit 517 via the network 516, and the exposure conditions may be input from the exposure apparatus 519 via the network 516. In this case, the input means includes a mask design processing unit 517, an exposure apparatus 519, and a network 516.

Next, the exposure simulator will be described. That is, as shown in FIG. 4, by using an exposure simulator, a mask (reticle) designed based on mask data (401) forming a measurement object (resist pattern) and exposure conditions, which are input by an input means. ) Calculate the light intensity distribution (403) when exposed by data. FIG. 13 shows a schematic diagram of an exposure optical system and an exposure simulation model. Illumination emitted from the light source surface (1300) irradiates an exposure mask pattern (reticle) (1302) through a lens L1 (1301). An image of the light source surface (1300) is formed on the pupil surface (1304) by the lens L1 (1301) and the lens L2 (1303). The image of the object plane (1302) is formed on the image plane (1306) by the lens L2 (1303) and the lens L3 (1305). The action of each lens in these optical systems can be modeled by Fourier transform and inverse Fourier transform. From the light source surface (1300) to the object surface (1302), the inverse Fourier transform and from the object surface (1302), respectively. The pupil plane (1304) can be associated with the Fourier transform, and the pupil plane (1304) to the image plane (1306) can be associated with the inverse Fourier transform. A flow of simulation based on the above association is shown in a broken line frame in FIG. The following (1) to (6) show the flow of simulation.
(1) The shape (1307) of the light source is determined from the illumination conditions (light wavelength λ, numerical aperture NA, apparent size σ of the light source, etc.).
(2) The illumination (1307) is subjected to inverse Fourier transform (1308) to obtain an illumination distribution (1310) on the object plane.
(3) The exposure mask pattern (reticle) (1309 (401)) is multiplied by the illumination distribution (1310) calculated in (2) to obtain the state (1311) in which the pattern is illuminated.
(4) The calculation result (1311) of (3) is Fourier transformed (1312) to obtain a diffraction pattern (1314) of the pattern on the pupil plane.
(5) Multiply the pupil plane (1313) by the calculation result (1314) of (4) to obtain a diffraction image (1315) after passing through the pupil plane.
(6) The inverse Fourier transform is performed on (5) (1316) to obtain an image plane pattern (1317).

  By this method, the shape of the illumination, the numerical aperture NA, the wavelength λ of the illumination light, the apparent size σ of the light source, the shape of the exposure mask (reticle) based on the design data 300, the size of the pupil, etc. can be arbitrarily designated. Thus, the light intensity distribution (1317 (403)) formed by the designated exposure condition and exposure mask can be calculated by the exposure simulator 515 and stored in the storage medium 514, for example.

  Next, the CAD data (design data) and the SEM image of the calculation result (light intensity distribution 403 (1317)) of the exposure simulator 515 described above are applied to, for example, an overlay process in the image processing unit 511 shown in FIG. The application will be described. That is, the exposure simulator 515 can slice (402) the calculated light intensity distribution (403) with a certain light intensity and provide the cross-sectional shape to the image memory 513 as a transfer pattern (404 (302)).

  The CPU 512 of the image processing unit (evaluation index calculating means) 511 performs matching processing on the transfer pattern (404) stored in the image memory 513 and the SEM image (303) of the resist pattern by image processing, and the overlapping position of both patterns. Is calculated.

  As an example of a matching method in the CPU 512 of the image processing unit (evaluation index calculating means) 511, an edge image is calculated from both images of the transfer pattern and the SEM image, and, for example, normalized correlation between both images is taken, The position where the correlation value is maximum is taken as the overlapping position.

  Further, the exposure simulator 515 varies the light intensity to be sliced (405), calculates the cross-sectional shape at each slice, stores it in the image memory 513, and the image processing unit 511 stores each image stored in the image memory 513. There is also a method of matching the cross-sectional shape at the slice and the SEM image (303) of the resist pattern by image processing. When this method is used, it becomes possible to match the transfer pattern (302) having a shape closer to the resist pattern and the SEM image (303) of the resist pattern, and design data (300 for the SEM image (303) of the resist pattern is obtained. ) Is determined with high accuracy, the overlay accuracy between the design data (300) and the SEM image (303) of the resist pattern is further improved. Note that the matching method based on image processing is not limited to this example. As described above, the image processing unit 511 realizes high-precision overlay processing of the design data (300) and the resist pattern (303).

  That is, the light intensity distribution obtained by the exposure simulation becomes a distribution of values (light intensity) continuous in the wafer surface (XY plane) direction as indicated by (403) in FIG. Here, the cross-sectional shape (404) obtained by cutting (slicing) this distribution with an appropriate light intensity has a shape closer to a length-measurement SEM image (Top-Down VIEW) of the resist pattern as compared with the design pattern. Therefore, in the exposure simulator 515, the value (light intensity) for cutting (slicing) the light intensity distribution is changed and each cross-sectional shape is stored in the image memory 513. The image processing unit 511 superimposes each cross-sectional shape and the length-measuring SEM image of the resist pattern, searches for a cross-section having the highest degree of shape overlap (similar in shape), and determines the cross-sectional shape as CAD (300) − If used in the matching process of the SEM (303), highly accurate CAD-SEM overlay can be realized. Specifically, the value (light intensity) for cutting (slicing) the light intensity distribution is varied, and the normalized correlation between the edge image obtained from each cross section and the edge image obtained from the length measurement SEM image of the resist pattern The matching result with the cross section having the largest correlation value is used as the matching result.

(3) Configuration of Length Measurement SEM System (Circuit Pattern Shape Evaluation System) Used in Embodiments Here, an example of the configuration of the length measurement SEM and peripheral devices used for OPC evaluation of the present invention will be described. FIG. 5 is a block diagram showing a configuration of the length measurement SEM system, and a portion surrounded by a broken line 500 is a component that realizes an OPC evaluation function constructed on the length measurement SEM system. First, a wafer (exposed substrate: including a liquid crystal substrate) 507, which is a sample placed on the stage 509, has a resist pattern for obtaining a length measurement SEM image formed by, for example, a semiconductor lithography process. Become. In FIG. 5, a primary electron beam 502 emitted from an electron gun 501 is focused on a wafer 507 (including a liquid crystal substrate) placed on a stage 509 via a beam deflector 504, an ExB deflector 505, and an objective lens 506. Knotted and irradiated. When the electron beam is irradiated, secondary electrons are generated from the wafer 507 which is a sample. Secondary electrons generated from the wafer 507 are deflected by the ExB deflector 505 and detected by the secondary electron detector 508. It is generated from a sample having a resist pattern in synchronization with two-dimensional scanning of an electron beam by the deflector 504 or repeated scanning of the electron beam in the X direction by the deflector 505 and continuous movement of the wafer in the Y direction by the stage 509. By detecting electrons, a two-dimensional electron beam image (length measurement SEM image) of a resist pattern (exposure circuit pattern) is obtained. The signal detected by the secondary electron detector 508 is converted into a digital signal by the A / D converter 510 and sent to the image processing unit 511. The image processing unit (evaluation index calculation means) 511 includes an image memory storage medium 513 for temporarily storing a digital image, and a CPU 512 that calculates an OPC evaluation index value from an image on the image memory. The overall control is performed by a workstation (overall control unit) 515, and a graphical user can perform necessary apparatus operations, exposure simulation (shown in FIG. 13), confirmation of an OPC evaluation point input screen / OPC evaluation index calculation result described later, and the like. It can be realized by an interface (hereinafter referred to as GUI). In addition, the storage medium (storage device) 514 and the workstation 515 are connected to an external network 516 so that data can be exchanged with the outside. The calculated OPC evaluation index value can be fed back from the storage medium (storage unit) 514 to the mask design processing unit 517 and the exposure apparatus 519 through the network 516.

  Further, the design data (601) of the exposure circuit pattern (resist pattern) is input and stored in the storage unit 514 from a CAD device (not shown), the mask design processing unit 517, or the like. As a result, the evaluation index calculation means (image processing unit) 511 can calculate the evaluation index value.

(4) Calculation of Evaluation Index Here, an evaluation index value calculated by the evaluation index calculation unit (image processing unit) 511 in order to perform detailed OPC evaluation will be described. In order to perform detailed OPC evaluation, it is necessary to calculate not only the conventional measurement of the line width dimension of a pattern but also an evaluation index representing a geometric feature that is important for the quality evaluation of other resist patterns. There is.

  FIG. 6 shows an example of the evaluation index. FIG. 6 shows the SEM image of the resist pattern (600) stored in the image memory 513 and the design data (601) stored in the storage unit 514 superimposed on the display screen of the workstation 515, for example. . Examples of evaluation index types (types of evaluation indexes) (810 shown in FIG. 8) for detailed OPC evaluation include the following examples. CD value (602), GAP value (603), distance between patterns (604), shape index (corner roundness (605)), hole diameter (606).

  Each index value will be described below. The CD value (602) quantifies the line width of the resist pattern. The GAP value (603) is used to quantify the width of the resist pattern edge that has receded from the position intended in the design pattern as shown in FIG. 6 by OPE (optical proximity effect). The inter-pattern distance (604) quantifies the distance between adjacent patterns. The corner roundness (605) quantifies the corner roundness of the design pattern. The hole diameter (606) is used to quantify the radius (or major axis or minor axis) of a circular (or elliptical) pattern such as a contact hole. The evaluation index value raised here is one example, and the evaluation index value is not limited to this as long as it is an evaluation index representing the geometric characteristics of the resist pattern.

  If the above-mentioned index values (for example, CD value, GAP value, distance between patterns, corner roundness, hole diameter) are out of the allowable range of the set values at the time of circuit design, the device characteristics of the semiconductor element to be formed have desired properties. Unlike the above, there is a possibility of causing a malfunction of the circuit, and the occurrence of a poor connection between the layers of the semiconductor element (described later) may also cause a malfunction of the circuit. Therefore, detailed OPC evaluation can be realized by evaluating the quality of the resist pattern using the detailed evaluation index values shown in the present invention.

(5) GUI Display Here, using FIG. 7 and FIG. 8, an input and output GUI, for example, at a workstation 515 of a measuring device (for example, a length measurement SEM system shown in FIG. 5) that realizes the OPC evaluation method according to the present invention Will be described.

(5.1) Input Screen: Input of Measurement Point Here, an embodiment of an input screen of a measuring instrument that performs OPC evaluation of the present invention will be described. The pattern of the resist pattern to be formed is where the minute difference from the desired shape causes a fatal defect in device characteristics and the resist pattern is unstable and unstable due to variations in process conditions. The points that need to be evaluated (hereinafter referred to as critical points). The critical point can be calculated as a portion having a small process margin for obtaining a pattern shape having desired device characteristics by using exposure simulation at the mask pattern design stage. The position information of the calculated critical point on the CAD data is stored in the storage unit 514. When the formed resist pattern is evaluated after exposure with the designed mask pattern, a point to be evaluated is selected from the critical points.

  For example, FIG. 7 shows an example of the input screen shown to the user at the workstation 515. This input screen has a GUI (701) for selecting a critical point for OPC evaluation. Here, the function has a function of displaying a critical point on the design data (718) and designating an area (all or a part of the critical point) (702) to be evaluated. In this input screen, the simulation exposure conditions (light wavelength λ, numerical aperture NA, apparent size σ of light source, defocusing, etc.) when matching high-accuracy design data and SEM images using the aforementioned simulation are used. Etc.) An input GUI (707) is provided. Further, an evaluation mode selection screen (708) is provided. In the automatic measurement mode (709), an evaluation index value is automatically calculated from each fatal point in the designated area. At that time, by specifying the measurement pattern type (711), it is possible to evaluate an arbitrary critical point in the specified area. For example, it is possible to specify a pattern type and size (line width, hole diameter, etc.) such as a line pattern (712) and a hole pattern (713). In the manual measurement mode (710) of the evaluation mode selection screen (708), the critical point to be measured is manually specified, the measurement point type (evaluation index type) (714), etc., is measured according to the critical point pattern. It can be specified manually. As described above, it is possible to specify an OPC evaluation location on this input screen.

(5.2) Output Screen: CAD Data Overlay Display on SEM Image and Presentation of Evaluation Index Here, a method of presenting each calculated OPC evaluation index to the user will be described. FIG. 8 is an example of a GUI output screen for evaluation indices at the workstation 515, for example. The present invention has an OPC evaluation information display function including some or all of the display functions shown here. This output screen has a GUI (801) that presents an SEM image (802) of the resist pattern, design data (803), simulation results, and all or part of the pattern allowable range in an overlapping manner. The SEM image (802) is an image obtained by obtaining a resist pattern at a point where OPC evaluation is performed by length measurement SEM measurement and storing it in the image memory 513. As shown in FIG. 3, the design data (803) positioned at the position of the transfer pattern subjected to collation / retrieval processing (described above) between the SEM image (303) of the resist pattern and the transfer pattern data (302) is displayed as an SEM image. (802) Overlay and display. The simulation result is displayed by superimposing the calculated transfer pattern (302) on the SEM image (303) using the exposure simulator 515 based on the mask pattern (301) and the exposure conditions.

  The pattern allowable range as an evaluation index for OPC evaluation is displayed in an easy-to-understand manner on the GUI by superimposing the allowable range of the shape of the resist pattern to be generated on the SEM image (900) of the resist pattern as shown in FIG. To do. This figure shows the maximum allowable range (901) and the minimum allowable range (902) of the pattern. The image display area (801) shown in FIG. 8 has a function of displaying measurement points in an overlapping manner, and the types of evaluation indices calculated at the measurement points, such as the above-described CD value (804), GAP value ( 805), pattern interval (807), roundness of corners (806), hole diameter (808), and the like can be partially or entirely displayed. At that time, it is possible to select and display all or some of the evaluation index types, measurement locations, and measurement results. In addition, it has a function (809) that makes it possible to select an evaluation mode according to the purpose of calculating the evaluation index value. For example, the mask evaluation mode (816) is a mode (described above) in which the calculated OPC evaluation index is fed back to the mask design step (mask design processing unit 517). The process evaluation mode (817) is a mode in which the calculated OPC evaluation index is used to capture fluctuations in exposure and process conditions, and an alarm is sounded if it is outside the allowable range (details will be described later). Also, a GUI (810) for selecting an evaluation index value to be calculated is included. The selected evaluation index is calculated from the evaluation points set on the input screen. The calculation result of each index value is displayed on this output screen. It has a GUI (815) for selecting data to be displayed in an area (801) for presenting an image superimposed with the SEM image. Examples of items that can be selected for display include a length measurement SEM image display (811), a design data display (812), a simulation result display (813), a resist pattern shape allowable range display (814), and the like. The calculated evaluation index value is displayed on this screen or saved in a storage medium. The calculated detailed OPC evaluation index value is presented to the user by the GUI as described above.

(6) Process Evaluation Here, a method for using an evaluation index for process evaluation will be described. In the mass production line, the degree of deviation between the design data and the SEM image of the resist pattern is quantified by the evaluation index value as described above. FIG. 10 is a conceptual diagram of a process evaluation flow. A flow in a region surrounded by a broken line in the drawing shows a flow of the semiconductor manufacturing process (1001) (going from left to right). After the exposure process (1002) and the development process (1003), the etching process (1004) is performed. In this evaluation method, after the development process (1003), the resist pattern formed on the wafer is measured with a length measurement SEM (1009), and the SEM image of the resist pattern (exposure circuit pattern) obtained by the measurement is the same as described above. And a resist pattern design data (1005) are overlaid (1010). In the overlay process, transfer pattern data (1007) is calculated based on the photomask pattern data (1006) created based on the resist pattern design data (1005) and exposure conditions. 1008) is calculated. The calculated transfer pattern data and the SEM image of the resist pattern are overlaid (1010), and the positional relationship between the transfer pattern data (1008) and the resist pattern design data (1005) is within the simulation. Since the transfer pattern data (1008) and the resist pattern design data (1005) are replaced and positioned, the SEM image and the design data are superimposed (1010). Next, the difference between the superimposed design data and the SEM image of the resist pattern is calculated, and the completion of the resist pattern is evaluated (1011). If the formed resist pattern satisfies the evaluation criteria, the process proceeds to the next process step (1013). On the other hand, if the quality of the formed resist pattern does not satisfy the evaluation criteria, the information is fed back to the exposure device 519 (1012) to correct the exposure / process conditions. The information is fed back to the mask design processing unit 517 to correct the mask design. Reference numeral 1014 denotes a length measurement SEM system (circuit pattern shape evaluation system) having an OPC evaluation function according to the present invention.

  The evaluation criterion here is a criterion for determining whether or not the degree of deviation between the formed resist pattern and the design data is within an allowable range in which the target circuit operates normally. FIG. 12 shows an example of a resist pattern (1200) in which the calculated evaluation index satisfies the allowable range and a resist pattern (1205) that does not satisfy the allowable range. In this embodiment, the CD value (1202) and the GAP value (1203) of the pattern are calculated, and the CD value (1202) and the GAP are calculated when the design data (1206) and the resist pattern (1205) greatly deviate. If the value (1203) is outside the permissible range, it can be determined that the resist pattern is defective, and the resist pattern formed by stopping the next process step and increasing the exposure / process condition fluctuation amount. Warning that a defect has occurred. Further, as described above, the evaluation information of the defective part is displayed on the GUI, and the evaluation index type and the evaluation index value are presented to the user.

  The user performs exposure / process condition correction in the exposure apparatus 519 with reference to the information. As a result, detailed resist pattern evaluation can be performed to improve the yield of mass-produced wafers, and detailed evaluation index values can be calculated and displayed in an easy-to-understand manner on the GUI to improve process evaluation efficiency and reduce user burden. Can be planned.

(7) Overlay of design pattern of previous or subsequent process Here, a description will be given of a method of performing OPC evaluation using a design pattern of a process before or after observation data when performing OPC evaluation. The structure of the circuit formed on the wafer is formed not to be a single layer but to be stacked in a number of layers in the wafer thickness direction. Different layer patterns are transferred and formed by different masks, and in order to construct a circuit in each device, it is necessary to connect the patterns of the different layers. That is, the relative positional relationship with the pattern formed in the previous or subsequent layer is important. One example thereof is shown in FIG. In this example, a via (1100) in the subsequent process is connected to the SEM image (1105) of the resist pattern. Accordingly, it is necessary that the overlap between the SEM image (1105) of the resist pattern and the design data (1100) of the subsequent process via is within an allowable range. Therefore, in the OPC evaluation method of the present invention, the connection between layers can be evaluated by superimposing the design pattern of the previous or subsequent process on the SEM image of the resist pattern. The overlay process of the design data and the resist pattern is performed by overlaying the design data and the resist pattern of the same layer as the observed resist pattern using the same method as described above. Since the positional relationship between each layer is stored in the design data, the design data can be replaced with the previous or subsequent layer design data based on the overlay result of the resist pattern and the design data of the same layer. Thus, it is possible to superimpose the design data of the layer of the previous or subsequent process on the SEM image of the observed resist pattern. The evaluation index includes an interval (1101, 1102) between the resist pattern end (1100) and the design data (1100), an area of the overlapping portion (1103), and the like. Evaluation is made based on whether or not these evaluation index values are within an allowable range. As described above, OPC evaluation can be performed in consideration of the pattern connection relationship between different layers.

  As described above, according to the present embodiment, in the shape evaluation of the formation pattern in the semiconductor lithography process by the length measurement SEM or the like, an evaluation index that becomes important as the semiconductor design pattern becomes finer in the future is proposed, A method for presenting the index value to the user and a method for using the index value can be provided.

  According to the present invention, it becomes possible to perform highly accurate and detailed OPC evaluation that will be important in the future as the semiconductor design pattern becomes finer, and to improve the efficiency of the evaluation by presenting the evaluation result to the user in an easy-to-understand manner. Since it can contribute to the early mass production of an increasing number of low-volume semiconductor products, the industrial applicability is very high.

It is a figure explaining the relationship between a photomask pattern and an exposure circuit pattern (resist pattern). It is a flowchart which shows one Example of OPC evaluation which concerns on this invention. It is a figure for demonstrating one Example of the superimposition process by utilization of the exposure simulator which concerns on this invention. It is a figure for demonstrating one Example of utilization of the exposure simulation which concerns on this invention. It is a block diagram which shows one Example of the length measurement SEM system which concerns on this invention, or the evaluation system of a circuit pattern shape. It is a figure for demonstrating one Example of the OPC evaluation parameter | index which concerns on this invention. It is a figure which shows one Example of GUI (input screen) for OPC evaluation point input which concerns on this invention. It is a figure which shows one Example of the GUI display example (output screen) of the OPC evaluation index which concerns on this invention. It is a figure which shows one Example of the display of the tolerance | permissible_range which concerns on this invention. It is a figure which shows one Example of the process evaluation using the evaluation index value which concerns on this invention. It is a figure which shows one Example of the overlay display of the design data of the other layer which concerns on this invention. It is a figure which shows one Example of the process evaluation using the evaluation index value which concerns on this invention. It is a figure for demonstrating one Example of the exposure simulation by the exposure simulator which concerns on this invention.

Explanation of symbols

  300 ... Exposure circuit pattern design data, 301 ... Mask pattern design data, 302 ... Exposure circuit pattern transfer pattern (simulation result), 303 ... SEM image of exposure circuit pattern (resist pattern), 401 ... Mask data, 402 ... Slice, 403: Light intensity distribution, 404: Data of sliced cross-sectional shape, 500: Length measuring SEM having OPC evaluation function, 501 ... Electron gun, 503 ... Condenser lens, 504 ... Deflector, 505 ... ExB deflector, 506 ... objective lens, 507 ... wafer (substrate to be exposed), 508 ... secondary electron detector, 509 ... stage, 510 ... A / D converter, 511 ... image processing unit (evaluation index calculating means), 512 ... CPU, 513 ... Image memory, 514 ... Recording medium (storage device), 515 ... Overall control unit (Works Exposure simulator), 516 ... network, 517 ... mask design processing unit, 519 ... exposure apparatus, 520 ... controller, 701 ... GUI for input screen, 707 ... GUI for exposure condition input, 708 ... input evaluation mode selection screen, 711 ... Input measurement pattern type selection screen, 714 ... Input evaluation index type selection screen, 801 ... Output screen GUI, 809 ... Output evaluation mode selection screen, 810 ... Output evaluation index type selection screen, 815 ... Various output display selection screens, 1001 ... Semiconductor manufacturing process, 1002 ... Exposure process, 1003 ... Development process, 1004 ... Etching process, 1014 ... Length measurement SEM system (circuit pattern shape evaluation system) having an OPC evaluation function.

Claims (18)

A dimension measurement scanning electron microscope system that acquires SEM observation data of an exposure circuit pattern exposed on a substrate to be exposed using an exposure apparatus having a predetermined exposure condition for a circuit pattern actually formed on a mask,
Design data input means for inputting design data of the exposure circuit pattern;
One-dimensional or two-dimensional data indicating the difference between the overlay processing of the exposure circuit pattern design data input by the design data input means and the acquired SEM observation data of the exposure circuit pattern. Evaluation index calculating means for calculating an evaluation index for optical proximity correction evaluation of the exposure by quantifying the geometric feature of
Exposure condition input means for inputting design data of the circuit pattern formed on the mask and the predetermined exposure condition;
Transfer circuit pattern data when the mask circuit pattern design data is exposed on the substrate to be exposed based on the mask circuit pattern design data and the predetermined exposure conditions input by the exposure condition input means. With an exposure simulator calculated
In the evaluation index calculating means, the transfer circuit pattern data obtained by the exposure simulator and the SEM observation data of the exposure circuit pattern are matched to calculate the position of the transfer circuit pattern data that can be correlated, and the calculation The exposure circuit pattern design data and the SEM observation data of the exposure circuit pattern are overlaid by replacing the exposure circuit pattern design data with the transferred transfer circuit pattern data position. Dimensional measurement scanning electron microscope system. In the evaluation index calculation means, the geometric feature to be quantified includes the line width dimension value of the circuit pattern, the receding dimension from the design position of the circuit pattern end, the distance between adjacent circuit patterns, and the circuit pattern corner. 2. The dimension measurement scanning electron microscope according to claim 1, wherein the dimension measurement scanning electron microscope is all or part of a degree of rounding, a radius or ratio of a minor axis to a major axis of a circular or elliptical circuit pattern, and an area of a circuit pattern. system. In the exposure simulator, the calculated transfer circuit pattern data is obtained by varying the light intensity distribution that cuts the light intensity distribution or the sectional shape data obtained by cutting the light intensity distribution with an appropriate light intensity. 2. The dimension measurement scanning electron microscope according to claim 1, wherein the cross-sectional shape data obtained at each light intensity is selected cross-sectional shape data close to the SEM observation data of the exposure circuit pattern. system. 3. The evaluation index calculation means includes display means for displaying all or part of SEM observation data of the exposure circuit pattern and design data of the exposure circuit pattern in an overlapping manner. Dimension measurement scanning electron microscope system. The dimension measurement scanning electron microscope system according to claim 1, wherein the evaluation index calculation unit includes a display unit that displays all or a part of the quantified geometric feature amount. An observation microscope that acquires SEM observation data of an exposure circuit pattern exposed on a substrate to be exposed using an exposure apparatus having a predetermined exposure condition for the circuit pattern actually formed on the mask;
Input means for inputting design data of the exposure circuit pattern;
The design data of the exposure circuit pattern input by the input means and the SEM observation data of the exposure circuit pattern acquired by the observation microscope are superposed, and the one-dimensional or two-dimensional difference indicating the difference between the superposed processes An evaluation index calculating means for calculating an evaluation index for optical proximity correction evaluation of the exposure by quantifying a geometric feature of a dimension;
Input means for inputting design data of the circuit pattern of the mask and the predetermined exposure condition;
Based on the design data of the mask circuit pattern inputted by the input means and the predetermined exposure condition, the circuit pattern data of the mask is calculated when the exposure target substrate is exposed to the design data of the circuit pattern of the mask. An exposure simulator having display means to be obtained,
In the evaluation index calculating means, the transfer circuit pattern data obtained by the exposure simulator and the SEM observation data of the exposure circuit pattern are matched to calculate the position of the transfer circuit pattern data that can be correlated, and the calculation The exposure circuit pattern design data and the SEM observation data of the exposure circuit pattern are overlaid by replacing the exposure circuit pattern design data with the transferred transfer circuit pattern data position,
In the exposure simulator, a circuit pattern shape evaluation system characterized in that all or part of the design data of the circuit pattern of the mask and the data of the transfer circuit pattern are superimposed on the display means. In the evaluation index calculation means, the geometric feature to be quantified includes the line width dimension value of the circuit pattern, the receding dimension from the design position of the circuit pattern end, the distance between adjacent circuit patterns, and the circuit pattern corner. 7. The circuit pattern shape evaluation system according to claim 6, wherein the circuit pattern shape evaluation system is all or part of the degree of rounding, the radius or ratio of the minor axis to the major axis of the circular or elliptical circuit pattern, and the area of the circuit pattern. . In the exposure simulator, the calculated transfer circuit pattern data is obtained by varying the light intensity distribution that cuts the light intensity distribution or the sectional shape data obtained by cutting the light intensity distribution with an appropriate light intensity. 7. The circuit pattern shape evaluation system according to claim 6, wherein the cross-sectional shape data obtained at each light intensity is selected cross-sectional shape data that is close in shape to observation data of the exposure circuit pattern. 8. The evaluation index calculation means includes display means for displaying all or part of SEM observation data of the exposure circuit pattern and design data of the exposure circuit pattern in an overlapping manner. Circuit pattern shape evaluation system. 8. The circuit pattern shape evaluation system according to claim 6, wherein the evaluation index calculation means includes display means for displaying all or part of the quantified geometric feature value. In the evaluation index calculation means, when it is determined that the calculated evaluation index is out of the allowable range, a critical part where the evaluation index is out of the allowable range for the mask design processing unit or the exposure apparatus. 8. The circuit pattern shape evaluation system according to claim 6, further comprising means for feeding back position information, a type of evaluation index, and an evaluation index value. 8. The circuit pattern shape according to claim 6, further comprising a means for outputting a warning when the evaluation index calculation means determines that the calculated evaluation index is out of an allowable range. Evaluation system. An observation data acquisition step of acquiring observation data of an exposure circuit pattern exposed on the substrate to be exposed using an exposure apparatus having a predetermined exposure condition for the circuit pattern actually formed on the mask;
A design data input step for inputting design data of the exposure circuit pattern;
The exposure circuit pattern design data input in the design data input step and the exposure circuit pattern observation data acquired in the observation data acquisition step are overlaid, and the difference between the two subjected to the overlap processing is shown. An evaluation index calculation step for calculating an evaluation index for optical proximity correction evaluation of the exposure by quantifying a two-dimensional or two-dimensional geometric feature;
An exposure condition input step for inputting design data of the circuit pattern of the mask and the predetermined exposure condition;
Transfer circuit pattern data when the mask circuit pattern design data is exposed on the substrate to be exposed based on the mask circuit pattern design data and the predetermined exposure conditions input in the exposure condition input step An exposure simulation step for calculating and obtaining
In the evaluation index calculation step, the transfer circuit pattern data obtained in the exposure simulation step and the exposure circuit pattern observation data are matched to calculate the position of the transfer circuit pattern data that can be correlated, and the calculation The exposure circuit pattern design data and the exposure circuit pattern observation data are overlaid by replacing the exposure circuit pattern design data at the position of the transferred transfer circuit pattern data. Circuit pattern shape evaluation method. In the evaluation index calculating step, the geometric feature to be quantified includes the line width dimension value of the circuit pattern, the receding dimension from the design position of the circuit pattern end, the distance between adjacent circuit patterns, and the circuit pattern corner. 14. The method of evaluating a circuit pattern shape according to claim 13, wherein the circuit pattern shape is all or part of a rounding degree, a radius or a ratio of a minor axis to a major axis of a circular or elliptical circuit pattern, and an area of the circuit pattern. . In the exposure simulation step, the calculated transfer circuit pattern data is obtained by varying the cross-sectional shape data obtained by cutting the light intensity distribution with an appropriate light intensity or the light intensity for cutting the light intensity distribution. 14. The method of evaluating a circuit pattern shape according to claim 13, wherein the cross-sectional shape data obtained at each light intensity is selected cross-sectional shape data whose shape is close to the observation data of the exposure circuit pattern. . 15. The evaluation index calculating step includes a display step of superimposing or displaying all or part of the exposure circuit pattern observation data and the exposure circuit pattern design data on a display unit. The circuit pattern shape evaluation method described in 1. The circuit pattern shape evaluation according to claim 13 or 14, wherein the evaluation index calculation step includes a display step of displaying all or a part of the quantified geometric feature amount on a display means. Method. In the evaluation index calculation step, when it is determined that the calculated evaluation index is out of the allowable range, the critical design point where the evaluation index is out of the allowable range is determined for the mask design processing unit or the exposure apparatus. 15. The circuit pattern shape evaluation method according to claim 13, further comprising a step of feeding back position information, a type of evaluation index, and an evaluation index value.

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