JP4540933B2 - 薄層形成方法 - Google Patents

薄層形成方法 Download PDF

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Publication number
JP4540933B2
JP4540933B2 JP2002581571A JP2002581571A JP4540933B2 JP 4540933 B2 JP4540933 B2 JP 4540933B2 JP 2002581571 A JP2002581571 A JP 2002581571A JP 2002581571 A JP2002581571 A JP 2002581571A JP 4540933 B2 JP4540933 B2 JP 4540933B2
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Prior art keywords
layer
substrate
region
interface
bonding
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Expired - Lifetime
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JP2002581571A
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Japanese (ja)
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JP2004535664A5 (https=
JP2004535664A (ja
Inventor
アスパール，ベルナール
モリソー，ユベール
ジユシー，マルク
レサク，オリビエ
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コミサリヤ・ア・レネルジ・アトミク
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/50—Devices controlled by mechanical forces, e.g. pressure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/11—Separation of active layers from substrates
    • H10P95/112—Separation of active layers from substrates leaving a reusable substrate, e.g. epitaxial lift off
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7432—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/11—Methods of delaminating, per se; i.e., separating at bonding face

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  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Materials For Medical Uses (AREA)
  • Laminated Bodies (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
JP2002581571A 2001-04-13 2002-04-11 薄層形成方法 Expired - Lifetime JP4540933B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0105129A FR2823596B1 (fr) 2001-04-13 2001-04-13 Substrat ou structure demontable et procede de realisation
PCT/FR2002/001266 WO2002084721A2 (fr) 2001-04-13 2002-04-11 Substrat ou structure demontable et procede de realisation

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009297080A Division JP2010114456A (ja) 2001-04-13 2009-12-28 剥離可能な基板または剥離可能な構造、およびそれらの製造方法

Publications (3)

Publication Number Publication Date
JP2004535664A JP2004535664A (ja) 2004-11-25
JP2004535664A5 JP2004535664A5 (https=) 2005-12-22
JP4540933B2 true JP4540933B2 (ja) 2010-09-08

Family

ID=8862351

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2002581571A Expired - Lifetime JP4540933B2 (ja) 2001-04-13 2002-04-11 薄層形成方法
JP2009297080A Withdrawn JP2010114456A (ja) 2001-04-13 2009-12-28 剥離可能な基板または剥離可能な構造、およびそれらの製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2009297080A Withdrawn JP2010114456A (ja) 2001-04-13 2009-12-28 剥離可能な基板または剥離可能な構造、およびそれらの製造方法

Country Status (9)

Country Link
US (1) US7713369B2 (https=)
EP (1) EP1378003B1 (https=)
JP (2) JP4540933B2 (https=)
KR (1) KR100933897B1 (https=)
CN (1) CN100355025C (https=)
AU (1) AU2002304525A1 (https=)
FR (1) FR2823596B1 (https=)
TW (1) TW577102B (https=)
WO (1) WO2002084721A2 (https=)

Families Citing this family (122)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2823596B1 (fr) 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
FR2823599B1 (fr) * 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2846788B1 (fr) * 2002-10-30 2005-06-17 Procede de fabrication de substrats demontables
FR2847077B1 (fr) * 2002-11-12 2006-02-17 Soitec Silicon On Insulator Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation
FR2848336B1 (fr) * 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
FR2892228B1 (fr) * 2005-10-18 2008-01-25 Soitec Silicon On Insulator Procede de recyclage d'une plaquette donneuse epitaxiee
US20090325362A1 (en) * 2003-01-07 2009-12-31 Nabil Chhaimi Method of recycling an epitaxied donor wafer
EP1437426A1 (de) * 2003-01-10 2004-07-14 Siemens Aktiengesellschaft Verfahren zum Herstellen von einkristallinen Strukturen
US6759277B1 (en) * 2003-02-27 2004-07-06 Sharp Laboratories Of America, Inc. Crystalline silicon die array and method for assembling crystalline silicon sheets onto substrates
FR2852445B1 (fr) * 2003-03-14 2005-05-20 Soitec Silicon On Insulator Procede de realisation de substrats ou composants sur substrats avec transfert de couche utile, pour la microelectronique, l'optoelectronique ou l'optique
US7122095B2 (en) 2003-03-14 2006-10-17 S.O.I.Tec Silicon On Insulator Technologies S.A. Methods for forming an assembly for transfer of a useful layer
JP4794810B2 (ja) * 2003-03-20 2011-10-19 シャープ株式会社 半導体装置の製造方法
FR2856844B1 (fr) * 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
JP4581349B2 (ja) * 2003-08-29 2010-11-17 株式会社Sumco 貼合せｓｏｉウェーハの製造方法
US8475693B2 (en) 2003-09-30 2013-07-02 Soitec Methods of making substrate structures having a weakened intermediate layer
FR2860249B1 (fr) * 2003-09-30 2005-12-09 Michel Bruel Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium
JP4809600B2 (ja) * 2003-10-28 2011-11-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
FR2861497B1 (fr) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
FR2871291B1 (fr) * 2004-06-02 2006-12-08 Tracit Technologies Procede de transfert de plaques
JP4838504B2 (ja) * 2004-09-08 2011-12-14 キヤノン株式会社 半導体装置の製造方法
FR2876220B1 (fr) * 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
US7405108B2 (en) 2004-11-20 2008-07-29 International Business Machines Corporation Methods for forming co-planar wafer-scale chip packages
FR2878648B1 (fr) * 2004-11-30 2007-02-02 Commissariat Energie Atomique Support semi-conducteur rectangulaire pour la microelectronique et procede de realisation d'un tel support
FR2880189B1 (fr) * 2004-12-24 2007-03-30 Tracit Technologies Sa Procede de report d'un circuit sur un plan de masse
JP2006216891A (ja) * 2005-02-07 2006-08-17 Tokyo Univ Of Agriculture & Technology 薄膜素子構造の作製方法、及び薄膜素子構造作製用の機能性基体
US20090075429A1 (en) * 2005-04-27 2009-03-19 Lintec Corporation Sheet-Like Underfill Material and Semiconductor Device Manufacturing Method
FR2888400B1 (fr) * 2005-07-08 2007-10-19 Soitec Silicon On Insulator Procede de prelevement de couche
FR2889887B1 (fr) * 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
EP1777735A3 (fr) * 2005-10-18 2009-08-19 S.O.I.Tec Silicon on Insulator Technologies Procédé de recyclage d'une plaquette donneuse épitaxiée
FR2893750B1 (fr) * 2005-11-22 2008-03-14 Commissariat Energie Atomique Procede de fabrication d'un dispositif electronique flexible du type ecran comportant une pluralite de composants en couches minces.
EP1801870A1 (en) * 2005-12-22 2007-06-27 Princo Corp. Partial adherent temporary substrate and method of using the same
US7829436B2 (en) 2005-12-22 2010-11-09 Sumco Corporation Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer
US7781309B2 (en) * 2005-12-22 2010-08-24 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
TWI285424B (en) * 2005-12-22 2007-08-11 Princo Corp Substrate including a multi-layer interconnection structure, methods of manufacturing and recycling the same, method of packaging electronic devices by using the same, and method of manufacturing an interconnection device
CN1996582B (zh) * 2006-01-06 2012-02-15 巨擘科技股份有限公司 包含多层内连线结构的载板及其制造、回收以及应用方法
WO2007104444A1 (de) 2006-03-14 2007-09-20 Institut Für Mikroelektronik Stuttgart Verfahren zum herstellen einer integrierten schaltung
DE102006013419B4 (de) * 2006-03-14 2008-05-29 Institut Für Mikroelektronik Stuttgart Verfahren zum Herstellen einer integrierten Schaltung
DE102006059394B4 (de) * 2006-12-08 2019-11-21 Institut Für Mikroelektronik Stuttgart Integrierte Schaltung und Verfahren zu deren Herstellung
US8051557B2 (en) 2006-03-31 2011-11-08 Princo Corp. Substrate with multi-layer interconnection structure and method of manufacturing the same
US20080057678A1 (en) * 2006-08-31 2008-03-06 Kishor Purushottam Gadkaree Semiconductor on glass insulator made using improved hydrogen reduction process
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2912839B1 (fr) * 2007-02-16 2009-05-15 Soitec Silicon On Insulator Amelioration de la qualite de l'interface de collage par nettoyage froid et collage a chaud
FR2913968B1 (fr) * 2007-03-23 2009-06-12 Soitec Silicon On Insulator Procede de realisation de membranes autoportees.
WO2008123117A1 (en) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
FR2914493B1 (fr) 2007-03-28 2009-08-07 Soitec Silicon On Insulator Substrat demontable.
US7605054B2 (en) 2007-04-18 2009-10-20 S.O.I.Tec Silicon On Insulator Technologies Method of forming a device wafer with recyclable support
FR2922359B1 (fr) * 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
FR2925221B1 (fr) * 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
FR2926671B1 (fr) * 2008-01-17 2010-04-02 Soitec Silicon On Insulator Procede de traitement de defauts lors de collage de plaques
FR2926672B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication de couches de materiau epitaxie
US9111981B2 (en) * 2008-01-24 2015-08-18 Brewer Science Inc. Method for reversibly mounting a device wafer to a carrier substrate
FR2929758B1 (fr) * 2008-04-07 2011-02-11 Commissariat Energie Atomique Procede de transfert a l'aide d'un substrat ferroelectrique
TWI424587B (zh) * 2008-06-30 2014-01-21 Luxtaltek Corp Light emitting diodes with nanoscale surface structure and embossing molds forming nanometer scale surface structures
JP5478199B2 (ja) * 2008-11-13 2014-04-23 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
US9847243B2 (en) 2009-08-27 2017-12-19 Corning Incorporated Debonding a glass substrate from carrier using ultrasonic wave
US8187901B2 (en) 2009-12-07 2012-05-29 Micron Technology, Inc. Epitaxial formation support structures and associated methods
EP2529394A4 (en) 2010-01-27 2017-11-15 Yale University Conductivity based selective etch for gan devices and applications thereof
SG183820A1 (en) 2010-03-31 2012-10-30 Ev Group E Thallner Gmbh Method for producing a wafer provided with chips
US8852391B2 (en) 2010-06-21 2014-10-07 Brewer Science Inc. Method and apparatus for removing a reversibly mounted device wafer from a carrier substrate
EP2600400A4 (en) * 2010-07-30 2015-03-18 Kyocera Corp COMPOSITE SUBSTRATE, ELECTRONIC COMPONENT, METHOD FOR PRODUCING THE COMPOSITE COMPOSITE AND METHOD FOR PRODUCING THE ELECTRONIC COMPONENT
US9263314B2 (en) 2010-08-06 2016-02-16 Brewer Science Inc. Multiple bonding layers for thin-wafer handling
TWI500118B (zh) * 2010-11-12 2015-09-11 半導體能源研究所股份有限公司 半導體基底之製造方法
JP5926527B2 (ja) * 2011-10-17 2016-05-25 信越化学工業株式会社 透明ｓｏｉウェーハの製造方法
US8975157B2 (en) * 2012-02-08 2015-03-10 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US10543662B2 (en) 2012-02-08 2020-01-28 Corning Incorporated Device modified substrate article and methods for making
CN104471360B (zh) * 2012-06-18 2016-04-20 松下知识产权经营株式会社 红外线检测装置
US9583353B2 (en) 2012-06-28 2017-02-28 Yale University Lateral electrochemical etching of III-nitride materials for microfabrication
CN104507853B (zh) 2012-07-31 2016-11-23 索泰克公司 形成半导体设备的方法
WO2014026292A1 (en) * 2012-08-15 2014-02-20 Mcmaster University Arbitrarily thin ultra smooth film with built-in separation ability and method of forming the same
KR101392133B1 (ko) * 2012-08-20 2014-05-07 세종대학교산학협력단 서로 다른 젖음성을 갖는 영역들을 구비하는 캐리어 기판, 이를 사용한 소자 기판 처리 방법
FR2995447B1 (fr) 2012-09-07 2014-09-05 Soitec Silicon On Insulator Procede de separation d'au moins deux substrats selon une interface choisie
FR2995445B1 (fr) * 2012-09-07 2016-01-08 Soitec Silicon On Insulator Procede de fabrication d'une structure en vue d'une separation ulterieure
TWI617437B (zh) 2012-12-13 2018-03-11 康寧公司 促進控制薄片與載體間接合之處理
US10014177B2 (en) 2012-12-13 2018-07-03 Corning Incorporated Methods for processing electronic devices
US9340443B2 (en) 2012-12-13 2016-05-17 Corning Incorporated Bulk annealing of glass sheets
US10086584B2 (en) 2012-12-13 2018-10-02 Corning Incorporated Glass articles and methods for controlled bonding of glass sheets with carriers
DE102012112989A1 (de) * 2012-12-21 2014-06-26 Ev Group E. Thallner Gmbh Verfahren zum Aufbringen einer Temporärbondschicht
US9028628B2 (en) 2013-03-14 2015-05-12 International Business Machines Corporation Wafer-to-wafer oxide fusion bonding
US9058974B2 (en) 2013-06-03 2015-06-16 International Business Machines Corporation Distorting donor wafer to corresponding distortion of host wafer
JP2015035453A (ja) * 2013-08-07 2015-02-19 アズビル株式会社 ウエハ
US10510576B2 (en) 2013-10-14 2019-12-17 Corning Incorporated Carrier-bonding methods and articles for semiconductor and interposer processing
WO2017034644A2 (en) * 2015-06-09 2017-03-02 ARIZONA BOARD OF REGENTS a body corporate for THE STATE OF ARIZONA for and on behalf of ARIZONA STATE UNIVERSITY Method of providing an electronic device and electronic device thereof
US10381224B2 (en) * 2014-01-23 2019-08-13 Arizona Board Of Regents On Behalf Of Arizona State University Method of providing an electronic device and electronic device thereof
US10046542B2 (en) 2014-01-27 2018-08-14 Corning Incorporated Articles and methods for controlled bonding of thin sheets with carriers
FR3019374A1 (fr) * 2014-03-28 2015-10-02 Soitec Silicon On Insulator Procede de separation et de transfert de couches
CN106457758B (zh) 2014-04-09 2018-11-16 康宁股份有限公司 装置改性的基材制品及其制备方法
US11095096B2 (en) 2014-04-16 2021-08-17 Yale University Method for a GaN vertical microcavity surface emitting laser (VCSEL)
CN107078190B (zh) 2014-09-30 2020-09-08 耶鲁大学 用于GaN垂直微腔面发射激光器(VCSEL)的方法
US11018231B2 (en) 2014-12-01 2021-05-25 Yale University Method to make buried, highly conductive p-type III-nitride layers
JP2018524201A (ja) 2015-05-19 2018-08-30 コーニング インコーポレイテッド シートをキャリアと結合するための物品および方法
CN107710381B (zh) 2015-05-19 2022-01-18 耶鲁大学 涉及具有晶格匹配的覆层的高限制因子的iii族氮化物边发射激光二极管的方法和器件
US11905201B2 (en) 2015-06-26 2024-02-20 Corning Incorporated Methods and articles including a sheet and a carrier
KR20170033163A (ko) 2015-09-16 2017-03-24 임종순 수로관 및 이의 시공방법
DE102016106351A1 (de) * 2016-04-07 2017-10-12 Ev Group E. Thallner Gmbh Verfahren und Vorrichtung zum Bonden zweier Substrate
US20180019169A1 (en) * 2016-07-12 2018-01-18 QMAT, Inc. Backing substrate stabilizing donor substrate for implant or reclamation
TW202216444A (zh) 2016-08-30 2022-05-01 美商康寧公司 用於片材接合的矽氧烷電漿聚合物
TWI810161B (zh) 2016-08-31 2023-08-01 美商康寧公司 具以可控制式黏結的薄片之製品及製作其之方法
KR102320673B1 (ko) 2016-12-28 2021-11-01 인벤사스 본딩 테크놀로지스 인코포레이티드 적층된 기판의 처리
FR3063176A1 (fr) * 2017-02-17 2018-08-24 Soitec Masquage d'une zone au bord d'un substrat donneur lors d'une etape d'implantation ionique
TWI756384B (zh) * 2017-03-16 2022-03-01 美商康寧公司 用於大量轉移微型led的方法及製程
CN111372772A (zh) 2017-08-18 2020-07-03 康宁股份有限公司 使用聚阳离子聚合物的临时结合
KR102179165B1 (ko) 2017-11-28 2020-11-16 삼성전자주식회사 캐리어 기판 및 상기 캐리어 기판을 이용한 반도체 패키지의 제조방법
FR3074960B1 (fr) 2017-12-07 2019-12-06 Soitec Procede de transfert d'une couche utilisant une structure demontable
US11331692B2 (en) 2017-12-15 2022-05-17 Corning Incorporated Methods for treating a substrate and method for making articles comprising bonded sheets
KR20260047323A (ko) * 2018-03-14 2026-04-07 도쿄엘렉트론가부시키가이샤 기판 가공 장치 및 기판 가공 방법
TWI791099B (zh) * 2018-03-29 2023-02-01 日商日本碍子股份有限公司 接合體及彈性波元件
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11101158B1 (en) * 2018-08-08 2021-08-24 United States Of America As Represented By The Administrator Of Nasa Wafer-scale membrane release laminates, devices and processes
DE102019124181B4 (de) 2018-09-28 2023-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Vereinzelungsverfahren für gestapelte Halbleiter-Bauelemente sowie gestapelte Halbleitervorrichtung
US11081392B2 (en) * 2018-09-28 2021-08-03 Taiwan Semiconductor Manufacturing Co., Ltd. Dicing method for stacked semiconductor devices
JP2022553827A (ja) 2019-10-31 2022-12-26 イェール ユニバーシティー 多孔質ｉｉｉ族窒化物ならびにこれを使用および製造する方法
FR3108439B1 (fr) 2020-03-23 2022-02-11 Soitec Silicon On Insulator Procede de fabrication d’une structure empilee
FR3109016B1 (fr) 2020-04-01 2023-12-01 Soitec Silicon On Insulator Structure demontable et procede de transfert d’une couche mettant en œuvre ladite structure demontable
EP4315398A4 (en) 2021-03-31 2025-03-05 Adeia Semiconductor Bonding Technologies Inc. DIRECT ADHESION AND REMOVING A CARRIER
US20230025444A1 (en) * 2021-07-22 2023-01-26 Lawrence Livermore National Security, Llc Systems and methods for silicon microstructures fabricated via greyscale drie with soi release
CN114937649A (zh) * 2022-06-15 2022-08-23 北京青禾晶元半导体科技有限责任公司 一种半导体可拆卸基板结构、可拆卸方法和用途
CN115101705B (zh) * 2022-06-29 2025-01-03 深圳市华星光电半导体显示技术有限公司 显示面板及蒸镀装置

Family Cites Families (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4121334A (en) 1974-12-17 1978-10-24 P. R. Mallory & Co. Inc. Application of field-assisted bonding to the mass production of silicon type pressure transducers
JPS53104156A (en) 1977-02-23 1978-09-11 Hitachi Ltd Manufacture for semiconductor device
US4179324A (en) 1977-11-28 1979-12-18 Spire Corporation Process for fabricating thin film and glass sheet laminate
JPS5831519A (ja) 1981-08-18 1983-02-24 Toshiba Corp 半導体装置の製造方法
SU1282757A1 (ru) 1983-12-30 2000-06-27 Институт Ядерной Физики Ан Казсср Способ изготовления тонких пластин кремния
JPS62265717A (ja) 1986-05-13 1987-11-18 Nippon Telegr & Teleph Corp <Ntt> ガリウムひ素集積回路用基板の熱処理方法
GB8725497D0 (en) 1987-10-30 1987-12-02 Atomic Energy Authority Uk Isolation of silicon
JP2927277B2 (ja) 1988-12-05 1999-07-28 住友電気工業株式会社 車載ナビゲータ
JPH0355822A (ja) 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法
US5013681A (en) 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5310446A (en) 1990-01-10 1994-05-10 Ricoh Company, Ltd. Method for producing semiconductor film
US5034343A (en) 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
JPH0719739B2 (ja) 1990-09-10 1995-03-06 信越半導体株式会社 接合ウェーハの製造方法
US5618739A (en) 1990-11-15 1997-04-08 Seiko Instruments Inc. Method of making light valve device using semiconductive composite substrate
JPH04199504A (ja) 1990-11-28 1992-07-20 Mitsubishi Electric Corp 半導体装置の製造方法
JP2812405B2 (ja) 1991-03-15 1998-10-22 信越半導体株式会社 半導体基板の製造方法
US5256581A (en) 1991-08-28 1993-10-26 Motorola, Inc. Silicon film with improved thickness control
JP3416163B2 (ja) 1992-01-31 2003-06-16 キヤノン株式会社 半導体基板及びその作製方法
JPH05235312A (ja) 1992-02-19 1993-09-10 Fujitsu Ltd 半導体基板及びその製造方法
JP3352118B2 (ja) * 1992-08-25 2002-12-03 キヤノン株式会社 半導体装置及びその製造方法
US5234535A (en) 1992-12-10 1993-08-10 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
JPH07211876A (ja) * 1994-01-21 1995-08-11 Canon Inc 半導体基体の作成方法
FR2715501B1 (fr) 1994-01-26 1996-04-05 Commissariat Energie Atomique Procédé de dépôt de lames semiconductrices sur un support.
FR2715502B1 (fr) 1994-01-26 1996-04-05 Commissariat Energie Atomique Structure présentant des cavités et procédé de réalisation d'une telle structure.
FR2715503B1 (fr) 1994-01-26 1996-04-05 Commissariat Energie Atomique Substrat pour composants intégrés comportant une couche mince et son procédé de réalisation.
JP3293736B2 (ja) 1996-02-28 2002-06-17 キヤノン株式会社 半導体基板の作製方法および貼り合わせ基体
JP3352340B2 (ja) 1995-10-06 2002-12-03 キヤノン株式会社 半導体基体とその製造方法
JP3257580B2 (ja) 1994-03-10 2002-02-18 キヤノン株式会社 半導体基板の作製方法
JPH0817777A (ja) 1994-07-01 1996-01-19 Mitsubishi Materials Shilicon Corp シリコンウェーハの洗浄方法
JPH0851103A (ja) 1994-08-08 1996-02-20 Fuji Electric Co Ltd 薄膜の生成方法
US5567654A (en) 1994-09-28 1996-10-22 International Business Machines Corporation Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging
JPH08133878A (ja) * 1994-11-11 1996-05-28 Mitsubishi Materials Corp グレーズドセラミック基板の製造方法
EP0717437B1 (en) 1994-12-12 2002-04-24 Advanced Micro Devices, Inc. Method of forming buried oxide layers
JP3381443B2 (ja) 1995-02-02 2003-02-24 ソニー株式会社 基体から半導体層を分離する方法、半導体素子の製造方法およびｓｏｉ基板の製造方法
FR2744285B1 (fr) 1996-01-25 1998-03-06 Commissariat Energie Atomique Procede de transfert d'une couche mince d'un substrat initial sur un substrat final
FR2747506B1 (fr) 1996-04-11 1998-05-15 Commissariat Energie Atomique Procede d'obtention d'un film mince de materiau semiconducteur comprenant notamment des composants electroniques
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
FR2748850B1 (fr) 1996-05-15 1998-07-24 Commissariat Energie Atomique Procede de realisation d'un film mince de materiau solide et applications de ce procede
JP4001650B2 (ja) 1996-05-16 2007-10-31 株式会社リコー 画像形成装置
SG65697A1 (en) 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
US6054363A (en) 1996-11-15 2000-04-25 Canon Kabushiki Kaisha Method of manufacturing semiconductor article
DE19648501A1 (de) 1996-11-22 1998-05-28 Max Planck Gesellschaft Verfahren für die lösbare Verbindung und anschließende Trennung reversibel gebondeter und polierter Scheiben sowie eine Waferstruktur und Wafer
KR100232886B1 (ko) 1996-11-23 1999-12-01 김영환 Soi 웨이퍼 제조방법
DE19648759A1 (de) 1996-11-25 1998-05-28 Max Planck Gesellschaft Verfahren zur Herstellung von Mikrostrukturen sowie Mikrostruktur
JPH10163166A (ja) * 1996-11-28 1998-06-19 Mitsubishi Electric Corp 半導体装置の製造方法及び製造装置
FR2756847B1 (fr) * 1996-12-09 1999-01-08 Commissariat Energie Atomique Procede de separation d'au moins deux elements d'une structure en contact entre eux par implantation ionique
ATE261612T1 (de) 1996-12-18 2004-03-15 Canon Kk Vefahren zum herstellen eines halbleiterartikels unter verwendung eines substrates mit einer porösen halbleiterschicht
JP3962465B2 (ja) 1996-12-18 2007-08-22 キヤノン株式会社 半導体部材の製造方法
FR2758907B1 (fr) * 1997-01-27 1999-05-07 Commissariat Energie Atomique Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique
JP3114643B2 (ja) 1997-02-20 2000-12-04 日本電気株式会社 半導体基板の構造および製造方法
US6033974A (en) 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US6159824A (en) 1997-05-12 2000-12-12 Silicon Genesis Corporation Silicon-on-silicon wafer bonding process using a thin film blister-separation method
US5877070A (en) 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
WO1999001893A2 (de) 1997-06-30 1999-01-14 MAX-PLANCK-Gesellschaft zur Förderung der Wissenschaften e.V. Verfahren zur herstellung von schichtartigen gebilden auf einem substrat, substrat sowie mittels des verfahrens hergestellte halbleiterbauelemente
US6054369A (en) 1997-06-30 2000-04-25 Intersil Corporation Lifetime control for semiconductor devices
US6534380B1 (en) 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JPH1145862A (ja) 1997-07-24 1999-02-16 Denso Corp 半導体基板の製造方法
US6103599A (en) 1997-07-25 2000-08-15 Silicon Genesis Corporation Planarizing technique for multilayered substrates
FR2767416B1 (fr) 1997-08-12 1999-10-01 Commissariat Energie Atomique Procede de fabrication d'un film mince de materiau solide
FR2767604B1 (fr) * 1997-08-19 2000-12-01 Commissariat Energie Atomique Procede de traitement pour le collage moleculaire et le decollage de deux structures
JPH1174208A (ja) 1997-08-27 1999-03-16 Denso Corp 半導体基板の製造方法
JP3412470B2 (ja) 1997-09-04 2003-06-03 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
US5981400A (en) 1997-09-18 1999-11-09 Cornell Research Foundation, Inc. Compliant universal substrate for epitaxial growth
JP2998724B2 (ja) 1997-11-10 2000-01-11 日本電気株式会社 張り合わせｓｏｉ基板の製造方法
FR2771852B1 (fr) 1997-12-02 1999-12-31 Commissariat Energie Atomique Procede de transfert selectif d'une microstructure, formee sur un substrat initial, vers un substrat final
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2774510B1 (fr) 1998-02-02 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats, notamment semi-conducteurs
JP3031904B2 (ja) * 1998-02-18 2000-04-10 キヤノン株式会社 複合部材とその分離方法、及びそれを利用した半導体基体の製造方法
MY118019A (en) * 1998-02-18 2004-08-30 Canon Kk Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof
JP3809733B2 (ja) 1998-02-25 2006-08-16 セイコーエプソン株式会社 薄膜トランジスタの剥離方法
US6057212A (en) 1998-05-04 2000-05-02 International Business Machines Corporation Method for making bonded metal back-plane substrates
US6054370A (en) * 1998-06-30 2000-04-25 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
US6271101B1 (en) 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US6118181A (en) 1998-07-29 2000-09-12 Agilent Technologies, Inc. System and method for bonding wafers
FR2781925B1 (fr) 1998-07-30 2001-11-23 Commissariat Energie Atomique Transfert selectif d'elements d'un support vers un autre support
EP0989593A3 (en) 1998-09-25 2002-01-02 Canon Kabushiki Kaisha Substrate separating apparatus and method, and substrate manufacturing method
FR2784795B1 (fr) 1998-10-16 2000-12-01 Commissariat Energie Atomique Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure
FR2789518B1 (fr) 1999-02-10 2003-06-20 Commissariat Energie Atomique Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure
AU4481100A (en) 1999-04-21 2000-11-02 Silicon Genesis Corporation Treatment method of cleaved film for the manufacture of substrates
JP2001015721A (ja) 1999-04-30 2001-01-19 Canon Inc 複合部材の分離方法及び薄膜の製造方法
US6664169B1 (en) 1999-06-08 2003-12-16 Canon Kabushiki Kaisha Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus
US6362082B1 (en) * 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
FR2796491B1 (fr) * 1999-07-12 2001-08-31 Commissariat Energie Atomique Procede de decollement de deux elements et dispositif pour sa mise en oeuvre
EP1939932A1 (en) 1999-08-10 2008-07-02 Silicon Genesis Corporation A substrate comprising a stressed silicon germanium cleave layer
DE19958803C1 (de) 1999-12-07 2001-08-30 Fraunhofer Ges Forschung Verfahren und Vorrichtung zum Handhaben von Halbleitersubstraten bei der Prozessierung und/oder Bearbeitung
FR2811807B1 (fr) 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
FR2818010B1 (fr) 2000-12-08 2003-09-05 Commissariat Energie Atomique Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses
US6774010B2 (en) 2001-01-25 2004-08-10 International Business Machines Corporation Transferable device-containing layer for silicon-on-insulator applications
FR2823373B1 (fr) 2001-04-10 2005-02-04 Soitec Silicon On Insulator Dispositif de coupe de couche d'un substrat, et procede associe
FR2823596B1 (fr) 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
US6759282B2 (en) 2001-06-12 2004-07-06 International Business Machines Corporation Method and structure for buried circuits and devices
US6645831B1 (en) 2002-05-07 2003-11-11 Intel Corporation Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide
US7535100B2 (en) 2002-07-12 2009-05-19 The United States Of America As Represented By The Secretary Of The Navy Wafer bonding of thinned electronic materials and circuits to high performance substrates
JP4199504B2 (ja) 2002-09-24 2008-12-17 イーグル工業株式会社 摺動部品及びその製造方法
US7071077B2 (en) 2003-03-26 2006-07-04 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for preparing a bonding surface of a semiconductor layer of a wafer
FR2855910B1 (fr) 2003-06-06 2005-07-15 Commissariat Energie Atomique Procede d'obtention d'une couche tres mince par amincissement par auto-portage provoque
FR2876220B1 (fr) 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
FR2876219B1 (fr) 2004-10-06 2006-11-24 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.

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TW577102B (en) 2004-02-21
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FR2823596A1 (fr) 2002-10-18
FR2823596B1 (fr) 2004-08-20
US7713369B2 (en) 2010-05-11
EP1378003A2 (fr) 2004-01-07
AU2002304525A1 (en) 2002-10-28
JP2010114456A (ja) 2010-05-20
EP1378003B1 (fr) 2017-11-08
KR100933897B1 (ko) 2009-12-28
WO2002084721A2 (fr) 2002-10-24
KR20040000425A (ko) 2004-01-03
WO2002084721A3 (fr) 2003-11-06

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