JP4433588B2 - BS digital broadcast demodulation / decoding device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a BS digital broadcast demodulation / decoding device for demodulating and decoding a broadcast wave of BS digital broadcast.
[0002]
[Prior art]
In Japan, digital satellite broadcasting (BS digital broadcasting) is scheduled to start by the end of 2000. This BS digital broadcasting is a very complicated transmission method compared to conventional digital broadcasting (for example, CS digital broadcasting). For example, transmission data is broadcast while dynamically switching between a plurality of modulation schemes (BPSK, QPSK, TC8PSK), or transmission data is broadcast while dynamically switching between a plurality of convolutional coding schemes. In addition, a maximum of eight transport streams (TS) defined in the MPEG2 SYSTEMS can be multiplexed and transmitted. For this reason, in BS digital broadcasting, a data structure called a super frame is defined, and the transmission rate of data and the modulation method and coding method that are dynamically switched are managed in units of the super frame.
[0003]
In BS digital broadcasting, all information regarding such a superframe configuration is described in TMCC (Transmission Multiplexing Configuration Control) information and broadcasted. This TMCC information describes the modulation / coding scheme of each slot, the number of the transport stream assigned to each slot constituting each super frame, and the like. In the TMCC information, one information unit is composed of 48 bytes, and one TMCC information is added to one superframe.
[0004]
Further, it is defined that this TMCC information is applied as superframe transmission control information after two superframes. Therefore, each module (for example, demodulator, inner code decoder (depuncture circuit, branch) constituting a demodulation / decoding device (that is, a device that demodulates an RF signal and outputs a TS)) that demodulates and decodes BS digital broadcasting. Metric generation circuit, Viterbi decoder), deinterleaver, RS decoder, TS output circuit, etc.) need to perform processing on the current superframe while referring to TMCC information two superframes before being decoded. is there.
[0005]
For this reason, a TMCC decoder that decodes TMCC information in parallel with the TS output circuit is usually provided at the final stage of the BS digital broadcast demodulating / decoding device. It is distributed to each module in time for this process.
[0006]
[Problems to be solved by the invention]
By the way, the fact that TMCC information is reflected in the superframe after 2 superframes means that each module constituting the BS digital broadcast demodulating / decoding device has been newly received using TMCC information that has already been decoded. The transmission data is demodulated / decoded. Therefore, unless TMCC information is correctly decoded, transmission data cannot be demodulated or decoded normally.
[0007]
Therefore, for example, when performing operation verification of a demodulation / decoding device (or demodulation / decoding IC), it is possible to specify which module has a bug or what the bug is. It becomes very difficult.
[0008]
For example, it is assumed that only one bug is mixed in a certain module constituting the demodulation / decoding device, and TMCC information cannot be correctly decoded due to the bug. In this case, since this incorrect TMCC information is distributed to each module, each module to which TMCC information is distributed cannot obtain a correct output result. That is, even if the module does not have a bug and operates normally as designed, incorrect TMCC information is distributed to the module, and thus erroneous data is output.
[0009]
Conventionally, in order to avoid such problems, TMCC information for test mode is preset in the apparatus, and operation verification is performed using the preset TMCC information. That is, each module is operated by TMCC information in which a predetermined parameter is described without using TMCC information obtained as a result of decoding.
[0010]
However, as described above, the structure of transmission data of BS digital broadcasting is very complicated, and the number of parameters set in the TMCC information also increases accordingly.
[0011]
In verifying each module, the optimum parameter for each module differs for each module. For example, the optimal parameter for verifying the Viterbi decoder is preferably set to a modulation scheme that does not use a parallel path, that is, BPSK or QPSK instead of TC8PSK. On the other hand, for example, the optimum parameter for verifying the deinterleaver is desirably set to a modulation scheme not including a dummy slot, that is, TC8PSK.
[0012]
As described above, it is difficult to preset the TMCC information set to the optimum parameter setting for each module. In other words, if TMCC information in which optimum parameters are set is preset for every module, the memory capacity for presetting becomes very large and the cost increases. On the other hand, if a minimum number of TMCC information is preset, verification becomes difficult and the cost is increased.
[0013]
The present invention has been made in view of such a situation as described above, and provides a BS digital broadcast demodulation / decoding device capable of efficiently performing design verification and efficiently performing demodulation / decoding operations. For the purpose.
[0014]
[Means for Solving the Problems]
A BS digital broadcast demodulating / decoding device according to the present invention receives a BS digital broadcast broadcast wave and demodulates transmission data, and decodes BS digital broadcast transmission data demodulated by the demodulation unit and transports the demodulated data. A decoding unit that outputs stream (TS) and TMCC (Transmission Multiplexing Configuration Control) information, and a TMCC control unit that controls the demodulation unit and the decoding unit based on TMCC information. An external TMCC mode that has an input port and performs control based on TMCC information input from the outside and an internal TMCC mode that performs control based on TMCC information output from the decoding unit can be set from the outside. Switching is based on this.
[0015]
In this BS digital broadcast demodulation / decoding device, an external TMCC mode that performs control based on TMCC information input from the outside and an internal TMCC mode that performs control based on the TMCC information output from the decoding unit are externally transmitted. Switch based on the setting.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a BS digital broadcast demodulation / decoding device to which the present invention is applied will be described as an embodiment of the present invention.
[0017]
FIG. 1 shows a configuration diagram of a BS digital broadcast demodulation / decoding device according to an embodiment of the present invention.
[0018]
The BS digital broadcast demodulation / decoding device 1 includes a demodulation unit 11, a decoding unit 12, and a TMCC control unit 13, as shown in FIG.
[0019]
The demodulator 11 receives an RF signal obtained by receiving with the parabolic antenna 2. The demodulator 11 multiplies the RF signal by the carrier wave signal and demodulates the I signal and the Q signal, which are orthogonal modulation signals. Then, I signal data and Q signal data obtained by encoding the demodulated I signal and Q signal are generated. The I signal data and the Q signal data are sent to the decoding unit 12.
[0020]
The decoding unit 12 includes an inner code decoder, a deinterleaver, an inverse energy spreading circuit, a frame configuration circuit, an RS decoding circuit, a TS output circuit, an inverse energy spreading circuit for TMCC, an RS decoding circuit for TMCC, and the like. Yes.
[0021]
The inner code decoder performs depuncturing processing and Viterbi decoding according to the modulation scheme and inner code coding rate of each symbol. The modulation scheme and the inner code coding rate are given by the TMCC information from the TMCC control unit 13.
[0022]
The deinterleaver deinterleaves transmission data in units of superframes.
[0023]
The inverse energy spreading circuit performs an inverse energy spreading process using a 15th order pseudo-random sequence (PRBS).
[0024]
The frame reconstruction circuit performs processing for adding a synchronization signal (0x47) of a TS packet deleted during transmission, insertion of a so-called dummy slot, and the like. The insertion position and the like of the dummy slot are specified based on the TMCC information from the TMCC control unit 13.
[0025]
The RS decoding circuit performs Reed-Solomon decoding of RS (204, 188) in units of transmission packets of 204 bytes.
[0026]
The TS output circuit selects one TS from the multiplexed TS, smooths this TS, and outputs it. The slot position where each TS is stored is specified based on the TMCC information from the TMCC control unit 13.
[0027]
The TMCC inverse energy spread processing circuit performs inverse energy spread on TMCC data divided and transmitted in a superframe using a ninth-order pseudo-random sequence (PRBS).
[0028]
The RS decoding circuit for TMCC performs RS (64, 48) Reed-Solomon decoding of 64 bytes of TMCC data, and as a result, outputs 48 bytes of TMCC information.
[0029]
The TS decoded by the decoding unit 12 is supplied to, for example, an MPEG decoder provided at the subsequent stage of the present apparatus. The TMCC information decoded by the decoding unit 12 is supplied to the TMCC control unit 13.
[0030]
TMCC information is input to the TMCC control unit 13 from the decoding unit 12 or from the outside of the apparatus. The TMCC information input from the decoding unit 12 is TMCC information included in each superframe of transmission data. The TMCC information input from the decoding unit 12 is hereinafter referred to as internal TMCC information. The TMCC information input from the outside of the apparatus is TMCC information in which parameters are arbitrarily set by the user. This TMCC information input from outside is hereinafter referred to as external TMCC information.
[0031]
The TMCC control unit 13 switches between external TMCC information and internal TMCC information according to the setting by the external device, and distributes either one of the TMCC information to each module in the demodulation unit 11 and the decoding unit 12. The setting for selecting external TMCC information is referred to as an external TMCC mode, and the setting for selecting internal TMCC information is referred to as an internal TMCC mode.
[0032]
In the case of the internal TMCC mode, the TMCC control unit 13 can also send internal TMCC information to the outside according to the setting from the external device.
[0033]
The TMCC control unit 13 uses a dedicated port for data input / output or a general-purpose port for an interface used for exchanging data such as TMCC information with an external device. For example, select whether to use a general-purpose port or a dedicated port from the viewpoint of whether the external device of the connection destination also has a general-purpose port as an interface and whether there is room to lay out the dedicated port on the board. Design.
[0034]
In this embodiment, as an example, I ² An example using a general-purpose port C will be described.
[0035]
I ² C is a bus that connects ICs mounted on home appliances and communication devices, and is generally widely used. I ² In general, when the devices are controlled using C, the following method is used. On the controlled device side, items that can be set / monitored externally are ² Mapping is performed in advance on the C address space. The controller side issues a write / read command to the address space. As a result, the control device can set / monitor the controlled device.
[0036]
For example, as shown in FIG. 2, the TMCC control unit 13 sets an address space of 0x00 to 0xff. The TMCC control unit 13 assigns 1 bit (for example, the bit indicated by A in FIG. 2) in this address space as the mode setting address of the TMCC information write mode. Then, the external device is set to the internal TMCC mode by writing “1” to this mode setting address, and is set to the external TMCC mode by writing “0”. Also, the TMCC control unit 13 assigns 48 bytes in this address space (for example, the area indicated by B in FIG. 2) as an address for designation / monitoring of TMCC information. When the internal TMCC mode is set, the internal TMCC information can be monitored from the designated / monitor address space. When the external TMCC mode is set, the designated / monitor address space is TMCC information can be specified. Further, the other address spaces (areas indicated by hatching in FIG. 2) are address areas in which control not directly related to the exchange of TMCC information is performed.
[0037]
The TMCC control unit 13 can exchange TMCC information with an external device by using the general-purpose port as described above.
[0038]
Next, a specific circuit configuration of the TMCC control unit 13 will be further described with reference to FIG.
[0039]
As shown in FIG. ² CI / F circuit 21, internal memory 22, flag F generation circuit 23, first to third AND circuits 24 to 26, first selector 27, second selector 28, OR circuit 29, , First to fourth registers 31 to 34, and a third selector 35 are provided.
[0040]
I ² The CI / F circuit 21 connects the TMCC control unit 13 and an external device. ² C bus interface circuit. I ² The CI / F circuit 21 ² A command issued from an external device via the C bus is decoded to write data (WDT), write address (WADR), read address (RADR), flag set command (FSET), flag reset command (FRST), write A request (WREQ) and a read request (RREQ) are output. I ² The CI / F circuit 21 receives read data (RDT) and a read enable signal (REN) and sends them to an external device.
[0041]
The write data (WDT) is data input to the TMCC control unit 13 from an external device. ² This is data written to the designated / monitoring address (area indicated by B in FIG. 2) in the C address space. Specifically, external TMCC information is transmitted as the write data (WDT). The external TMCC information is 48 bytes of data in total, but is serialized for each byte, and I ² Output from the CI / F circuit 21.
[0042]
Read data (RDT) is data output from the TMCC control unit 13 to an external device. ² This is data to be written to the designated / monitoring address (area indicated by B in FIG. 2) in the C address space. Specifically, internal TMCC information or external TMCC information is transmitted as the write data (RDT). The external TMCC information and the internal TMCC information are 48-byte data in total. ² Input to the CI / F circuit 21.
[0043]
The write address (WADR) is an address designated for writing external TMCC information or internal TMCC information to the internal memory 22. A value from a counter that counts from 0 to 47 is transmitted as the write address (WADR). This counter is reset every superframe. By specifying the address of the write data (WDT) using such a counter, 48 bytes of serialized external TMCC information or internal TMCC information can be written to the internal memory 22 byte by byte.
[0044]
The read address (RADR) is an address designated for reading internal TMCC information (or external TMCC information) from the internal memory 22. As the read address (RADR), a value from a counter that counts from 0 to 47 is transmitted. This counter is reset every superframe. By specifying an address of read data (RDT) using such a counter, 48 bytes of serialized internal TMCC information (or external TMCC information) can be read from the internal memory 22 byte by byte.
[0045]
The flag set instruction (FSET) and the flag reset instruction (FRST) are instructions for setting a flag F that designates the external TMCC mode and the internal TMCC mode. The flag F designates the internal TMCC mode when the value is 1, and designates the external TMCC mode when the value is 0. I ² The CI / F circuit 21 ² If 1 is written to the mode setting address (bit A in FIG. 2) in the C address space, a flag set instruction (FSET) is issued to set the flag F to 1, and 0 is written. For example, a flag reset instruction (FRST) is issued to set the flag F to zero.
[0046]
The write request (WREQ) is a signal indicating a write request for writing the external TMCC information or the internal TMCC information to the internal memory 22, and is 1 when there is a write request and 0 when there is no write request.
[0047]
The read request (RREQ) is a signal indicating a read request for reading internal TMCC information or external TMCC information from the internal memory 22, and is 1 when there is a read request and 0 when there is no read request.
[0048]
The read enable signal (REN) is 1 when the internal TMCC information or the external TMCC information can be read from the internal memory 22, and is 0 when the read is impossible.
[0049]
Further, the internal data (IMTDT), the internal address (TMTADR), and the internal enable signal (IMTEN) are input to the TMCC control unit 13 from the decoding unit 12.
[0050]
The internal data (IMTDT) is data input from the decoding unit 12 to the TMCC control unit 13, and specifically is 48-bit internal TMCC information. The internal TMCC information is 48-byte data in total, but is serialized for each byte and input from the decoding unit 12.
[0051]
The internal address (IMTADR) is an address that designates a data byte of internal TMCC information input from the decoding unit 12. As this internal address (IMTADR), a value from a counter that counts from 0 to 47 is transmitted. This counter is reset every superframe. By specifying the address of the internal data (IMTDT) using such a counter, 48 bytes of serialized internal TMCC information can be input byte by byte.
[0052]
The internal enable signal (IMTEN) is information indicating the validity of the internal data (IMTDT).
[0053]
The internal memory 22 is a memory for storing internal TMCC information or external TMCC information. When the write enable signal input to the write enable terminal (WE) is set to 0, the internal memory 22 transmits data specified by the address input to the address terminal (ADR) from the data output terminal (ODT). Output. Data output from the data output terminal (ODT) is read data (RDT) as I ² It is supplied to the CI / F circuit 21 or supplied to the third selector 35 as TMCC information to be output. Further, when the write enable signal input to the write enable terminal (WE) is 1, the internal memory 22 is input to the data input terminal (IDT) at the address specified from the address terminal (ADR). Store the data.
[0054]
The flag F generation circuit 23 is a circuit that generates a flag F that designates an external TMCC mode and an external TMCC mode. The flag F generation circuit 23 sets the flag F to 1 when a flag set instruction (FSET) is input, and sets the flag F to 0 when a flag reset instruction (FRST) is input.
[0055]
The first AND circuit 24 performs an AND operation on the flag F and the internal enable signal (IMTEN). The first AND circuit 24 outputs the AND operation result as an internal write enable signal iwen. This internal write enable signal iwen is supplied to the OR circuit 29 and the second register 32.
[0056]
The second AND circuit 25 performs an AND operation on the inverted signal of the flag F and the write request (WREQ). The second AND circuit 25 outputs the AND operation result as a write external write enable signal wen. The external write enable signal wen is supplied to the OR circuit 29.
[0057]
The OR circuit 29 performs an OR operation between the internal write enable signal iwen and the external write enable signal wen. The OR circuit 29 supplies the OR operation result to the write enable terminal (WE) of the internal memory 22 as the write enable signal WE. The OR operation result is stored in the third register 33.
[0058]
The third AND circuit 26 performs an AND operation on the inverted signal of the internal enable signal (IMTEN) and the read request (RREQ). The third AND circuit 26 reads out the AND operation result and outputs it as an enable signal ren. This read enable signal ren is supplied to the fourth register 34.
[0059]
The first selector 27 outputs I according to the outputs of the first to third AND circuits 24-26. ² Either the address (read address RADR or write address WADR) output from the CI / F circuit 21 or the internal address (IMTADR) output from the decoding unit 12 is selected and output. The address selected by the first selector 27 is supplied to the address terminal (ADR) of the internal memory 22.
[0060]
The second selector 28 selects I according to the outputs of the first to third AND circuits 24-26. ² Either write data (WDT: external TMCC information) output from the CI / F circuit 21 or internal data (IMTDT: internal TMCC information) output from the decoding unit 12 is selected and output. The data selected by the second selector 28 is supplied to the data input terminal (IDT) of the internal memory 22 and the first register 31.
[0061]
The first register 31 adjusts the timing of the external TMCC information or the internal TMCC information selected by the second selector 28 and supplies it to the third selector 35.
[0062]
The second register 32 stores the internal write enable signal iwen output from the first AND circuit 24.
[0063]
The third selector 35 performs switching control according to the internal write enable signal iwen stored in the second register 32. When the internal write enable signal iwen is 1, the first register 31 is selected. When the internal write enable signal iwen is 0, the internal memory 22 is selected and the data stored in the internal memory 22 is output as output data (OTMCDT).
[0064]
The third register 33 stores a write enable signal WE for the internal memory 22, which is the operation result of the OR circuit 29. The third register 33 outputs the write enable signal WE as an enable signal for output data (OTMCDT) to be output.
[0065]
The fourth register 34 adjusts the timing of the read enable signal ren output from the third AND circuit 26. As the fourth register 34, the read enable signal (REN), I ² This is supplied to the CI / F circuit 21.
[0066]
The third selector 35 follows the internal write enable signal (iwen) stored in the second register 32 and the TMCC information stored in the internal memory 22 and the TMCC information stored in the first register 31. Either one of them is selected and output. When the internal write enable signal iwen is 0, the TMCC information output from the data output terminal (ODT) of the internal memory 22 is selected. When the internal write enable signal iwen is 1, the first register 31 is selected. Select stored TMCC information. The selected TMCC information is supplied from the TMCC control unit 13 to each module of the demodulation unit 11 and the decoding unit 12.
[0067]
Next, the operation of the TMCC control unit 13 will be described.
[0068]
I ² If there is a request to read TMCC information from an external device via the C bus, I ² The CI / F circuit 21 decodes the request and outputs a read address (RADR) and a read request (RREQ).
[0069]
At this time, if the internal TMCC information or the external TMCC information is being written to the internal memory 22, the TMCC control unit 13 sets the read enable signal (REN) to 0, ² Input to the CI / F circuit 21. I ² If the read enable signal (REN) is 0, the CI / F circuit 21 ² Notifies the external device that reading has failed via the C bus.
[0070]
If the internal TMCC information or the external TMCC information is not being written to the internal memory 22, the TMCC control unit 13 reads the byte specified by the read address (RADR) from the data stored in the internal memory 22. ) As I ² Input to the CI / F circuit 21. At the same time, the TMCC control unit 13 sets the read enable signal (REN) to 1, ² Input to the CI / F circuit 21. I ² If the read enable signal (REN) is 1, the CI / F circuit 21 ² Read data (RDT) input via the C bus is sent to an external device.
[0071]
I ² If there is a request to write TMCC information from an external device via the C bus, ² The CI / F circuit 21 decodes the request and outputs a write address (RADR), a write request (RREQ), and write data (WDT).
[0072]
At this time, if the value of the flag F is 1, the TMCC control unit 13 ignores the write request. At this time, if the value of the flag F is 0, the TMCC control unit 13 writes the write data (WDT) to the address on the internal memory 22 designated by the write address (WADR).
[0073]
When the internal data (ITMDT), the internal address (IMTADR), and the internal enable signal (IMTEN) are input from the decoding unit 12, if the flag F is 1, the internal specified by the internal address (IMTADR) The internal data (ITMDT) is written to the address on the memory 22, and the same data as the data written to the internal memory 22 is output as output data (OTMCDT). If the flag F is 0, the data stored at the address on the internal memory 22 specified by the internal address (IMTADR) is read at the same timing as when the flag F is 1, and the output data ( OTMCDT) is output.
[0074]
By processing in this way, each module in the apparatus can operate without being conscious of whether it is internal TMCC information or external TMCC information.
[0075]
In the BS digital broadcast demodulation / decoding device 1 as described above, an external TMCC mode that performs control based on TMCC information input from the outside and an internal TMCC mode that performs control based on the TMCC information output from the decoding section Switching based on external settings.
[0076]
For this reason, in the BS digital broadcast demodulation / decoding device 1, any TMCC information can be given from the outside to each module in the verification process, and parameters for verifying each module are set to the optimum setting from the outside. Can do. Therefore, bugs in each module can be found efficiently.
[0077]
Further, if the control can be performed based on the TMCC information input from the outside as described above, not only the verification of the apparatus but also the following can be performed.
[0078]
For example, in the case of BS digital broadcasting, TMCC information of other channels may be transmitted in PSI / SI (Program Specific Information / Service Information) information such as NIT (Network Information Table) included in the transport stream. Is possible. In such a case, if TMCC information of other channels described in PSI / SI is acquired in advance by a TS decoder or the like, TMCC information is not acquired again after the channel change, but at the same time as the channel change. TMCC information can be provided.
[0079]
Thus, if TMCC information can be given to the demodulation / decoding unit from the outside simultaneously with the channel change, the demodulation of the main signal can be started without decoding the TMCC information included in the broadcast signal. Therefore, the time from when the channel is changed to when TMCC information is newly decoded and the demodulation of the main signal is started (takes more than two superframes) is shortened. It is possible to shorten the switching time until the output of.
[0080]
【The invention's effect】
In the BS digital broadcast demodulation / decoding device according to the present invention, an external TMCC mode that performs control based on TMCC information input from outside, and an internal TMCC mode that performs control based on TMCC information output from the decoding unit, Switch based on external settings.
[0081]
For this reason, in this BS digital broadcast demodulation / decoding device, arbitrary TMCC information can be given to each module from the outside in the verification process, and parameters for verifying each module can be set to the optimum setting from the outside. it can. Therefore, bugs in each module can be found efficiently.
[0082]
Further, in this BS digital broadcast demodulation / decoding device, demodulation / decoding can be performed based on TMCC information designated in advance by the outside, so that demodulation / decoding can be performed efficiently. For example, when program switching or channel switching is performed, the timing for starting demodulation of the main signal can be shortened.
[Brief description of the drawings]
FIG. 1 is a block configuration diagram of a BS digital broadcast demodulation / decoding device according to an embodiment of the present invention.
FIG. 2 ² It is a figure for demonstrating the address space of a C bus interface.
FIG. 3 is a circuit diagram of a TMCC control unit of the BS digital broadcast demodulation / decoding device.
[Explanation of symbols]
1 BS digital broadcast demodulation / decoding device, 11 demodulation unit, 12 decoding unit, 13 TMCC control unit

Claims (3)

A demodulator that demodulates transmission data by receiving a broadcast wave of BS digital broadcasting;
A decoding unit that decodes transmission data of the BS digital broadcast demodulated by the demodulation unit and outputs transport stream (TS) and TMCC (Transmission Multiplexing Configuration Control) information;
A TMCC control unit for controlling the demodulation unit and the decoding unit based on TMCC information,
The TMCC control unit has a port to which TMCC information is input from the outside, an external TMCC mode that performs control based on the TMCC information input from the outside, and an internal that performs control based on the TMCC information output from the decoding unit A BS digital broadcast demodulation / decoding device that switches between TMCC modes based on an external setting. The said TMCC control part outputs TMCC information output from the said decoding part to the outside via the said port according to the setting from the outside in the case of internal TMCC mode. BS digital broadcast demodulation / decoding device. 2. The BS digital broadcast demodulating / decoding apparatus according to claim 1, wherein the TMCC control unit receives TMCC information from outside in an external TMCC mode when a program is changed.

Images