JP4429300B2 - Manufacturing method of electronic device material - Google Patents

Manufacturing method of electronic device material Download PDF

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JP4429300B2
JP4429300B2 JP2006239558A JP2006239558A JP4429300B2 JP 4429300 B2 JP4429300 B2 JP 4429300B2 JP 2006239558 A JP2006239558 A JP 2006239558A JP 2006239558 A JP2006239558 A JP 2006239558A JP 4429300 B2 JP4429300 B2 JP 4429300B2
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gas
plasma
insulating film
film
sccm
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JP2007027777A (en
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敏雄 中西
吉秀 多田
成則 尾▲崎▼
惠美 村川
征嗣 松山
卓也 菅原
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東京エレクトロン株式会社
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Description

  The present invention relates to a manufacturing method suitable for manufacturing semiconductor or electronic device materials. The method for producing an electronic device material of the present invention can be suitably used for forming, for example, a MOS type semiconductor structure.

  Conventionally, when forming a plurality of layers constituting a semiconductor or a semiconductor material, various layer forming techniques have been used. Typical examples of these layer forming techniques include vacuum deposition, sputtering, and CVD (chemical vapor deposition). Among these layer formation technologies, the CVD method has a feature that the film formation speed of the layer formation is high and the film can be formed in a relatively short time. Therefore, various semiconductor or electronic device materials including MOS type semiconductor devices are used. Is used in many processes.

  The manufacturing method of the present invention can be generally widely used for manufacturing electronic device materials. Here, for convenience of explanation, an EPROM which is an aspect of a nonvolatile memory called a flash memory is taken as an example here. Next, the technology as the background of the present invention will be described.

  The EPROM has a multilayer structure as shown in FIG. 12, for example.

Referring to FIG. 12, in this EPROM multilayer structure, an insulating layer 101 made of SiO 2 and semiconductor layers 102 and 103 made of polycrystalline silicon are formed in a predetermined pattern on a substrate 100 to be processed made of p-type single crystal silicon. And a metal layer 104 made of a metal (aluminum, copper, etc.) deposited thereon.

In such a semiconductor device, the above-described CVD method is widely used to form semiconductor layers 102 and 103 made of polycrystalline silicon and an interlayer SiO 2 layer.

  However, a layer formed by the CVD method has relatively many surface roughnesses and defects in the film, and there is a tendency that atomic bonds called dangling bonds are formed in the film. If this dangling bond is formed in the film, it affects the flow of electrons in this layer and in the adjacent layer, and the electrical characteristics of the layer are deteriorated. The problem of degradation can arise.

  The objective of this invention is providing the manufacturing method of the electronic device material which can solve the above-mentioned conventional problem.

  Another object of the present invention is to provide a manufacturing method capable of improving the electrical characteristics of layers constituting an electronic device (for example, a semiconductor) and manufacturing an electronic device of excellent quality.

  Still another object of the present invention is to provide a method for producing a high-quality electronic device material (for example, a MOS type semiconductor) provided with an insulating layer or a semiconductor layer having excellent electrical characteristics.

  The method for producing an electronic device material according to the present invention is based on microwave irradiation via a planar antenna member having a plurality of slots on a substrate to be processed that includes at least an electronic device substrate and an insulating film disposed on the substrate. The method includes a step of modifying the insulating film by exposure to plasma generated from a processing gas.

According to the present invention, the electronic device substrate, the first SiO 2 film disposed on the substrate, the first polycrystalline silicon layer disposed on the first SiO 2 film, A substrate to be processed including at least a second SiO 2 film disposed on one polycrystalline silicon layer is exposed to plasma generated from a processing gas based on microwave irradiation through a planar antenna member having a plurality of slots; An electronic device material manufacturing method including a step of modifying the second SiO 2 film is provided.

  According to the present invention, the substrate to be processed further including at least an electronic device substrate and an insulating film disposed on the substrate is irradiated with the processing gas through the planar antenna member having a plurality of slots. There is provided a method of manufacturing an electronic device material, which includes a step of exposing to the plasma generated thereby, modifying the insulating film using the plasma, and forming a metal layer on the insulating film.

As described above, according to the present invention, a method using a so-called SPA antenna, in which an insulating film disposed on an electronic device substrate is irradiated with microwaves via a planar antenna member (SPA) having a plurality of slots. Thus, plasma can be directly supplied onto the silicon substrate to modify the insulating film (eg, SiO 2 film). Therefore, dangling bonds in the surface of the insulating film or in the film can be terminated in a suitable manner without damaging the insulating film itself, and a high-quality insulating film, and thus a high-quality electronic device (for example, a semiconductor device) can be obtained. Obtainable.

  Hereinafter, the present invention will be described in detail with reference to the drawings as necessary. In the following description, “parts” and “%” representing the quantity ratio are based on mass unless otherwise specified.

(Method for manufacturing electronic device material)
In the method for manufacturing an electronic device material according to the present invention, a substrate to be processed including at least a layer of an electronic device material and an insulating film disposed on the layer is irradiated with microwaves via a planar antenna member having a plurality of slots. And at least a step of modifying the insulating film by exposing it to plasma generated from a processing gas.

(Materials for electronic devices)
The electronic device material that can be used in the present invention is not particularly limited, and can be appropriately selected from one or a combination of two or more known electronic device materials. Examples of such electronic device materials include semiconductor materials and liquid crystal device materials. Examples of the semiconductor material include a material containing silicon as a main component (single crystal silicon, polysilicon, amorphous silicon, etc.), a material containing a silicon nitride film as a main component, and a material containing silicon germanium as a main component.

(Insulating film)
The insulating film disposed on the layer of the electronic device material is not particularly limited, and can be appropriately selected from one or a combination of two or more known electronic device insulating films. Examples of such an insulating film include a silicon oxide film (SiO 2 ) and a silicon nitride film (SiN). The silicon oxide film is preferably a film formed by CVD from the viewpoint of thermal history and productivity.

(Processing gas)
The processing gas that can be used in the present invention is not particularly limited, and can be appropriately selected from one or a combination of two or more known processing gases that can be used for electronic device manufacturing. Examples of such a processing gas include a mixed gas containing a rare gas and oxygen (O 2 ) or a rare gas, nitrogen (N 2 ), and hydrogen (H 2 ).

(Rare gas)
The rare gas that can be used in the present invention is not particularly limited, and can be appropriately selected from one or a combination of two or more known rare gases that can be used for electronic device manufacturing. Examples of such process gases include krypton (Kr), xenon (Xe), helium (He), or argon (Ar).

  In the insulating film modification of the present invention, the following modification conditions can be preferably used from the viewpoint of the characteristics of the modified film to be formed.

O 2 : 1-1000 sccm, more preferably 10-500 sccm
Noble gas (for example, Kr, Ar, He or Xe): 200 to 3000 sccm, more preferably 500 to 2000 sccm,
H 2 : 1 to 200 sccm, more preferably 1 to 50 sccm,

Temperature: room temperature (25 ° C.) to 700 ° C., more preferably room temperature to 500 ° C.
Pressure: 20 to 5000 mTorr, more preferably 20 to 3000 mTorr, particularly preferably 50 to 2000 mTorr
Microwave: 0.5 to 5 W / cm 2 , more preferably 1 to 4 W / cm 2

(Example of suitable conditions)
In the production method of the present invention, the following conditions can be given as preferable examples from the viewpoint of the characteristics of the modification to be formed.
A suitable example of the processing gas: O 2 or N 2 having a flow rate of 10 to 500 sccm and a gas containing Kr, He, Xe, or Ar having a flow rate of 500 to 2000 sccm.
A suitable example of the processing conditions for the SiO 2 film: room temperature to 500 ° C.

A suitable example of processing conditions for the SiO 2 film: 2.7 to 270 Pa (20 to 2000 mTorr)
A suitable example of the conditions for forming the SiO 2 film: Plasma is formed at an output of 1 to 4 W / cm 2 .

(Mode for modifying the SiO 2 film on the polycrystalline silicon layer)
The manufacturing method according to another aspect of the present invention includes an electronic device substrate, a first SiO 2 film disposed on the substrate, and a first polycrystalline silicon disposed on the first SiO 2 film. A substrate to be processed including at least a layer and a second SiO 2 film disposed on the first polycrystalline silicon layer was generated from a processing gas based on microwave irradiation through a planar antenna member having a plurality of slots It includes at least a step of modifying the second SiO 2 film by exposure to plasma. When the SiO 2 film disposed on such a polycrystalline silicon layer is modified, the advantage of improved operation reliability can be obtained.

For example, as a control gate electrode for a flash memory, a second polycrystalline silicon layer may be formed on the second SiO 2 film thus modified. The second SiO 2 film may be another insulating film (SiN or a stacked structure of SiN and SiO 2 ). In the case where the second polycrystalline silicon layer is formed on such a modified SiO 2 film, it is possible to further obtain the advantage of improving the operation reliability.

When the first polycrystalline silicon layer, the second SiO 2 film, and / or the second polycrystalline silicon layer are formed by CVD, further advantages such as a reduction in thermal history can be obtained. From the viewpoint of productivity, it is most preferable to form all of the first polycrystalline silicon layer, the second SiO 2 film, and the second polycrystalline silicon layer by CVD.

In the electronic device material manufacturing method according to the above aspect, between the step of forming the first polycrystalline silicon layer and the step of forming the second SiO 2 film on the first polycrystalline silicon layer, And / or after forming the second polycrystalline silicon layer, the substrate to be processed is exposed to plasma generated by irradiating a processing gas with microwaves through a planar antenna member having a plurality of slots. The method may further include a step of modifying the first or second polycrystalline silicon layer using plasma. As described above, the surface of the first and second polycrystalline silicon layers is smoothed by including the additional exposure to the plasma generated from the processing gas based on the microwave irradiation through the planar antenna member. 2 can be expected to improve the reliability of the SiO 2 film. Further, by improving the oxidation resistance of the first and second polycrystalline silicon by this step, it is expected that the variation in the area of the polycrystalline silicon in the subsequent step can be suppressed. Furthermore, it is also possible to form the second SiO 2 by oxidizing the polycrystalline silicon surface in this step using a processing gas plasma generated via SPA. This step can be performed at a low temperature. In the normal thermal oxidation process, there is a risk that the device characteristics will be deteriorated by high temperatures, but by using this process, it is possible to form an oxide film while suppressing the deterioration of the device characteristics (dopant diffusion, etc.) due to the thermal process. Become.

(Mode in which a metal layer is formed on the modified insulating layer)
Still another method of manufacturing an electronic device material according to the present invention includes a substrate to be processed including at least a layer of an electronic device material and an insulating film (for example, a gate insulating film) disposed on the layer. And at least a step of modifying the insulating film by exposing to plasma generated from a processing gas based on microwave irradiation through a planar antenna member having; and a step of forming a metal layer on the insulating film. In the case where a metal layer is formed on the insulating film thus modified, advantages such as improved operational reliability and reduced leakage can be obtained.

(Insulating film material)
In the method for manufacturing the electronic device, as the first insulating film (for example, the gate insulating film), conventionally used low dielectric constant SiO 2 , SiON, SiN and high dielectric constant Al 2 O 3 , ZrO 2 , HfO are used. 2 , Ta 2 O 5 , and one or more selected from the group consisting of Silicate such as ZrSiO and HfSiO, and Aluminum such as ZrAlO.

(Flat antenna member)
In the method for producing an electronic device material of the present invention, a plasma having a low electron temperature and a high density is formed by irradiating microwaves through a planar antenna member having a plurality of slots, and the plasma is used to form a film. Since the modification is performed, a process with low plasma damage and high reactivity at low temperatures becomes possible.

  The film subjected to the modification according to the present invention is modified using a plasma having a low electron temperature and a high density obtained by irradiating microwaves through the planar antenna member having the plurality of slots. Therefore, the dangling bonds in the film are terminated in an ideal form. As a result, the insulating characteristics of the film itself are improved, and as a result, an electronic device material (for example, a semiconductor material) having excellent characteristics can be obtained. Further, since the wafer temperature and the chamber temperature can be used at a low temperature, an energy saving process is possible.

(Preferred plasma)
The characteristics of plasma that can be suitably used in the present invention are as follows.
Electron temperature: 0.5 to 2.0 eV
Density: 1E10-5E12 cm −3
Plasma density uniformity: within ± 10%

  According to the present invention, a high-quality modified insulating film can be formed. Therefore, it is easy to form a semiconductor device structure having excellent characteristics by forming another layer (for example, an electrode layer) on the modified insulating film.

(Suitable characteristics of insulating film)
According to the present invention, a modified insulating film having suitable characteristics as described below can be easily formed.
Reduction of leakage current: Low power consumption of device Long-term memory retention capability by applying to flash memory Improvement of reliability: Suppression of deterioration due to increased number of operations

(Suitable characteristics of semiconductor structure)
The range to which the method of the present invention should be applied is not particularly limited, but a high-quality modified insulating film that can be formed according to the present invention can be particularly suitably used as an insulating film of a flash memory structure.

According to the present invention, a flash memory structure having suitable characteristics as described below can be easily manufactured. In evaluating the characteristics of the insulating film modified according to the present invention, for example, a standard as described in the literature (IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol 46, No. 9, SEPTEMBER 1999 PP 1866-1871). By forming a flash memory and evaluating the characteristics of the flash memory, the characteristics of the insulating film itself can be evaluated. This is because in such a standard flash memory structure, the characteristics of the insulating film constituting the structure have a strong influence on the flash memory characteristics.
Characteristics: High repeatability

(Mode of manufacturing electronic device materials)
Hereinafter, one embodiment of the present invention will be described.

  First, an electronic device material manufacturing apparatus that can be used in a method for manufacturing a flash memory according to the present invention will be described.

  FIG. 1 is a schematic view (schematic plan view) showing an example of the entire configuration of an electronic device (semiconductor device) manufacturing apparatus 30 for carrying out the method for manufacturing an electronic device material of the present invention.

  As shown in FIG. 1, a transfer chamber 31 for transferring the wafer W (FIG. 2) is disposed in the approximate center of the semiconductor manufacturing apparatus 30, and surrounds the periphery of the transfer chamber 31. Plasma processing unit 32 for performing various processing on the wafer, CVD processing unit 33, two load lock units 34 and 35 for performing communication / blocking operations between the processing chambers, and various heating operations And a heating reaction furnace 47 for performing various heat treatments on the wafer. The heating reaction furnace 47 may be provided separately from the semiconductor manufacturing apparatus 30.

  Next to the load lock units 34 and 35, a preheating unit 45 and a cooling unit 46 for performing various preheating or cooling operations are respectively arranged.

  Inside the transfer chamber 31, transfer arms 37 and 38 are disposed, and the wafer W (FIG. 2) can be transferred between the units 32 to 36.

  Loader arms 41 and 42 are disposed on the front side of the load lock units 34 and 35 in the drawing. These loader arms 41 and 42 can further load / unload wafers W with four cassettes 44 set on a cassette stage 43 disposed on the front side thereof.

  Further, the plasma processing unit 32 and the CVD processing unit 33 are interchangeable, and the plasma processing unit 32 and the CVD processing unit 33 can be interchanged, and / or the positions of the plasma processing unit 32 and the CVD processing unit 33 are changed. It is also possible to set one or two single-chamber CVD processing units or plasma processing units.

(One aspect of plasma treatment)
FIG. 2 is a schematic vertical sectional view of a plasma processing unit 32 that can be used in the processing of the present invention.

Referring to FIG. 2, reference numeral 50 is a vacuum vessel made of, for example, aluminum. An opening 51 larger than the substrate (for example, the wafer W) is formed on the upper surface of the vacuum container 50, and a flat made of a dielectric material such as quartz or aluminum oxide so as to close the opening 51. A cylindrical top plate 54 is provided. On the side wall on the upper side of the vacuum vessel 50, which is the lower surface of the top plate 54, for example, gas supply pipes 72 are provided at 16 positions arranged uniformly along the circumferential direction. A processing gas containing at least one selected from O 2 , rare gas, N 2, H 2, and the like is supplied uniformly in the vicinity of the plasma region P of the vacuum vessel 50.

  On the outside of the top plate 54, a high frequency power supply unit is formed through a planar antenna member having a plurality of slits, for example, a slot plane antenna (SPA) 60 formed of a copper plate, for example, 2.45 GHz micro A waveguide 63 connected to a microwave power source 61 that generates a wave is provided. The waveguide 63 includes a flat circular waveguide 63A having a lower edge connected to the SPA 60, a cylindrical waveguide 63B having one end connected to the upper surface of the circular waveguide 63A, and the cylindrical waveguide. A coaxial waveguide converter 63C connected to the upper surface of the tube 63B, and a rectangular waveguide having one end connected perpendicularly to the side surface of the coaxial waveguide converter 63C and the other end connected to the microwave power source 61. 63D is combined.

  Here, in the present invention, UHF and microwaves are referred to as a high frequency region. That is, the high-frequency power supplied from the high-frequency power supply unit is 300 MHz to 2500 MHz including UHF of 300 MHz or higher and microwaves of 1 GHz or higher, and the plasma generated by these high-frequency power is called high-frequency plasma. .

  Inside the cylindrical waveguide 63B, one end side of the shaft portion 62 made of a conductive material is connected to substantially the center of the upper surface of the SPA 60, and the other end side is connected to the upper surface of the cylindrical waveguide 63B. Thus, the waveguide 63B is configured as a coaxial waveguide.

  A mounting table 52 for the wafer W is provided in the vacuum container 50 so as to face the top plate 54. The mounting table 52 incorporates a temperature control unit (not shown) so that the mounting table 52 functions as a heat plate. Further, one end side of the exhaust pipe 53 is connected to the bottom of the vacuum vessel 50, and the other end side of the exhaust pipe 53 is connected to the vacuum pump 55.

(One aspect of SPA)
FIG. 3 is a schematic plan view showing an example of SPA 60 that can be used in the electronic device material manufacturing apparatus of the present invention.

  As shown in FIG. 3, the SPA 60 has a plurality of slots 60a, 60a,... Concentrically formed on the surface. Each slot 60a is a substantially rectangular through groove, and adjacent slots are arranged so as to be orthogonal to each other to form the letter “T” of the alphabet. The length and arrangement interval of the slots 60 a are determined according to the wavelength of the microwave generated from the microwave power supply unit 61.

(One aspect of CVD processing unit)
FIG. 4 is a schematic vertical sectional view showing an example of the CVD processing unit 33 that can be used in the electronic device material manufacturing apparatus of the present invention.

  As shown in FIG. 4, the processing chamber 82 of the CVD processing unit 33 is formed in a structure that can be hermetically sealed, for example, with aluminum or the like. Although omitted in FIG. 4, the processing chamber 82 is provided with a heating mechanism and a cooling mechanism.

  As shown in FIG. 4, a gas introduction pipe 83 for introducing gas into the upper center is connected to the processing chamber 82, and the inside of the processing chamber 82 and the inside of the gas introduction pipe 83 are communicated with each other. The gas introduction pipe 83 is connected to a gas supply source 84. A gas is supplied from the gas supply source 84 to the gas introduction pipe 83, and the gas is introduced into the processing chamber 82 via the gas introduction pipe 83. As this gas, for example, various gases (electrode forming gas) such as silane, which are raw materials for gate electrode formation, can be used, and an inert gas can also be used as a carrier gas, if necessary.

  A gas exhaust pipe 85 for exhausting the gas in the process chamber 82 is connected to the lower part of the process chamber 82, and the gas exhaust pipe 85 is connected to an exhaust means (not shown) such as a vacuum pump. By this exhaust means, the gas in the processing chamber 82 is exhausted from the gas exhaust pipe 85, and the processing chamber 82 is set to a desired pressure.

  In addition, a mounting table 87 on which the wafer W is mounted is disposed below the processing chamber 82.

  In the embodiment shown in FIG. 4, the wafer W is mounted on the mounting table 87 by an electrostatic chuck (not shown) having the same diameter as the wafer W. The mounting table 87 is provided with a heat source means (not shown), and has a structure capable of adjusting the processing surface of the wafer W mounted on the mounting table 87 to a desired temperature.

  The mounting table 87 has a mechanism capable of rotating the mounted wafer W as necessary.

  In FIG. 4, an opening 82a for taking in and out the wafer W is provided on the wall surface of the processing chamber 82 on the right side of the mounting table 87. The opening and closing of the opening 82a moves the gate valve 98 in the vertical direction in the figure. Is done. In FIG. 4, a transfer arm (not shown) for transferring the wafer W is provided adjacent to the right side of the gate valve 98, and the transfer arm enters and exits the processing chamber 82 through the opening 82a. The wafer W is placed on the substrate 87 and the processed wafer W is unloaded from the processing chamber 82.

  A shower head 88 as a shower member is disposed above the mounting table 87. The shower head 88 is formed so as to partition a space between the mounting table 87 and the gas introduction pipe 83, and is made of, for example, aluminum.

  The shower head 88 is formed so that the gas outlet 83a of the gas introduction pipe 83 is located at the upper center of the shower head 88, and the gas is introduced into the processing chamber 82 through the gas supply hole 89 provided at the lower part of the shower head 88. Yes.

(Mode of manufacturing electronic device materials)
Next, an aspect of a method for producing an electronic device material according to the present invention will be described below.

  FIG. 4 is a flowchart of a method for manufacturing an electronic device material according to this embodiment, and FIGS. 6 to 8 are schematic vertical sectional views showing respective manufacturing steps of the flash memory cell according to this embodiment.

In this embodiment, first, as shown in FIGS. 5 and 6B, a buried data line (n + layer) (selectively implanted and annealed into a wafer W made of p-type Si as a substrate to be processed). Impurity buried layer) 22 is formed (step 1).

Next, as shown in FIG. 6C, the surface of the wafer W is heated or CVD processed to form the first insulating film, and the SiO 2 film (first SiO 2 film) is formed on the entire surface of the wafer W. 23 is formed (step 2). When the SiO 2 film 23 is formed by thermal oxidation, the heating unit 36 or the heating reaction furnace 47 (FIG. 1) is used. When the SiO 2 film 23 is formed by the CVD method, the CVD processing unit 33 (FIG. 1) is used. 1) can be used.

Next, as shown in FIG. 6D, the wafer W having the first SiO 2 film 23 formed on the surface thereof is loaded into the chamber of the CVD processing unit 33 and heated in the presence of a processing gas, for example, silane gas, to A polycrystalline silicon layer (first polycrystalline silicon layer) 24 is formed on the surface of the first SiO 2 film 23 (step 3).

Next, the first polycrystalline silicon layer is selectively etched and patterned by, for example, photolithography and dry etching techniques (step 4), and a floating gate (on the SiO 2 film 23 is formed as shown in FIG. 7A). Floating Gate) 25 is formed.

Next, the wafer W is loaded again into the CVD processing unit 33 (FIG. 1), subjected to the CVD process on the surface of the wafer W, and as shown in FIG. 7B, the second floating gate 25 is exposed on the second floating gate 25. The SiO 2 layer 26 is formed as a second insulating layer (step 5).

Next, the wafer W is loaded into the plasma processing unit 32 (FIG. 1), where the second SiO 2 layer 26 is subjected to plasma processing to modify the second SiO 2 layer 26 (step 6). .

That is, the transfer arms 37 and 38 are moved into the CVD processing unit 33 to take out the wafer W having the SiO 2 layer formed on the surface, and then a gate valve (on the side wall of the vacuum vessel 50 in the plasma processing unit 32 ( (Not shown) is opened, and the wafer W is placed on the placement table 52 by the transfer arms 37 and 38.

  Subsequently, after closing the gate valve and sealing the inside, the internal atmosphere is evacuated by the vacuum pump 55 through the exhaust pipe 53 and evacuated to a predetermined degree of vacuum, and maintained at a predetermined pressure. On the other hand, for example, 1.80 GHz (2200 W microwave is generated from the microwave power supply unit 61, and this microwave is guided by the waveguide and introduced into the vacuum vessel 50 via the SPA 60 and the top plate 54. A high-frequency plasma is generated in the upper plasma region P in 50.

  Here, the microwave is transmitted in the rectangular mode in the rectangular waveguide 63D, is converted from the rectangular mode to the circular mode by the coaxial waveguide converter 63C, is transmitted through the cylindrical coaxial waveguide 63B in the circular mode, and The flat waveguide 63A is transmitted in the radial direction, is radiated from the slot 60a of the SPA 60, passes through the top plate 54, and is introduced into the vacuum vessel 50. At this time, since microwaves are used, high density and low electron temperature plasma is generated, and since microwaves are emitted from many slots 60a of the SPA 60, the plasma has a highly uniform distribution.

Then, while adjusting the temperature of the mounting table 52 and heating the wafer W to, for example, 400 ° C., a rare gas such as krypton or argon, which is a processing gas for forming an oxide film, and O 2 gas are supplied from the gas supply pipe 72. The reforming process is carried out by introducing at a predetermined flow rate.

For example, this plasma treatment can be suitably performed under the following conditions. That is, a mixed gas of O 2 with a flow rate of 5 to 50 sccm and krypton with a flow rate of 500 to 2000 sccm is used as a processing gas, and the pressure of the plasma source is 300 to 700 ° C. and a pressure of 2.7 to 135 Pa (20 to 1000 mTorr). It can be performed under conditions of an output of 1 to 3 W / cm 2 .

In this step, the introduced processing gas is activated (radicalized) by the plasma flow generated in the plasma processing unit 32, and the SiO 2 film 26 covering the uppermost surface of the wafer W is modified by this plasma. . In this way, the above modification process is performed for 40 seconds, for example, and the modification is performed by causing the plasma of the processing gas to act on the surface of the SiO 2 film 26 on the uppermost surface of the wafer W. The plasma of the processing gas generated at this time has a low electron temperature. Therefore, the bias between the plasma of the processing gas and the SiO 2 film 26 is low. Therefore, impact on the when the plasma of the process gas is brought into contact with the SiO 2 film 26 is small, the plasma damage to the SiO 2 film 26 when the so-called process gas plasma collides with the SiO 2 film 26 surface is small. For this reason, the surface of the SiO 2 film 26 and dangling bonds in the film are appropriately terminated, and the SiO 2 film 26 has a high-quality fine-grained state.

  Next, after modification with plasma in this way, patterning is performed by selective etching (for example, by photolithography and dry etching) (step 7).

Next, the patterned wafer W is loaded into the CVD processing unit 33, and the wafer W is heated in the presence of a processing gas, for example, silane gas, in the CVD processing unit 33, as shown in FIG. A second polycrystalline silicon layer 27 is formed over the entire surface of the finished SiO 2 film 26 (step 8).

  Next, the second polycrystalline silicon layer 27 is patterned by a method such as selective etching (step 9), and a control gate 28 is formed as shown in FIG. 8A.

Next, as shown in FIG. 8B, a third insulating layer (SiO 2 film) 29 is formed on the control gate 28 by, for example, CVD (step 10).

Next, as shown in FIG. 8C, the third insulating layer is patterned to expose a part of the data line (n + layer) 22 (step 11).

  Further, as shown in FIG. 8D, a metal layer 31 is formed by depositing a metal such as aluminum on the insulating layers 23, 26, 29 and the data line 22 (step 12). Further, the metal layer is patterned (for example, by photolithography and selective etching) to form an electrode (step 13).

  Thereafter, the cell manufacturing process is completed by performing an insulating film forming process, a passivation layer forming process, a contact hole forming process, a wiring forming process, and the like by a general method (such an insulating film forming process, a passivation layer forming process, Regarding the cell manufacturing process including the contact hole forming process and the wiring forming process, reference can be made to, for example, the literature ULSI TECHNOLOGY McGRAW-HILL INTERNATIONAL EDITIONS CY CHANG and SM SZE).

In the modification step (step 6) of the SiO 2 film 26 described above, when modifying the SiO 2 film 26, a plane having a plurality of slots is formed in the wafer W mainly composed of single crystal silicon in a processing gas atmosphere. Since the plasma containing oxygen (O 2 ) and rare gas is formed by irradiating microwaves through the antenna member (SPA), and the SiO 2 film 26 is modified using this plasma, the quality is improved. And film quality can be controlled successfully.

The quality of the modified oxide film (SiO 2 film 26) is high as shown in the graph of FIG.

FIG. 9 shows the reliability of the SiO 2 film 26 subjected to the modification process by applying plasma to the surface of the SiO 2 film 26 via SPA in the modification step (step 6) of the manufacturing method of the electronic device material according to this embodiment. It is a graph showing an evaluation result.

  The vertical axis of this graph is the failure rate value, and the horizontal axis is the Qbd value (dielectric breakdown charge).

The device structure in this measurement was created by the following methods 1-7.
1: Substrate A P-type or N-type silicon substrate is used as the substrate, and one having a specific resistance of 1 to 30 Ωcm and a plane orientation (100) is used. A 500A sacrificial oxide film is formed on the surface of the silicon substrate.

2: Cleaning before Gate oxidation APM (mixture of ammonia, hydrogen peroxide, and pure water), HPM (mixture of hydrochloric acid, hydrogen peroxide, and pure water) and DHF (mixture of hydrofluoric acid and pure water) The sacrificial oxide film and contamination elements (metal, organic matter, particles) were removed by combined RCA cleaning.

3: a SiO 2 film by a deposition CVD of SiO 2. SiH 2 Cl 2 and N 2 O were allowed to flow at 200 sccm and 400 sccm respectively on the substrate heated to 780 ° C., and the pressure was maintained at 60 Pa for 30 minutes, and a 60 A CVD oxide film (High Temperature Oxide: HTO). Was deposited.

4: Plasma oxidation process The silicon substrate on which the SiO 2 film of 3 was formed was modified by the following method. The silicon substrate on which the 3 SiO 2 film is formed is heated to 400 ° C., and a rare gas and oxygen are flown over the wafer at 1000 sccm and 20 sccm, respectively, and the pressure is maintained at 13 Pa to 107 Pa (100 mTorr to 900 mTorr). A plasma containing oxygen and a rare gas is formed by irradiating a microwave of 3 W / cm 2 through a planar antenna member (SPA) having a plurality of slots in the atmosphere. Two membranes were modified.

5: Polysilicon film formation for Gate electrode Polysilicon film was formed as a Gate electrode on the Sio 2 film formed in 3 and 4 by the CVD method. The silicon substrate on which the SiO 2 film is formed is heated at 630 ° C., and silane gas 250 sccm is introduced onto the substrate under a pressure of 33 Pa and is held for 30 minutes, whereby the electrode polysilicon having a film thickness of 3000 A is formed on the SiO 2 film. Form a film.

6: P (phosphorus) doping to polysilicon The silicon substrate fabricated in 5 is heated to 800 ° C., and POCl 3 gas, oxygen, and nitrogen are introduced onto the substrate at 350 sccm, 200 sccm, and 20000 sccm, respectively, at normal pressure for 24 minutes. By holding, the polysilicon was doped with phosphorus.

7: Patterning, Gate etching Patterning is performed by lithography on the silicon substrate manufactured in 6 and patterning is performed by immersing the silicon substrate in a chemical solution having a ratio of HF: HNO 3 : H 2 O = 1: 60: 60 for 3 minutes. The portion of the polysilicon that was not melted was melted to produce a MOS capacitor.

The measurement was performed by the method as shown below. A constant current stress of −0.1 A / cm 2 was applied to a capacitor having a Gate electrode area of 10,000 μm 2 , and the time until dielectric breakdown occurred (Break Down Time: Tbd) was measured. The dielectric breakdown charge (Qbd) is an absolute value of a product of current stress −0.1 A / cm 2 and Tbd.

Graph (1) shows the Qbd value of a SiO 2 film (High Temperature Oxide: HTO) formed by a conventional CVD method for reference, and graph (2) shows the presence of O 2 and 2 krypton as a rare gas. The Qbd value of the result obtained by plasma-treating the above-mentioned SiO 2 film at a pressure of 100 mTorr using SPA is shown. Graph (3) shows the above-described SiO 2 film using SPA in the presence of O 2 and krypton. The Qbd value of the plasma treatment obtained at a pressure of 500 mTorr is shown. Graph (4) is obtained by plasma treatment of the above SiO 2 film at a pressure of 900 mTorr using SPA in the presence of O 2 and krypton. Represents the Qbd value.

As is apparent from the graph of FIG. 9, the Qbd value of the SiO 2 film modified by the manufacturing method of the present invention is higher than the Qbd value of the SiO 2 film formed by the conventional CVD method. High-quality and high-quality device characteristics are expected.

  By the electronic device manufacturing method of the present invention, it was possible to modify and form an oxide film having a higher quality and a higher Qbd value than a conventional CVD oxide film.

(Estimated mechanism of high quality modified insulating film)
The reason why the quality of the insulating film modified by the above-described method becomes high is estimated as follows according to the knowledge of the present inventor.

That is, plasma formed by irradiating a processing gas with microwaves using SPA is formed with high density and relatively low electron temperature. Therefore, high-density radicals can be generated, and the bias between the plasma and the surface of the substrate to be processed is suppressed to a relatively low value, and plasma damage is small. Therefore, the dangling bonds in the SiO 2 film are appropriately terminated by the oxygen reactive species generated by the plasma, and the weak Si—Si bond is changed to a strong Si—O—Si bond, which is good as shown in FIG. It is considered that the SiO 2 film having electrical characteristics is reformed.

Hereinafter, the present invention will be described more specifically with reference to examples.
A first SiO 2 film is formed to a thickness of about 10 nm on a substrate to be processed mainly composed of single crystal silicon, and a CVD process is applied to the substrate to be processed to form a first polycrystalline silicon film on the first SiO 2 film. A layer is formed to a thickness of about 100 nm to 300 nm. Thereafter, the substrate to be processed is subjected to CVD and high-temperature oxidation heat treatment to form a second SiO 2 film having a thickness of about 5 to 10 nm on the first polycrystalline silicon layer.

The formed object to be processed is placed on a mounting table heated to 400 ° C., and the surface of the second SiO 2 film is placed in an atmosphere of argon 1000 sccm, oxygen gas 50 sccm, and total pressure 500 mT via SPA (Slot Plain Antenna). The plasma generated by irradiating 2 W / cm 2 of microwave for 2 min. Expose to a degree. Through these steps, the second SiO 2 film subjected to the CVD and high-temperature heat oxidation treatment is modified to improve the characteristics.

In addition, this invention is not limited to an above-described aspect. For example, in the above embodiment, only the insulating layer (SiO 2 layer) 26 between the two polycrystalline silicon layers 25 and 28 is subjected to the surface treatment using the processing gas plasma generated via SPA. An insulating layer other than the above, for example, one or both of the SiO 2 layers 23 and 29 may be subjected to a surface treatment using a processing gas plasma generated via SPA in the same manner as described above.

Further, the surface of the two polycrystalline silicon layers 25 and 28 is surface-modified using the processing gas plasma generated via SPA, so that the surfaces of the two polycrystalline silicon layers become smooth, and the polycrystalline silicon layer An improvement in the reliability of the insulating layer 26 between 25 and 28 (a layer formed of SiO 2 or SiN) can be expected. In addition, the oxidation resistance of 25 or 28 polycrystalline silicon can be improved by using a rare gas and nitrogen gas as the processing gas in this process, and the area variation of the polycrystalline silicon in the subsequent process can be suppressed.

Furthermore, it is also possible to form 26 SiO 2 by oxidizing 25 polycrystalline silicon surfaces using process gas plasma generated via SPA. This step can be performed at a low temperature. In the normal thermal oxidation process, there is a risk that the device characteristics will be deteriorated by high temperatures, but by using this process, it is possible to form an oxide film while suppressing the deterioration of the device characteristics (dopant diffusion, etc.) due to the thermal process. Become.

  In that case, it is possible to perform automatic continuous processing up to the steps 25 to 27 without being exposed to the atmosphere and in the semiconductor manufacturing apparatus shown in FIG. 1, thereby improving the reliability of the semiconductor performance and simplifying the manufacturing process. Can be expected.

(Second aspect)
Below, the 2nd aspect of this invention is demonstrated. In the second aspect, the insulating film is subjected to surface modification by SPA plasma processing in the logic device manufacturing process.

  FIG. 10 is a flowchart showing the manufacturing process of the logic device according to this aspect, and FIG. 11 is a schematic vertical sectional view schematically showing the manufacturing process of the logic device according to this aspect.

The logic device manufacturing method according to this aspect is roughly divided as follows.
Element isolation-> MOS transistor fabrication-> Capacitance fabrication-> Interlayer insulation film deposition and wiring The following explains the fabrication of the MOS structure, which is the previous step in the fabrication of MOS transistors including the SPA process, with a general example Do.

1: Substrate A P-type or N-type silicon substrate is used as the substrate, and one having a specific resistance of 1 to 30 Ωcm and a plane orientation (100) is used.

  Depending on the purpose, element isolation processes such as STI and LOCOS and channel implantation are performed on the silicon substrate, and a sacrificial oxide film is formed on the surface of the silicon substrate on which the gate oxide film and the gate insulating film are formed. (FIG. 11A).

2: Cleaning before forming a gate oxide film (Gate insulating film) Generally, APM (mixture of ammonia, hydrogen peroxide, and pure water), HPM (mixture of hydrochloric acid, hydrogen peroxide, and pure water), and DHF (mixed liquid) The sacrificial oxide film and the contaminating elements (metal, organic matter, particles) are removed by RCA cleaning using a combination of hydrofluoric acid and pure water. SPM (mixed solution of sulfuric acid and hydrogen peroxide solution), ozone water, FPM (mixed solution of hydrofluoric acid, hydrogen peroxide solution and pure water), hydrochloric acid solution (mixed solution of hydrochloric acid and pure water), organic as required Sometimes alkali or the like is used.

3: Formation of Gate Oxide Film (Gate Insulating Film) Gate insulating film formation is roughly divided into a process using thermal oxidation and a process using CVD. Here, the formation of a gate insulating film by CVD is mainly described. The formation of the gate insulating film by CVD is performed by supplying a source gas (for example, SiH 4 and N 2 O) onto the above-described silicon substrate heated in a range of 200 ° C. to 1000 ° C., and reacting species formed by heat (for example, Film formation (for example, SiO 2 ) is performed by reacting Si radical and O radical on the film surface. The reactive species may be generated by plasma. Generally, the thickness of the gate oxide film is 1 nm to 10 nm (FIG. 11B).

4: Gate insulating film reforming process by SPA plasma The insulating film by CVD described in 3 is oxidized by mainly using rare gas and oxygen as gases for forming SPA plasma, thereby modifying the CVD film. The effect of oxidation includes an effect of improving film characteristics by changing weak Si—Si bonds in the film to strong Si—O—Si bonds. Further, the plasma nitriding treatment can be performed by using a gas containing rare gas and nitrogen as a gas for forming SPA plasma. The effects of nitriding include thinning by increasing the dielectric constant and suppressing the diffusion of dopant from the Gate electrode. (FIG. 11B)

5: Polysilicon film formation for gate electrode Polysilicon (including amorphous silicon) is used as a gate electrode of the MOS transistor on the gate insulating film (including gate oxide film and gate oxynitride film) formed in steps 3 and 4 by CVD. To form a film. Gate insulation is performed by heating a silicon substrate on which a gate insulating film is formed in a range of 500 ° C. to 650 ° C. and introducing a gas containing silicon (silane, disilane, etc.) under a pressure of 10 to 100 Pa on the substrate. A polysilicon film for an electrode having a thickness of 50 nm to 500 nm is formed on the film. As the gate electrode, silicon germanium or metal (W, Ru, TiN, Ta, Mo, etc.) may be used instead of polysilicon (FIG. 11C).

  Thereafter, gate patterning and selective etching are performed to form a MOS capacitor (FIG. 11D), and a source and a drain are formed by ion etching (FIG. 11E). Subsequently, a logic device according to the present embodiment is obtained through a wiring process that combines film formation of an interlayer insulating film, patterning, selective etching, and metal film formation as subsequent processes (FIG. 11F).

Although an oxide film (SiO 2 film) is formed as an insulating film in this embodiment, an insulating film having a composition other than that can be formed. As the gate insulating film, conventionally used SiO 2 , SiON, SiN having a low dielectric constant, Al 2 O 3 , ZrO 2 , HfO 2 , Ta 2 O 5 having a high dielectric constant, and Silicate such as ZrSiO, HfSiO are used. And one or more selected from the group consisting of Aluminate such as ZrAlO.

  In this embodiment, the active atoms supplied by the low-temperature and high-density plasma generated via SPA have the effect of terminating the film surface or in the film, and are supplied by plasma composed of a gas containing a rare gas and nitrogen. As the nitrogen reactive species enter the surface layer, an effect as a barrier that suppresses diffusion of dopant from polycrystalline silicon can be expected.

FIG. 1 is a schematic view (schematic plan view) of a manufacturing apparatus for carrying out the electronic device manufacturing method of the present invention. FIG. 2 is a schematic vertical cross-sectional view showing an example of a slot plain antenna (hereinafter abbreviated as “SPA”) plasma processing unit that can be used in the electronic device manufacturing method of the present invention. FIG. 3 is a schematic plan view of an SPA that can be used in the electronic device manufacturing apparatus of the present invention. FIG. 4 is a schematic vertical sectional view of a CVD processing unit that can be used in the electronic device manufacturing method of the present invention. FIG. 5 is a flowchart showing an example of each step in the manufacturing method of the present invention. FIG. 6 is a schematic vertical sectional view showing an example of a state in the process of manufacturing the flash memory according to the manufacturing method of the present invention. FIG. 7 is a schematic vertical sectional view showing an example of a state in the middle of manufacturing the flash memory according to the manufacturing method of the present invention. FIG. 8 is a schematic vertical sectional view showing an example of a state in the middle of manufacturing the flash memory according to the manufacturing method of the present invention. FIG. 9 is a graph comparing various processing conditions and the quality characteristics of the insulating film obtained under the processing conditions. FIG. 10 is a flowchart showing an example of the manufacturing process of the logic device according to the second embodiment of the present invention. FIG. 11A is a schematic vertical sectional view showing an example of a manufacturing process of a logic device according to the second embodiment of the present invention. FIG. 11B is a schematic vertical sectional view showing an example of the manufacturing process of the logic device according to the second embodiment of the present invention. FIG. 12 is a schematic vertical sectional view of a typical flash memory.

Explanation of symbols

In the above drawings, the meanings of the used symbols are as follows.
20 wafer (substrate to be processed),
60 SPA (planar antenna member),
23 Insulating film (first SiO 2 film),
32 plasma processing unit (process chamber),
33 CVD processing unit (process chamber),
47 Heating reactor.

Claims (10)

  1. Carrying the substrate on which the insulating film is formed into a vacuum vessel;
    Generating a plasma using a planar antenna having a plurality of slots in the vacuum vessel and a processing gas, and modifying the insulating film with the plasma, and a plasma processing method comprising:
    The processing gas is a mixed gas containing a rare gas and oxygen, or a mixed gas containing a rare gas and nitrogen, and the plasma has a flow rate of the oxygen gas when the processing gas is a mixed gas containing a rare gas and oxygen. 1 to 1000 sccm, the flow rate of the rare gas is 200 to 3000 sccm, and when the process gas is a gas containing a rare gas and nitrogen, the flow rate of nitrogen gas is 10 to 500 sccm, and the flow rate of the rare gas is 200 to 3000 sccm. And
    The plasma processing method, wherein the plasma has a density of 1 × 10 10 to 5 × 10 12 / cm 3 .
  2. Carrying the substrate on which the insulating film is formed into a vacuum vessel;
    Generating a plasma using a planar antenna having a plurality of slots in the vacuum vessel and a processing gas, and modifying the insulating film with the plasma, and a plasma processing method comprising:
    The processing gas is a mixed gas containing a rare gas and oxygen, or a mixed gas containing a rare gas and nitrogen, and the plasma has a flow rate of the oxygen gas when the processing gas is a mixed gas containing a rare gas and oxygen. 1 to 1000 sccm, the flow rate of the rare gas is 200 to 3000 sccm, and when the process gas is a gas containing a rare gas and nitrogen, the flow rate of nitrogen gas is 10 to 500 sccm, and the flow rate of the rare gas is 200 to 3000 sccm. And
    The step of modifying the insulating film is performed at a temperature of room temperature to 700 ° C. and a pressure of 20 to 5000 mTorr,
    The plasma processing method, wherein the plasma has an electron temperature of 0.5 to 2 eV.
  3. The plasma processing method according to claim 1, wherein the plasma is generated at an output of 0.5 to 5 W / cm 2 .
  4. The insulating film SiO 2, a silicon oxynitride film (SiON), silicon nitride (SiN), aluminum oxide (Al 2 O 3), zirconium oxide (ZrO 2), hafnium oxide (HfO 2), silicates, and aluminates One or more selected from the group consisting of:
    The silicate is a composition ZrSiO or HfSiO, plasma processing method according to any one of claims 1 to 3, wherein the aluminate is a composition ZrAlO or HfAlO.
  5. Wherein the insulating film is a plasma processing method according to any one of claims 1 to 4 formed by using CVD, thermal oxidation or plasma.
  6. A substrate,
    A first insulating film formed on the substrate;
    A first polycrystalline silicon layer formed on the first insulating film;
    A second insulating film formed on the first polycrystalline silicon layer;
    A second polycrystalline silicon layer formed on the second insulating film;
    A third insulating film formed on the second polycrystalline silicon layer;
    A processing method for a substrate to be processed, comprising:
    A step of modifying the second insulating film in the vacuum vessel by plasma generated using a planar antenna having a plurality of slots in the vacuum vessel and a processing gas;
    In the step of modifying the second insulating film,
    When the processing gas is a mixed gas containing a rare gas and oxygen, or a mixed gas containing a rare gas and nitrogen, and the processing gas is a mixed gas containing a rare gas and oxygen, the flow rate of the oxygen gas is 1 to 1000 sccm. When the flow rate of the rare gas is 200 to 3000 sccm and the plasma is generated and the processing gas is a gas containing a rare gas and nitrogen, the flow rate of the nitrogen gas is 10 to 500 sccm and the flow rate of the rare gas is 200 to 3000 sccm. The plasma is generated, and the electron temperature of the plasma is 0.5 to 2 eV.
  7. The processing method according to claim 6 , wherein the second insulating film is made of SiN or a laminate of SiN and SiO 2 .
  8. The processing method according to claim 6 , wherein the first insulating film is SiO 2 .
  9. The processing method according to claim 6 , wherein the step of modifying the second insulating film is performed at a temperature of room temperature to 700 ° C. and a pressure of 20 to 5000 mTorr.
  10. The processing method according to claim 6 , further comprising a step of modifying each of surfaces of the first polycrystalline silicon and the second polycrystalline silicon with plasma.
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