JP4405959B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, an arrangement ball machine, a sparrow ball game machine, and a revolving game machine, and more particularly to a gaming machine in which the occurrence timing of a big hit state is unpredictable.

  A ball game machine such as a pachinko machine is provided with a symbol start opening provided on the game board, a liquid crystal display that is stopped after a plurality of symbols are changed for a predetermined time, and a grand prize opening that is opened and closed by an opening and closing plate. It is configured. When the detection switch provided at the symbol start port detects the passing of the game ball, the display symbol is changed for a predetermined time on the liquid crystal display, and then when the special symbol is aligned and stopped, the big prize opening is opened and the player The company is trying to generate a profitable situation.

  In this type of gaming machine, the jackpot counter CT is realized by software, and when the jackpot probability is 1 / N, the jackpot counter CT is circulated within a numerical range of 0 to N-1, while the numerical value is One of the ranges is set to the big hit winning value Hit. Here, the big hit counter CT specifically means a specific address of the RAM (hereinafter referred to as CT address). Then, due to an interrupt signal generated every predetermined time, the CPU reads the contents of the CT address, and stores the result of the increment processing in the CT address again, thereby updating the value of the big hit counter.

  Thus, the big hit counter CT (CT address) is updated in synchronization with the interrupt signal. However, when the detection switch provided at the symbol start port detects the passing of the game ball, the CT at that time The contents of the address are read out as a random number for lottery, and when this matches the jackpot winning value Hit, the subsequent profit state is entered. Note that the CT address constituting the jackpot counter is cleared to zero along with other RAM areas by the initial processing after power-on.

  By the way, the jackpot winning value Hit can be grasped only by obtaining the gaming machine and analyzing the program. Therefore, if an illegal circuit is attached to the gaming machine having the above configuration and the interrupt signal after power-on is counted, the big hit timing at which the value of the big hit counter CT matches the big hit winning value Hit can be known. . Moreover, since the big hit timing comes regularly corresponding to the Nth interrupt signal, if the ON signal of the detection switch of the symbol start opening is generated by an illegal circuit in accordance with the big hit timing, A big hit state can be realized arbitrarily.

  Therefore, in order to deal with such illegal actions, an attempt has been made to make the value of the jackpot counter CT irregular by using the sub-counter BGN in addition to the jackpot counter CT. In this case, the sub-counter BGN circulates starting from 0 in the numerical range of 0 to N-1. The big hit counter CT circulates in the numerical range of 0 to N−1 starting from the initial value START determined by the subcounter BGN.

  Then, when the big hit counter CT goes around the numerical value range N, the value of the sub-counter BGN at that time is acquired, and the circulation operation is repeated again by using it as a new initial value START. If the initial value START of the jackpot counter CT is changed at random in this way, the jackpot timing will not come regularly corresponding to the Nth interrupt signal, which has a great effect on eliminating fraud. .

  However, even in the above countermeasure, only the initial initial value after the CPU is reset as after the power is turned on must be determined uniformly in software (usually zero). If an illegal circuit is attached and the CPU is forced to be reset at an appropriate timing, the big hit timing can be grasped only in the first round after the reset.

  In other words, even if the initial value is changed at random, the CPU is repeatedly reset at appropriate time intervals, and thereafter, the ON signal of the detection switch at the symbol start opening at the timing when the big hit counter CT coincides with the big hit winning value Hit. There is a problem that a big hit state occurs every time.

  The present invention has been made in view of such problems, and it is an object of the present invention to provide a gaming machine capable of excluding illegal gaming acts even when a jackpot winning value is known.

In order to solve the above problems, the present invention provides a backup power source that maintains RAM data even after the power is shut off, and is configured so that the game operation before the power shuts off can be resumed when the power is turned on, while the CPU is reset. In the gaming machine configured to execute the RAM clear process for forcibly clearing the RAM data when the initialization switch is turned ON during the operation, the initial process executed after the CPU reset is completed. After that, it has a system reset process that repeats an infinite loop process, a timer interrupt process that is activated every predetermined time, and a backup process that sets a backup flag secured in the RAM to a predetermined value when the power is turned off. A main counter used in a random number lottery process for determining whether or not to generate a profit state advantageous to the player; A sub-counter that is updated at predetermined time intervals in the timer interrupt process and determines an initial value of the main counter, and the main counter is composed of a 16-bit length register built in the CPU, while the main counter Each time the counter circulates one or more times within a predetermined numerical range, an initial value of the subsequent circulation operation is determined based on the value of the sub-counter. Even if not turned on, if the backup flag is not a predetermined value, the RAM clear process is executed. However, the value of the main counter is set to a fixed value even after the CPU reset operation. And the numerical value is determined prior to the random number lottery process, and if the numerical value exceeds the predetermined numerical range, the numerical value is It is configured to be exposed.

In the present invention, since the CPU's 16-bit register is used as the main counter , even if the CPU is illegally reset and the RAM clear process is executed, the main counter will not be cleared , and illegal games will be ensured. Can be eliminated.

  As described above, according to the present invention, it is possible to realize a gaming machine that can eliminate fraudulent gaming acts in advance even if the jackpot winning value is known.

  Hereinafter, the gaming machine of the present invention will be described in more detail based on examples. FIG. 1 is a block diagram illustrating an overall configuration of a pachinko machine according to an embodiment.

  The illustrated pachinko machine includes a main control board 1 for centrally controlling the game operation, a symbol control board 2 for controlling the operation of the liquid crystal display 8, a voice control board 3 for accelerating the game operation, and lamps. In response to the lamp control board 4 that makes the flashing operation and the game operation is excited, the payout control board 5 that pays out the game ball, the launch control board 7 that is controlled by the payout control board 5 and launches the game ball, and AC24V The power supply board 6 supplies a DC voltage to each part of the apparatus.

  The main control board 1, the symbol control board 2, the voice control board 3, the lamp control board 4, and the payout control board 5 are configured by a computer circuit including a one-chip microcomputer, and the sub control boards 2 to 5 are the main control boards. Individual control operations are realized based on the control commands from 1.

  FIG. 2 is a block diagram showing a circuit configuration of the main control board 1. As shown in the figure, the main control board 1 includes a CPU circuit 1a composed of a one-chip microcomputer, a system clock generator 1b that generates a clock signal Φ0 that is an integer multiple of the CPU operating clock CLK, and an address signal from the CPU. A decoding circuit 1c for generating a chip select signal for each part, an output port circuit 1d for outputting data from the CPU, an input port circuit 1e for the CPU to take in external data, and the sub-control boards 2 to 5 The output drive circuit 1f for outputting a control command to the controller and the switch input circuit 1g for inputting the ON / OFF state of switches of each part of the game board are mainly configured.

  In this embodiment, the one-chip microcomputer 1a incorporates a Z80 CPU equivalent as a CPU, and is made into one chip together with RAM, ROM, and other ICs. In addition to F (flag register), the Z80 CPU is a general-purpose register (A, B, C, D, E, H, L) each having an 8-bit length, and a back register (A ′, B ′) having the same 8-bit length. , C ′, D ′, E ′, H ′, L ′) and 16-bit index registers (IX, IY). These registers are not initialized by the internal circuit even when the power is reset, and random values at the power-on stage are held as they are.

  Therefore, in this embodiment, among the index registers, the IX register is used as a big hit counter. That is, in this embodiment, although the big hit counter CT is realized by software, since the IX register is used without using a memory area (RAM), the update processing of the big hit counter is completed exclusively by processing inside the CPU. be able to. Because of this configuration, not only can the update process be completed in a short time, but even if the CPU is illegally reset, the value of the jackpot counter is not forcibly reset to zero, Unauthorized gaming can be reliably eliminated.

  3 to 6 are flowcharts showing a control program of the main control board 1. The control program for the main control board 1 is a system reset processing program (FIG. 3) that is executed after the power is turned on and normally ends with an infinite loop processing (ST6), and a timer interrupt processing (prohibitable interrupt) program that is activated every predetermined time. (FIG. 4) and an NMI processing program (FIG. 6) which is driven by an NMI (Non Maskable interrupt) signal to back up the register value of the CPU when the power supply voltage falls below a predetermined value.

  The system reset processing program (main routine) will be described below with reference to FIG. This main routine is started not only when the power is turned on, but also when the count value of the watchdog timer reaches a predetermined value due to a program runaway and the CPU is reset. In addition, there is a possibility that the CPU is illegally reset due to mounting of an illegal circuit. There are also two patterns when the power is turned on, such as when the initialization switch 54 is turned off and the power is turned on, such as when recovering from a power failure, and when the pachinko hall is opened, There are cases where the initialization switch 54 is ON and the power is turned ON.

  In the main routine shown in FIG. 3, first, the Z80 CPU sets itself to an interrupt disabled state, and initializes each part of the one-chip microcomputer including the Z80 CPU core (ST1). Further, the CPU sets itself to interrupt mode 2 (ST2). In this embodiment, the index register IX is assigned to the jackpot counter, but the value of the index register IX is not initially set in the process of step ST1. Therefore, the index register IX holds an arbitrary value having a 16-bit length that is randomly determined when the power is turned on.

  Next, the CPU determines the value of the RAM clear signal (ST3). The RAM clear signal is a signal indicating whether or not to initialize the RAM area, and has a value corresponding to the ON / OFF state of the initialization switch 54. Assuming that the pachinko hall is opened and the initialization switch 54 is turned on and the power is turned on, the determination in step ST3 is Yes, the RAM work area is initialized, and other RAM areas are cleared to zero. At the same time, the CPU is set to an interrupt permission state (EI) (ST5). Thereafter, random number generation processing is performed in an infinite loop (ST6).

  The random number generation process of step ST6 includes an update process of the sub-counter BGN circulating through the numerical value range MAX by the increment process, and an update process of the off symbol counter. As will be described later, the value of the sub-counter BGN is used to change the initial value of the jackpot counter IX circulating through the numerical value range MAX by the random number generation process (ST21) in FIG. Further, the out symbol counter is a process for determining what kind of out game to be produced when it is in a disengagement state due to the big hit determination process in the special symbol processing (ST25) of FIG. is there.

  When the initialization switch 54 is in the OFF state as in the case of recovery from the power failure state, the content of the backup flag BFL is determined following the determination in step ST3 (ST4). The backup flag BFL is data indicating whether or not the backup data saved in the NMI process has been restored to the original state. In this embodiment, the backup flag BFL is set in the process of step ST74 in FIG. 5AH and is cleared to zero in the process of step ST12 of FIG.

  On the other hand, if it is determined in step ST4 in FIG. 3 that the content of the backup flag BFL is 5AH, 16-bit data read from the SP storage area of the RAM is written to the stack pointer SP of the CPU (ST7). Next, the RAM area data backed up in the NMI process at the time of a power failure is read out, and a backup restoration command is created (ST8 to ST10).

  Here, the backup return command creation processing (ST8) for the payout control board means a preparatory operation for rechecking the error signal and outputting a control command according to the current state of the gaming machine to the payout control board 5. . For example, if there is an error condition that the lower plate is full before the power failure, the error state is saved by the backup data, but it is highly possible that the player collects the game balls due to the power failure. The current situation is being confirmed.

  In addition, the backup return command creation process (ST9, ST10) for the symbol control board and the lamp control board is a so-called probability change state in which the gaming machine before the power failure is in a big hit state or the winning probability is increased. In such a case, the background color of the liquid crystal display 8 is set in accordance with the operating state, and a sound effect can be generated.

  When the processing of steps ST8 to ST10 is completed, the CPU executes the POP instruction to restore the values of the registers (BC, DE, HL) excluding the AF register from the stack area (ST11). As a result of this process, the recovery process after the power failure is completed, so the backup flag BFL is cleared to zero to indicate that (ST12). Finally, it is checked whether or not the interrupt was prohibited before the power failure (ST13 and ST14), and after the AF register is returned from the stack area (ST15 and ST17), the processing is ended while the interrupt is disabled (ST15 and ST17). (ST16) Or, the process is finished after returning to the interrupt enabled state (ST18, ST19). By executing the RET instruction in steps ST16 and ST19, the value of the PC (program counter) at the time of the PUSH processing being restored in the stack area is restored, and the processing suspended due to a power failure or the like is resumed. It will be.

  FIG. 4 is a flowchart showing the contents of the interrupt processing program of the timer interrupt INT (prohibited interrupt) that occurs every 2 msec during the infinite loop processing (ST6) of the main routine shown in FIG. When a timer interrupt occurs, the contents of each register are saved in the stack area, and switch input management processing, error management processing, etc. are performed (ST20). The error management process is a determination as to whether an abnormality has occurred inside the device. The switch input management process is a determination as to whether or not a game ball has passed through a gate 38, a symbol start opening 35, and the like, which will be described later. If the game ball has passed through the symbol start opening 35, a special operation is performed. In the symbol process ST25, a big hit lottery is performed using the index register IX (a big hit counter).

  When the process of step ST20 is completed, a random number generation process is performed (ST21). The random number generation processing refers to update processing of the winning counter RG and the big hit counter CT used in the lottery operation in the normal symbol processing ST24 and the special symbol processing ST25. In the present embodiment, the hit counter RG is assigned with a predetermined memory address as before, but the big hit counter CT is assigned with a predetermined CPU register (here, the index register IX) and counted. As described above, the index register IX is not cleared to zero even when the CPU is reset.

  FIG. 5 exemplifies the specific contents of the update processing (random number generation processing) of the index register IX serving as the jackpot counter CT and the jackpot counter RG. As shown in FIG. 5A, first, it is determined whether or not the value of the index register IX exceeds the numerical value range MAX (ST50). This determination is necessary because the index register IX has an arbitrary value of 16 bits because the index register IX is not initialized in the initial setting (ST1) after power-on.

  Here, if the value of the index register IX exceeds the numerical value range MAX (IX> MAX), mask processing is performed between the value of the index register IX and a predetermined mask value MASK (ST51). The mask value MASK is a numerical value for putting the value of the index register IX in the numerical value range MAX. MASK <MAX, only the lower predetermined bits are set to 1, and the remaining upper bits are 0. For example, when the numerical range is 317 and the big hit counter CT should be circulated in the range of 0 to 316, MASK = 255 (= 0000000011111111).

  By taking a logical product (AND) for each corresponding bit between the mask value MASK and the index register IX, the value of the index register IX can be less than a predetermined numerical range MAX. . As a result, the value of the index register IX, which is a random value after power-on, can be kept within a predetermined numerical range. Since the index register IX cannot directly perform mask processing, it is temporarily processed in a general-purpose register or memory.

  In the process of step ST50, if the value of the index register IX is less than the numerical value range MAX (IX <MAX), the index register IX is incremented. Alternatively, in the process of step ST50, if the value of the index register IX is the numerical value range MAX (IX = MAX), the value of the index register IX is returned to zero (ST53).

  Next, it is determined whether or not the value of the index register IX has reached the initial value START (ST54). If the value reaches the initial value START after going around the numerical value range (updated in the process of step ST6). The value of the sub counter BGN is written into the index register IX (ST55). Further, the value of the sub-counter BGN is written in the START address as a new initial value, and the process ends (ST56). The update of the winning counter RG is as shown in FIG. 5B (ST60 to ST62). The value of the winning counter RG is the normal symbol processing (ST24) when the game ball passes the gate. Used for lottery operation.

  When the random number generation process is completed as described above, the value of the process division counter is determined, and the corresponding process from ST23 to ST27 is performed. The above error management and switch management should be repeated at short time intervals. On the other hand, the processing related to the pachinko game production is complicated and sophisticated according to the player's needs, and therefore requires a certain amount of processing time. It will be. Therefore, in this embodiment, not all the game control operations are completed by one interrupt process, but are divided into five types of processes, and each divided process is divided and executed for each interrupt. Yes. Therefore, a processing division counter that circulates in the range of 0 to 4 is provided to perform processing according to the value of the processing division counter.

  More specifically, when the processing division counter is 0, processing relating to the opening of a big prize opening is performed (ST23), and when the processing division counter is 1, normal symbol processing relating to display of a normal symbol is performed (ST24). ), When the processing division counter is 2, processing relating to the display of the jackpot symbol is performed (ST25). If the gate pass switch is in the ON state, in normal symbol processing ST24, whether or not it is normal hit using the hit counter RG is determined. If the pass switch at the symbol start port is in the ON state, special symbol processing is performed. At 25, a jackpot determination using the index register IX is performed.

  If the process division counter is 3, timer management processing related to the opening / closing timing of the electric tulip and the big prize opening is performed (ST26). If the process division counter is 4, information output and error display command creation processing is performed (ST27). In the processing of steps ST23 to ST25, command creation processing transmitted from the main control board to each sub control board is also performed.

  When any one of steps ST23 to ST27 is completed, the value of the process division counter is updated (ST28), and the generated command is output to each sub-control board (ST29). In addition, the value of each register is restored and changed to the interrupt enabled state, and the routine returns from the interrupt processing routine to the main routine.

  FIG. 6 is a flowchart showing the contents of an NMI interrupt processing program that occurs when the power supply voltage drops due to a power failure or the like. In this interrupt processing, first, the contents of each register (AF, I, BC, DE, HL) are pushed to the stack area (ST70). Next, the value of the stack pointer SP after execution of the PUSH instruction in step ST70 is stored in the SP storage area of the RAM (ST71). FIGS. 6B and 6C show the saving state of each register (AF, I, BC, DE, HL), stack pointer SP, and program counter PC.

  Subsequently, since there is a case where a prize ball is currently being paid out, the state of the prize ball counting switch is detected and stored (ST72). Note that waiting for a predetermined time (ST73) takes into account the time during which the prize ball being paid out moves. Although not shown in the figure, after necessary processing is performed, the flag value 5AH is stored in the RAM area of the backup flag BFL (ST74). Thereafter, access to the RAM is prohibited, the power supply voltage drops, and the CPU is turned off. Waiting for an operating state (ST75). After that, the CPU becomes non-operating, but since the backup power is supplied to the RAM, the backed up data continues to be stored as it is. That is, even after the power supply is completely shut down, the RAM area is maintained as shown in FIGS.

  Subsequently, the above-mentioned bullet ball game machine will be further described. FIG. 7 is a perspective view showing the pachinko machine 21 of this embodiment, and FIG. 8 is a side view of the pachinko machine 21. A plurality of pachinko machines 21 are arranged in the length direction of the island structure of the pachinko hall while being electrically connected to the card-type ball lending machine 22.

  The illustrated pachinko machine 21 includes a rectangular frame-shaped wooden outer frame 23 that is detachably mounted on an island structure, and a front frame 24 that is pivotably mounted via a hinge H fixed to the outer frame 23. It consists of A game board 25 is detachably attached to the front frame 24 from the back side, and a glass door 26 and a front plate 27 are pivotally attached to the front side so as to be freely opened and closed.

  The front plate 27 is provided with an upper plate 28 for storing game balls for launch. A lower plate 29 for storing game balls overflowing from or extracted from the upper plate 28 and a launch handle 30 are disposed below the front frame 24. And are provided. The launch handle 30 is linked to a launch motor, and a game ball is launched by a striking rod 31 (see FIG. 10) that operates according to the rotation angle of the launch handle.

  On the right side of the upper plate 28, an operation panel 32 for lending the ball to the card-type ball lending machine 22 is provided, and on this operation panel 32, a card remaining amount display unit 32a for displaying the remaining amount of the card with a three-digit number. A ball lending switch 32b for instructing lending of game balls for a predetermined amount, and a return switch 32c for instructing to return the card at the end of the game. On the upper part of the glass door 26, a big hit LED lamp P1 indicating a big hit state is arranged. In addition, in the vicinity of the big hit LED lamp P1, abnormality notification LED lamps P2 and P3 are provided to indicate a replenishment state or a full state of the lower plate.

  As shown in FIG. 9, the game board 25 is provided with a guide rail 33 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display 8 is provided at the approximate center of the game area 25a on the inside. Is arranged. In addition, at a suitable place in the game area 25a, a symbol start opening 35, a big winning opening 36, a plurality of normal winning openings 37, and gates 38 which are left and right passing openings are arranged. Each of these winning openings 35 to 38 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display 8 is a device that variably displays a specific symbol related to the big hit state, and displays a background image, various characters, and the like in an animated manner. This liquid crystal display 8 has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 39 in the upper right portion. The normal symbol display unit 39 displays a normal symbol. When a game ball that has passed through the gate 38 is detected, the displayed normal symbol fluctuates for a predetermined time, and a lottery is drawn at the time the game ball passes through the gate 38. The stop symbol determined by the random number for lottery is displayed and stopped.

  The symbol start opening 35 is opened and closed by an electric tulip having a pair of opening and closing claws 35a. When the stop symbol after fluctuation of the normal symbol display unit 39 is displayed and the symbol is displayed, the opening and closing claws 35a are opened for a predetermined time. It has come to be. When a game ball wins the symbol start opening 35, the display symbols of the special symbol display portions Da to Dc change for a predetermined time, and are determined based on a lottery result corresponding to the winning timing of the game ball to the symbol start opening 35. Stop at the stop symbol pattern.

  The special winning opening 36 is controlled to open and close by an openable opening / closing plate 36a. When the special symbol display portions Da to Dc have a special symbol such as “777” after the change is stopped, the special winning symbol 36 is referred to as “big hit”. A special game is started and the opening / closing plate 36a is opened. There is a specific area 36b inside the big winning opening 36, and when the winning ball passes through the specific area 36b, a special game advantageous to the player is continued.

  After the opening / closing plate 36a of the big winning opening 36 is opened, the opening / closing plate 36a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. At this time, if the game ball does not pass through the specific area 36b, the special game ends, but if it passes through the specific area 36b, the special game is continued up to, for example, 15 times, which is advantageous to the player. To be controlled. In addition, when the stop symbol after the change is a certain symbol (specific symbol) of the special symbol, a privilege of shifting to a high probability state is given after the special game ends.

  As shown in FIG. 10, on the back side of the front frame 24, a back mechanism plate 40 for holding the game board 25 from the back side is detachably mounted. An opening 40a is formed in the back mechanism plate 40, and a prize ball tank 41 and a tank rail 42 extending therefrom are provided on the upper side thereof. A payout device 43 connected to the tank rail 42 is provided on the side of the back mechanism plate 40, and a passage unit 44 connected to the payout device 43 is provided below the back mechanism plate 40. The game balls paid out from the payout device 43 are paid out to the upper plate 28 from the upper plate discharge port 28a (FIG. 7) via the passage unit 44.

  The opening 40a of the back mechanism plate 40 is fitted with a back cover 45 mounted on the back side of the game board 25 and a winning ball discharge basket (not shown) for discharging the game balls won in the winning holes 35 to 37. Has been. The main control board 1 is disposed inside the case CA1 attached to the back cover 45, and the symbol control board 2 is disposed on the front side thereof (see FIG. 8). Below the main control board 1, the lamp control board 4 is provided in the case CA2 attached to the back cover 45, and the sound control board 3 is provided in the adjacent case CA3.

  Below these cases CA2 and CA3, a power supply board 6 and a payout control board 5 are provided in a case CA4 mounted on the back mechanism plate 40. A power switch 53 and an initialization switch 54 are disposed on the power board 6. The parts corresponding to both the switches 53 and 54 are notched, and both switches can be operated simultaneously with a finger.

  Inside the case CA5 attached to the rear side of the launch handle 30, a launch control board 7 is provided. And these circuit boards 1-7 are each comprised independently, and the computer circuit provided with the one-chip microcomputer is mounted in the control boards 1-5 except the power supply board 6 and the launch control board 7. FIG. The main control board 1 and the other control boards 2 to 5 are electrically connected via a connector with a plurality of signal lines.

  As described above, in the gaming machine of this embodiment, a predetermined register is assigned to the jackpot counter IX instead of the RAM. Conventionally, since RAM was allocated, the big hit random number was also initialized by the system reset, and there was a possibility that the big hit occurrence timing could be known within at least one cycle. However, according to the gaming machine of this embodiment, it is illegal. Even if the system is forcibly reset by an action, the contents of the register functioning as the jackpot counter IX are not reset. Therefore, the occurrence timing of the big hit is not known and fraud cannot be performed.

  Although the present invention has been specifically described above, the specific description content does not particularly limit the present invention. For example, in the above embodiment, the CPU index register IX is assigned to the big hit counter CT, but other registers such as an IY register may be used instead of the IX register.

  Further, in the above-described embodiment, an example in which mask processing is performed in order to keep the value of the index register IX after power-on within a predetermined numerical range MAX has been described, but by shifting right by a predetermined bit instead of mask processing, It may be within the predetermined numerical range MAX.

  Further, in the above embodiment, the main control board 1 is connected to all the sub-control boards 2 to 5 in a radial manner. However, the present invention is not limited to this configuration, and various types including those illustrated in FIG. The connection method can be adopted. That is, the connection relationship between the main control board and the sub control board can be changed as appropriate, and transmission of the control command from the main control board may be performed via another sub control board. Further, not only unidirectional communication but also bidirectional communication may be used.

  For example, in FIG. 11A, first, a control command is transmitted from the main control board 1 to the symbol control board 2, and the symbol control board 2 that receives the control command controls the liquid crystal display and the like, as well as the voice control board 3 and lamp A control command is transmitted to the control board 4 to control speakers and lamps. At that time, as shown in FIG. 5B, the lamp control board and the voice control board may be combined as a single board (lamp voice control board) 99 so that bidirectional communication with the symbol control board 2 is possible. . Also, as shown in FIG. 5C, a control command is transmitted from the main control board 1 to the lamp sound control board 99, and the unidirectional or bidirectional communication between the lamp sound control board 99 and the symbol control board 2 is performed. The symbol control operation may be realized. Furthermore, as shown in FIG. 6D, each substrate for symbol control, voice control, and lamp control may be combined into a single substrate 98.

  Note that the present invention can also be applied to a rotating game machine. In this case, the switch input of the lottery process is a switch input for detecting the operation of the rotating operation lever of the spinning cylinder display unit (the display unit of the rotating reel).

It is a block diagram which shows the whole structure of the pachinko machine which concerns on an Example. It is a block diagram which shows the structure of a main control board. It is a flowchart which shows the system reset process in a main control board. It is a flowchart which shows the timer interruption process in a main control board. It is a flowchart which shows the update process of the big hit counter or the win counter. It is a flowchart which shows the MNI interruption process in a main control board. It is a perspective view of the pachinko machine concerning an example. It is a side view of the pachinko machine of FIG. It is a front view of the game board of the pachinko machine of FIG. It is a rear view of the pachinko machine of FIG. It is a block diagram which shows the board | substrate structure of the pachinko machine which concerns on another Example.

Explanation of symbols

1 Main control board 2-5 Sub control board 21 Game machines (pachinko machines, etc.)

Claims (4)

A backup power supply is provided to maintain the RAM data even after the power is shut off. When the power is turned on, the game operation before the power shutoff can be resumed. On the other hand, when the initialization switch is turned ON during the CPU reset operation. In a gaming machine configured to execute a RAM clear process for forcibly clearing data in the RAM,
After completing the initial process executed after the CPU reset, a system reset process that repeats an infinite loop process, a timer interrupt process activated every predetermined time, and a backup flag secured in the RAM when the power is dropped Backup processing to set the value, and
A main counter used in a random number lottery process for determining whether or not to generate a profit state advantageous to a player, and a sub-counter that is updated every predetermined time in the timer interrupt process and determines an initial value of the main counter And,
The main counter is composed of a 16-bit length register built in the CPU. On the other hand, every time the main counter circulates one or more times within a predetermined numerical range, the initial value of the subsequent circulation operation is Configured to be determined based on the value of the sub-counter,
In the initial process, even if the initialization switch is not turned on, if the backup flag is not a predetermined value, the RAM clear process is configured to be executed. Is not set to a fixed value even after the reset operation, and the numerical value is determined prior to the random number lottery process, and the numerical value is changed when the predetermined numerical value range is exceeded. gaming machine, characterized in that there.   The random number lottery process is performed based on a detection signal from a sensor that performs a predetermined detection in relation to the gaming state, and the random number for lottery is determined by the main counter obtained due to the detection of the detection signal. The gaming machine according to claim 1, wherein the gaming machine is a value. The value of the main counter, when it is determined to exceed the predetermined value range, the value of the main counter, characterized in that it is housed within a predetermined numerical range by the AND operation processing to shift operation process The gaming machine according to claim 1 or 2. The value of the main counter is changed to a value within the predetermined numerical range by setting unnecessary high-order bits to zero when it is determined that the value of the main counter exceeds the predetermined numerical range. A gaming machine according to any one of the above.

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