JP4399506B2 - Method for manufacturing wiring circuit member - Google Patents

Description

  The present invention relates to a method of manufacturing a wiring circuit member used for forming a printed circuit board using metal bumps formed on a main surface of a metal plate as an interlayer connection means.

  The applicant company has developed a technique for using metal bumps as an interlayer connection means as a multilayer wiring circuit board manufacturing technique. Specifically, an etching barrier layer (thickness, for example, 1 μm) made of nickel, for example, is formed on one main surface of a bump forming copper layer (thickness, for example, 100 μm), for example, and the etching barrier is further formed. Using, as a base, a printed circuit board forming member in which a copper foil (thickness, for example, 18 μm) for forming a conductor circuit is formed on the main surface of the layer and processing it appropriately, for example, fine protrusions for interlayer connection on the surface In this regard, for example, Japanese Patent Application No. 2000-230142 (Japanese Patent Laid-Open No. 2002-43506) and Japanese Patent Application No. 2000-334332 (Japanese Patent Laid-Open No. 2002-141629) are obtained. ), And Japanese Patent Application No. 2002-66410 (Japanese Patent Application Laid-Open No. 2002-43506).

  In manufacturing a printed circuit board utilizing such bumps, after forming bumps and forming an insulating layer for interlayer insulation that fills between the bumps, the top surface of the bumps is exposed by surface polishing to remove the bumps. It is necessary to be able to be used as an interlayer connection means. Further, after finishing the formation of the insulating layer for interlayer insulation and the polishing for exposing the bump top surface, copper or the like serving as a wiring film on the surface It is also necessary to laminate a metal plate (metal foil).

6A to 6D are cross-sectional views showing an outline of a method for manufacturing such a member for wiring circuit in the order of steps.
(A) A thin metal plate 104 having a three-layer structure composed of a copper metal foil 101, a nickel film 102, and a copper foil 103 is prepared, and a photoresist film is selectively formed on one main surface by exposure and development processing, Thereafter, a metal bump 105 for conductive between upper and lower wirings is prepared by selectively etching the main surface of the metal plate 104 using the selectively formed photoresist film as a mask.

  Next, the photoresist film is removed, and then an insulating sheet 106 made of, for example, an epoxy resin, a polyimide resin, a polyester resin, a bismaleimide triazine resin, a polyphenylene ether resin, a liquid crystal polymer, or the like, which becomes an insulating layer of a wiring layer, a synthetic resin Alternatively, a release sheet (first release sheet) 107 and a paper (second release sheet) 108 made of metal foil are prepared and faced above the bump forming side main surface of the metal plate 104. FIG. 6 (A) shows the state where it is faced.

(B) Next, as shown in FIG. 6 (B), the insulating sheet 106, release sheet 107 and paper 108 are applied to the metal bump forming side main surface of the metal plate 104 by flat plate vacuum hot pressing (hot pressing). Laminate.
(C) Next, the paper 108 is peeled off, and then the metal bump forming side main surface of the metal foil 101 is polished to expose the top surface of each metal bump 105. Thereafter, the release sheet 107 is peeled off. FIG. 6C shows the peeled state.

(D) Now, it can be said that the wiring circuit member is completed, but the insulating sheet 106 of this wiring circuit member is formed, and the metal plate (metal foil) 109 is placed on the surface where the top surface of the metal bump 105 is exposed. It can also be sold in a stacked state. FIG. 6D shows a state in which the metal plate 109 faces the main surface of the wiring circuit member so as to be laminated.
JP 2002-43506 A (Japanese Patent Application No. 2000-230142) JP 2002-141629 A (Japanese Patent Application No. 2000-334332) JP 2002-43506 A (Japanese Patent Application No. 2002-66410)

By the way, according to the above-described conventional technique, it is difficult to sufficiently increase the reliability of the connection between the metal bump 105 and the metal plate (metal foil) 109 and the insulation between the metal layer 109 and the metal foil 101. was there.
Then, when this inventor repeated experiment and thought in order to pursue the problem, it turned out that there are two causes. The first cause is that the insulating sheet 106 or the like cannot enter between the adjacent metal bumps 105 and 105 when the arrangement pitch of the metal bumps 105 is narrow, and the reliability of the insulation between the metal foil 101 and the metal plate 109 is unsatisfactory. This may be sufficient or the component of the insulating sheet 106 may remain on the top surface of the metal bump 105, which may hinder good connectivity between the metal bump 105 and the metal plate 109.

  The second cause is that the exposed top surface of each metal plate 105 is oxidized after the polishing step of the metal foil 101 and before the metal plate 109 is laminated, and the longer the oxidation time, the more the metal bump 105 and This is because good connectivity with the metal plate 109 is hindered.

  First, the first cause will be described in detail. As shown in FIG. 7A, the wiring circuit member is small when the arrangement density of the metal bumps 105 is constant, and if there is a low density region 110, there is also a high density region 112. As shown in FIG. 7B, since the space between the adjacent metal bumps 105 and 105 is wide in the low-density region 110, the insulating sheet 106, the release sheet 107, and the like are between the adjacent metal bumps 105 and 105. However, in the high-density region 112, since the interval between the adjacent metal bumps 105 and 105 is narrow, it cannot easily enter between the adjacent metal bumps 105 and 105. ) 114 may occur.

This is because, in an area where IC (semiconductor integrated circuit) is mounted, the distance between the bumps is particularly narrow. For example, when a bump pitch of 0.3 mm type is taken as an example, one side is high in a high density area. 1089 (33 × 33) bumps are arranged in a 10 mm square area (area 1 cm ² ), and even in an example where the bump pitch is 0.5 mm, one side is high in a high density area. There are cases where bumps are densely packed, such that 400 (20 × 20) bumps are arranged in a 10 mm square region (area 1 cm ² ).
The premise in these cases is that each bump has a base (base portion) having a diameter of 80 to 150 μm, a top surface having a diameter of 80 to 120 μm, a bump height of 80 to 125 μm, and bumps are formed (in other words, The thickness of the metal layer (copper foil) made of copper (which is the base of the bumps) is 12 to 18 μm.

  Therefore, in such an area where the bump pitch is narrow, the reliability of interlayer insulation by the insulating sheet 106 may be lowered. Further, the insulating sheet 106 or the like that should enter between the adjacent metal bumps 105 and 105 cannot enter, and after polishing, the components of the insulating sheet 106 exist on the top surface of the metal bump 105 as a residue. Therefore, there is a possibility that good connectivity with the metal plate 109 to be laminated is impaired. FIG. 7C shows a state after polishing, and black, 116, 116,... Indicate contamination due to the insulating sheet 106 component on the top surface of the metal bump 105. As shown in FIG. 7C, in the low density region 110, the top surface of the metal bump 105 is hardly contaminated, and in the high density region 112, the top surface of the metal bump 105 is dirty. 116 results.

Next, the second cause will be described in detail. Copper is easily oxidized, but after polishing to expose the top surface of the metal bump 105, the oxide film or the like is destroyed by the strong pressure applied when the metal plate 109 is laminated, and the metal bump 105 and the metal plate 109 are good. It has been considered that a good connectivity can be obtained.
However, it has been found that the reliability of connection varies greatly depending on the length of time until the metal plate 109 is laminated after the polishing, and a reliability decrease that cannot be ignored occurs after a certain time.

  The present invention has been made to solve such problems. After forming metal bumps on the surface of a metal plate and forming an insulating layer for interlayer insulation that fills the space between the metal bumps, the surface of the metal bumps is polished by surface polishing. Method for manufacturing wiring circuit member that exposes top surface to allow use of metal bump as means for interlayer connection, or wiring circuit in which metal plate (metal foil) is laminated on surface of wiring circuit member In the manufacturing method of the member for use, it is an object to further improve the reliability of the connection between the metal bump and the metal plate connected thereto and the reliability of the insulating layer for interlayer insulation.

  According to a first aspect of the present invention, there is provided a method for manufacturing a wiring circuit member on a surface of a metal plate on which a plurality of metal bumps having a conical shape or a trapezoidal shape are formed on the surface. The insulating sheet is laminated by heating and pressing, and the surface on which the insulating sheet is formed is polished so that the top surface of the metal bump is exposed, and then the metal bump of the metal plate is formed and the insulation is formed. The release sheet is laminated on the surface on which the sheet is laminated by heating and pressing, and then the surface on the side on which the insulating sheet is formed is polished together with the release sheet so that the top surface of the metal bumps is exposed. Thereafter, the release sheet is peeled off.

  In the method for manufacturing a wiring circuit member according to the second aspect of the present invention, the metal bump of the metal plate having a metal bump made of a plurality of copper having a conical shape or a trapezoidal shape on the surface is formed. An insulating sheet is laminated on the surface, and the surface on which the insulating sheet is formed is polished one or more times so that the top surface of the metal bump is exposed, and 6 hours after the last polishing. And a metal plate different from the metal plate connected to each metal bump is laminated on the surface of the metal plate on the side where the metal bump is formed.

According to the method for manufacturing a wiring circuit member of the first aspect of the present invention, after insulating sheets are laminated and then the surface on which the insulating sheets are formed is polished so that the top surfaces of the metal bumps are exposed. Then, the release sheet is laminated on the surface by heating and pressing, and then the surface on which the insulating sheet is formed is polished together with the release sheet so that the top surface of the metal bump is exposed. Can be completely filled with an insulating sheet so as not to generate voids, so that the reliability of interlayer insulation can be increased.
And by polishing twice instead of once, the top surface of the metal bump is more reliably exposed so that no residue remains on the metal bump and the connection between the metal bump and the metal plate laminated on the wiring circuit member. Can be more reliable.

  According to the method for manufacturing the wiring circuit member of the second aspect of the present invention, the metal bumps are formed on the surface of the metal plate on the side where the metal bumps made of copper are formed within 6 hours after the last polishing. The metal foil to be connected is laminated, and as shown in FIG. 4 and FIG. 5, if the copper surface is oxidized within 6 hours, the required reliability of connectivity will not be impaired. It is possible to ensure the reliability of connection between the metal plate laminated on the wiring circuit member.

According to the first aspect of the present invention, there is provided a method for manufacturing a member for a wiring circuit, in which an insulating sheet is laminated, and the top surface of the metal bump is exposed on the surface on which the insulating sheet is formed. Polishing is repeated twice, but as a material for a wiring circuit member, for example, a copper, nickel etching stop layer and a three-layer structure metal plate made of copper are optimal, and a copper foil on one main surface is used. It can be said that the metal bumps are preferably formed by selectively etching using the etching stop layer as an etching stopper.
However, a metal bump may be formed by preparing a single metal plate and half-etching (selective etching shallower than the thickness of the metal plate).
Moreover, as an insulating sheet, an epoxy resin, a polyimide resin, a polyester resin, a bismaleimide triazine resin, a polyphenylene ether resin, a liquid crystal polymer, etc. are suitable, for example.

According to the second aspect of the present invention, there is provided a method for manufacturing a wiring circuit member, wherein the metal is formed on the surface of the metal plate on which the metal bumps made of copper are formed within 6 hours after the last polishing. The metal foil to be connected to the bumps is laminated, and it can be said that the shorter the time from the polishing to the lamination of the metal plates, the better. However, if it is within 6 hours, the workability is particularly sacrificed. It can be said that there is no need to shorten it.
In the method for manufacturing a wiring circuit member according to the second aspect, basically, an insulating sheet is laminated, and the surface on which the insulating sheet is formed is polished so that the top surface of the metal bump is exposed. Can be applied to a method for manufacturing a member for a wiring circuit that is performed only once, but also to a method for manufacturing a member for a wiring circuit that is performed twice (a method for manufacturing a member for a wiring circuit according to the first aspect of the present invention). Can be applied.

Hereinafter, the present invention will be described in detail according to illustrated embodiments.
1 (A) to (D), FIGS. 2 (E) to (H) and FIGS. 3 (I) and 3 (J) show the first embodiment of the method for manufacturing a wiring circuit member of the present invention in the order of steps (A It is sectional drawing shown to (J).
(A) A wiring circuit member 2 having a three-layer structure consisting of a copper foil 4, a nickel layer 6, and a copper foil 8 that is a metal bump (8) thicker than the copper foil 4 is prepared, and the copper foil 8 is selectively etched. As a result, metal bumps 8 made of copper are formed. In this etching, the nickel layer 6 serves as an etching stopper and prevents the copper foil 4 from being etched. Thereafter, the nickel layer 6 is removed by etching using the metal bumps 8 made of copper as a mask.

Thereafter, an insulating sheet 14 serving as an interlayer insulating film, a release sheet (first release sheet) 16, and a paper (second release sheet) 18 are prepared and are exposed above the main surface on the bump forming side of the metal plate 1. I will. FIG. 1A shows this state. Reference numeral 10a denotes between the adjacent metal bumps 8 and 8 in the area 12a where the arrangement pitch of the metal bumps 8 is large. Reference numeral 10b denotes between the adjacent metal bumps 8 and 8 in the area 12b where the arrangement pitch of the metal bumps 8 is small. Show.
The insulating sheet 14 is made of, for example, epoxy resin, polyimide resin, polyester resin, bismaleimide triazine resin, polyphenylene ether resin, liquid crystal polymer, and the like, and the release sheet (first release sheet) 16 is made of synthetic resin or metal foil. The paper 18 is made of paper.

(B) Next, as shown in FIG. 1 (B), the insulating sheet 14, release sheet 16 and paper 18 are made of the metal by heating and pressurization, specifically, by flat plate vacuum hot pressing (hot pressing). It is laminated on the metal bump forming side main surface of the plate 1.
In the area 12a where the arrangement pitch of the metal bumps 8 is large, since the interval between the adjacent metal bumps 8 and 10a is wide, the insulating sheet 14 can enter the interval 10a. In the small area 12b, since the interval between the adjacent metal bumps 8 and 10b is narrow, the insulating sheet 14 cannot sufficiently enter the interval 10b. Reference numeral 20 denotes a space (void) that is generated when the adjacent metal bumps 8 and 8 cannot enter 10b. This space (that is, void) 20 hardly occurs in the area 12a where the arrangement pitch of the metal bumps 8 is large.

(C) Next, as shown in FIG. 1C, the uppermost paper 18 is peeled off.
(D) Next, as shown in FIG. 1D, the surface of the wiring circuit member 2 is polished. In this polishing, basically, there is a possibility that the component of the insulating sheet 14 or copper powder exists on the surface of the metal bump 8, particularly on the surface of the metal bump 8 in the area 12 b where the arrangement pitch of the metal bumps 8 is small. There is.
(E) Next, as shown in FIG. 2 (E), the release sheet 16 is peeled off.
In the prior art, after peeling off the release sheet 16, a metal plate to be a wiring layer is laminated. In this embodiment, the following steps (F) Repeat lamination and polishing of release sheet and paper. Therefore, the following steps (F) will be described.

(F) After the polishing, the wiring circuit member 2 in the state where the release sheet 16 has been peeled off, and the main surface from which the release sheet 16 has been peeled off, the release sheet (first release sheet) 26 and the paper (first 2 release sheet) 28 is prepared, and is exposed above the main surface of the metal plate 1 on the bump forming side. FIG. 2 (F) shows this state.
The release sheet (first release sheet) 26 and the paper (second release sheet) 28 are, for example, the same material as the release sheet 16 and the paper 18.

(G) Next, the release sheet (first release sheet) 26 and paper (second release sheet) 28 are laminated on the main surface of the wiring circuit member 2 by pressing and heating. Specifically, as in the case of the step (C), lamination is performed by flat plate vacuum hot pressing (hot pressing). In this lamination, the space (void) 20 formed between the adjacent metal bumps 8 and 8 in the area 12b where the arrangement pitch of the metal bumps 8 is small is the release sheet (first release sheet) laminated in this lamination step. ) 26 and the paper (second release sheet) 28 are filled with the insulating sheet 14 (insulated sheet already laminated in the previous laminating step) 14 pressed. Therefore, interlayer insulation can be made more perfect by the insulating sheet 14.
Thereafter, the outermost paper 28 is peeled off. FIG. 2G shows a state after the peeling.

(H) Next, the second polishing of the surface of the wiring circuit member 2 on the metal bump 8 formation side is performed. This polishing is performed until the top surface of each metal bump 5 is completely exposed.
In the process of the second lamination and polishing, the top surfaces of the metal bumps 8 in the area 12a where the arrangement pitch is large and those in the area 12b where the arrangement pitch is small are exposed in the process of the second lamination and polishing. The degree of contamination by the component (insulator component) of the insulating sheet 14 is extremely less than that at the stage where polishing is completed.
(I) Next, as shown in FIG. 3 (I), the release sheet 16 is peeled off.

(J) Next, a metal plate (copper foil) 30 made of copper is laminated on the main surface of the wiring circuit member. FIG. 3J shows a state where the metal plate 30 is faced to the main surface of the wiring circuit member to be laminated.
It can be said that this lamination is preferably performed after the second polishing step and before 6 hours have elapsed. FIG. 4 below shows test data indicating the preferable grounds. This test data includes the initial resistance when the metal plates are laminated at the time points of 0 hours (that is, immediately after polishing), 3 hours, 6 hours, 9 hours, and 12 hours after polishing, the resistance after the test, It is data about the rate of change of the resistance.

In the test, the initial resistance is a terminal resistance of a test pattern formed on the metal circuit laminated wiring circuit member 2 for the test. Specifically, the test pattern is a zigzag series circuit formed by connecting a predetermined number of the metal bumps 8 between the upper circuit and the lower circuit in series and viewing in a longitudinal section. The terminal resistance of the series circuit before imposing the severe conditions described below of the wiring circuit member 2 is the initial resistance.
The post-test resistance means that the metal plate laminated wiring circuit member 2 whose initial resistance has been measured is immersed in silicon oil at 260 ° C. for 10 seconds and then placed in a normal indoor space at room temperature for 10 seconds. This is the resistance between the metal bump and the metal plate measured 30 times and then measured. This test that imposes severe conditions is called a hot oil (HO) test. As described above, the rate of change is (resistance after test−initial resistance) × 100 / initial resistance (%). A change rate of-(minus) is when the post-test resistance is smaller than the initial resistance, and is within the measurement error range.

As shown in FIG. 4, the applicant company has established a strict test standard in which only a change rate of 5% or less is accepted. X was attached to% or more. Up to 6 hours, the rate of change was within 5% for all metal bumps, and there were no bumps that would be Δ or X.
However, at 9 hours, 60% of the bumps have a resistance change rate of 5% or less and ◯, but the remaining 40% have a change rate of 5 to 10%, and Δ is attached. Thus, it can be said that it is not desirable to have bumps marked with Δ. Moreover, although 70% of the bumps are ◯ even after 12 hours, the remaining 30% of the bumps are x, which is not preferable.

  FIG. 5 shows the relationship between the time until the metal plate lamination after the last polishing, the resistance value change rate, and the yield rate. When the time is up to about 6 hours, the yield is 100%, and the resistance change rate is also shown. It is apparent that it is preferably 2.5% or less and within 6 hours.

  INDUSTRIAL APPLICABILITY The present invention has general applicability to a method for manufacturing a wiring circuit member used for forming a printed circuit board using metal bumps as interlayer connection means.

(A)-(D) are sectional drawings which show process (A)-(D) of the manufacturing method 1st Example of the member for wiring circuit of this invention. (E)-(H) are sectional drawings which show process (E)-(H) of the 1st Example of the manufacturing method of the member for wired circuit of this invention. (I), (J) is sectional drawing which shows process (I)-(J) of the 1st Example of the manufacturing method of the member for wired circuits of this invention. After polishing in the above examples, 0 hours (that is, immediately after polishing), 3 hours, 6 hours, 9 hours, and 12 hours after the initial resistance when the metal plate is laminated, and the resistance after the test, The determination result regarding the change rate of the resistance and whether it is a non-defective product is shown. It is a figure which shows the relationship between time to metal plate lamination | stacking after said last grinding | polishing, a resistance value change rate, and a yield rate. (A)-(D) are sectional drawings which show process (A)-(D) of the prior art example of the manufacturing method of the member for wiring circuits in order. (A)-(C) is for demonstrating the problem of a prior art example, (A) is a top view of the area | region where the arrangement density of a metal bump is low, and a high density area, (B) is arrangement | positioning of a metal bump. Sectional drawing which shows the state after lamination | stacking of the insulating sheet of a low density area | region and a high density area | region, (C) is the top surface of the metal bump of the area | region where the arrangement | positioning density of a metal bump after lamination | stacking and grinding | polishing is low, and a high density area | region It is a top view which shows the degree of contamination.

Explanation of symbols

2 ... Wiring circuit member,
4 ... Metal foil,
6 ... nickel foil,
8 ... Metal bump,
10a, 10b ... the part between adjacent metal bumps 8 and 8,
12a: Area where the bump arrangement density is low,
12b: Area with high bump arrangement density,
14 ... Insulating sheet (interlayer insulating film),
16 ... release sheet,
18 ... paper,
20 ...
24. Insulating sheet (interlayer insulating film),
26 ... release sheet,
28 ... paper, 30 ... metal plate (copper foil).

Claims (1)

An insulating sheet is laminated by heating and pressurizing on the surface of the metal plate on which the metal bumps are formed on the surface of which a plurality of metal bumps having a conical shape or a trapezoidal shape are formed,
Polishing the surface on which the insulating sheet is formed so that the top surface of the metal bump is exposed ,
Next, the release sheet is laminated by heating and pressing on the surface of the metal plate on which the metal bumps are formed and the insulating sheet is laminated,
Then, the surface on which the insulating sheet is formed is polished so that the top surface of the metal bump is exposed together with the release sheet,
After that, peel off the release sheet ,
Within 6 hours after the last polishing, a metal plate different from the metal plate connected to the metal bumps is laminated on the surface of the metal plate on the side where the metal bumps are formed. A method for manufacturing a wiring circuit member.

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