JP4398467B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4398467B2 JP4398467B2 JP2006535065A JP2006535065A JP4398467B2 JP 4398467 B2 JP4398467 B2 JP 4398467B2 JP 2006535065 A JP2006535065 A JP 2006535065A JP 2006535065 A JP2006535065 A JP 2006535065A JP 4398467 B2 JP4398467 B2 JP 4398467B2
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- film
- resist pattern
- etching
- protective film
- gate electrode
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- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Description
本実施の形態の半導体装置の製造工程を図面を参照して説明する。図1〜図6は、本発明の一実施の形態である半導体装置、例えばMISFET(Metal Insulator Semiconductor Field Effect Transistor)、の製造工程中の要部断面図である。
本実施の形態では、上記実施の形態1と同様にしてゲート電極5aを形成することができるが、上記ステップS4,S5,S6の各工程において半導体基板1の温度および温度分布を制御する。なお、ステップS4〜S6の各工程は、半導体基板1の温度および温度分布以外は上記実施の形態1と同様であるので、ここではその説明は省略する。
本実施の形態では、上記実施の形態1と同様にしてゲート電極5aを形成することができるが、上記ステップS4の保護膜23の堆積レート、ステップS5の保護膜23(および反射防止膜21)のエッチングレート、およびステップS6の多結晶シリコン膜5のエッチングレートの半導体基板面内分布を制御することにより、ゲート電極5aのゲート長の半導体基板面内分布を制御する。なお、ステップS4〜S6の各工程は、保護膜23の堆積レート、保護膜23(および反射防止膜21)のエッチングレート、および多結晶シリコン膜5のエッチングレートの半導体基板面内分布以外は上記実施の形態1と同様であるので、ここではその説明は省略する。
上記実施の形態1では、有機系の反射防止膜21を用いているが、本実施の形態では、有機系の反射防止膜21の代わりに無機系の反射防止膜21aを用いている。従って、上記実施の形態1では、反射防止膜21は炭素を含有する有機材料からなるが、本実施の形態では、反射防止膜21aは炭素を含有しない無機材料(無機系の絶縁材料、例えば酸窒化シリコン膜など)からなる。
上記実施の形態1では、レジストパターン22として、ArFリソグラフィ対応のレジストパターンを用いているが、本実施の形態では、ArFリソグラフィ対応のレジストパターン22の代わりに、電子線リソグラフィを用いたレジストパターン22aを用いている。また、本実施の形態では、電子線リソグラフィを用いてレジストパターン22aを形成するので、反射防止膜21の形成は省略することができる。
上記実施の形態1では、多結晶シリコン膜5上に反射防止膜21およびレジストパターン22を形成しているが、本実施の形態では、多結晶シリコン膜5上にハードマスク用の絶縁膜24を形成し、絶縁膜24上に反射防止膜21およびレジストパターン22を形成している。
上記実施の形態1では、多結晶シリコン膜5をパターニングしてゲート電極5aを形成しているが、本実施の形態では、多結晶シリコン膜5の代わりに金属膜25を用い、この金属膜25をパターニングして金属ゲート電極としてのゲート電極5bを形成している。
上記実施の形態1では、ゲート電極の形成工程に本発明を適用しているが、本実施の形態では、素子分離領域2用の素子分離溝2aを形成する工程に、本発明を適用している。
上記実施の形態1では、ゲート電極の形成工程に本発明を適用しているが、本実施の形態では、配線14を形成する工程に、本発明を適用している。
上記実施の形態1では、ゲート電極の形成工程に本発明を適用しているが、本実施の形態では、絶縁膜への開口部(孔または溝)の形成工程に、本発明を適用している。
上記実施の形態1では、多結晶シリコン膜5のような導電体膜をパターニングすることでゲート電極5aを形成しているが、本実施の形態では、多結晶シリコン膜5のような導電体膜をパターニングすることでダミーゲート電極5cを形成し、その後ダミーゲート電極5cを除去することで形成された開口部(溝)に導電体膜を埋め込んで埋込み型のゲート電極5dを形成する。
Claims (9)
- 以下の工程を有することを特徴とする半導体装置の製造方法;
(a)被加工層を有する半導体基板を準備する工程、
(b)前記被加工層上にレジストパターンを形成する工程、
(c)前記被加工層上に前記レジストパターンを覆うようにガスを用いて第1材料膜を堆積する工程、
(d)前記第1材料膜の少なくとも一部を除去する工程、
(e)前記(d)工程後、前記レジストパターンおよび前記第1材料膜の残存部分をエッチングマスクとして、前記被加工層をエッチングする工程。 - 請求項1記載の半導体装置の製造方法において、
前記(d)工程では、前記第1材料膜の全部を除去し、
前記(e)工程では、前記レジストパターンをエッチングマスクとして、前記被加工層をエッチングすることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程では、フロロカーボン系のガスを含むガスを用いたプラズマにより前記第1材料膜を形成することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程では、前記半導体基板にバイアス電圧を印加することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(d)工程では、前記半導体基板にバイアス電圧を印加することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程における前記半導体基板面内の温度差が、前記(e)工程における前記半導体基板面内の温度差よりも小さいことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程における前記第1材料膜の堆積膜厚の前記半導体基板の面内分布に応じて、前記(d)工程において前記第1材料膜のエッチングレートの前記半導体基板の面内分布を制御することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記被加工層は、シリコン層、金属材料層または絶縁層からなることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(b)〜(e)工程は、ゲート電極を形成するために行われることを特徴とする半導体装置の製造方法。
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