JP4388828B2 - Circuit verification device - Google Patents

Description

  The present invention relates to a circuit verification apparatus, and more particularly to a technique that is effective when applied to a circuit verification apparatus that verifies whether or not a static through current is generated or a device withstand voltage violation occurs in a large-scale circuit. .

  For example, examples of a verification device (circuit verification device) for a circuit include an analog circuit simulator and a logic circuit simulator that set an input waveform or the like and check the operation of the circuit. In addition, as a verification device (layout verification device) for a layout, an ERC (Electric Rule Check) device that performs verification such as open and short, a DRC (Design Rule Check) device that performs design rule verification, a circuit and a layout And LVS (Layout Versus Schematic check) for verifying the match between the device extracted from the network and the net, and a device for verifying noise.

  By the way, as a result of examination by the inventor of the verification device technology as described above, the following has been clarified.

  For example, in the verification apparatus as described in the background art, it is considered that the circuit verification apparatus has fewer items that can be verified than the layout verification apparatus. However, in order to increase the efficiency of design development, it is desirable to find as many defects as possible at the stage of circuit verification. On the other hand, the layout verification device has a relatively large number of items that can be verified and can detect many problems, but problems such as processing time may occur when targeting large-scale circuits. Can be considered.

  Under such circumstances, a method using an analog circuit simulator or the like can be cited as a method for verifying whether or not an unintended static through current such as a logic circuit is generated due to a design error in the circuit verification device. In this method, for example, it can be said that verification is generally performed by setting, for example, an input waveform and designating a location where current measurement is performed on the circuit. However, with this method, it takes a great deal of time to specify the location where the through current is generated, and in some cases, the generation of the through current may be overlooked. In other words, in order to identify the location where the through current is generated, it is necessary to gradually narrow down the circuit block for current measurement, and depending on the conditions of the input waveform set when verifying the through current The occurrence itself may be overlooked.

  Further, as semiconductor products are miniaturized, the design considering the breakdown voltage of transistors becomes more and more important. However, when designing a circuit having multiple power supplies, for example, a situation in which a design that violates the breakdown voltage of the transistor may occur due to a design error or the like. Therefore, a method for detecting such a simple design mistake at an early stage is desired.

  Therefore, the object of the present invention is to verify whether or not an unintended static through current is generated due to a design error or the like, and whether or not a breakdown voltage of a transistor is generated, particularly for a large-scale circuit, and to easily identify the occurrence location. It is an object of the present invention to provide a circuit verification device capable of satisfying the requirements.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the circuit verification device according to the present invention, circuit connection information and voltage value information of a fixed voltage terminal in the circuit are input, and the input information is referred to and the voltage value of each terminal of the transistor in the circuit is referred to. The transistor that is fixed to OFF is compared with the function for identifying the transistor that is fixed to OFF, and the input information is referred to, and the transistors other than those that are fixed to OFF are regarded as ON. Having a function of transmitting through a transistor regarded as ON, and a function of performing error determination for each transistor by referring to the voltage value of each terminal of the transistor after transmitting the voltage value of the terminal of the fixed voltage It is.

  That is, paying attention to the voltage value of the power supply terminal, the reference potential terminal, etc., the voltage value is simply transmitted through the transistor, and the error determination is performed by referring to the voltage value of each terminal of the transistor after the transmission. Is. As described above, since error determination is performed with simple processing, high-speed processing and the like are possible, and it is easily applicable to a large-scale circuit. Further, the position of the transistor in which the error has occurred can be easily specified.

  Here, for example, the transmission function is for the first conductivity type transistor among the transistors regarded as ON, and the transmission is performed so that each terminal of the first conductivity type transistor has the highest voltage value. A first function and a second function for transmitting a second conductivity type transistor so that each terminal of the second conductivity type transistor has the lowest voltage value among transistors regarded as ON; And the error determination function is ON with reference to the voltage values of the terminals of the first conductivity type and second conductivity type transistors after the voltage value of the fixed voltage terminal is transmitted. Or a transistor of the first conductivity type and the second conductivity type in which a forward diode is formed on the substrate terminal is determined as an error. This makes it possible to verify whether static through current is generated.

  In addition, the circuit verification device further receives information on the breakdown voltage value of the transistors in the circuit, and transmits the function so that each terminal of the transistor regarded as ON has the highest voltage value. The function of determining the error having a third function refers to the voltage value of each terminal of the transistor in the circuit after transmitting the voltage value of the terminal of the fixed voltage, and the input in the circuit This is compared with the withstand voltage information of the transistors in the circuit to determine the presence or absence of a withstand voltage violation of the transistors in the circuit.

  By the way, more specifically, the function of transmitting refers to, for example, voltage value information of the terminal of the input fixed voltage, and rearranges the voltage values in order of high or low, and the fixed voltage. A function for determining the voltage value of each terminal of the transistor, and a function for determining whether or not the voltage value of each terminal of the transistor is determined for a transistor that has transmitted the voltage value of the terminal of the transistor even once. Is included. Thus, by determining whether or not the voltage value of each terminal of the transistor is fixed in the order of the rearranged voltage values, each terminal of the transistor is made to transmit to the target transistors that are not fixed. The highest voltage value or the lowest voltage value can be obtained.

  The circuit verification device further has a function of determining whether or not a transistor that is designated as an error by the function of performing the error determination and a transistor indicated by the specified error list are the same when the specified error list is input. Is. As a result, more detailed error information can be added to the transistors indicated in the specified error list.

  It is possible to realize a circuit verification device capable of verifying whether or not a static through current has occurred and whether or not a transistor withstand voltage violation has occurred, and in the event of an error, the position of the transistor can be easily identified. it can. In addition, this circuit verification device can perform high-speed processing and can be easily applied to a large-scale circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram showing an example of the configuration of a circuit verification apparatus according to an embodiment of the present invention. The circuit verification apparatus shown in FIG. 1 includes, for example, an input data unit 10, a data processing unit 11, an output data unit 12, and the like. The input data unit 10 includes circuit data 10a, signal potential data 10b, and device parameters 10c. The data processing unit 11 includes a circuit development processing unit 11a, a power transmission processing unit 11b, and a device determination unit 11c. The output data unit 12 includes a gate-to-source error, a source-to-substrate error, and a device power supply withstand voltage. Error report files 12a, 12b, and 12c corresponding to the errors are included.

  The circuit verification device is realized by a computer system, and the input data unit 10 and the output data unit 12 are realized by a storage medium such as a hard disk, and the data processing unit 11 includes a storage medium such as a memory and a CPU (Central This is realized by a processing unit).

  The circuit data 10a is, for example, a transistor level netlist (circuit connection information) extracted from a circuit diagram or layout, and other transistors such as PMOS and NMOS, other elements such as resistors and capacitors, each power supply terminal, and the like. Connection information between each internal voltage terminal and the like is included. The signal potential data 10b includes information on voltage values at fixed voltage terminals such as a power supply terminal and an internal voltage terminal included in the circuit data 10a. The device parameter 10c includes information on transistor characteristics such as a transistor model (high withstand voltage / standard withstand voltage specification, etc.), withstand voltage information, threshold voltage Vth, and the like in the circuit data 10a.

  The circuit development processing unit 11a organizes each data of the input data unit 10 and develops it into data focusing on each device (transistor) as shown in FIG. In FIG. 2, each of the devices # 1 to #n is a MOS transistor, and device data for each MOS transistor is collected. This device data includes, for example, a gate net, a source net, a drain net, a bias net, and a model. As a result, the gate terminal, source terminal, drain terminal and substrate terminal of each MOS transistor are connected to each other, and whether the MOS transistor is a PMOS transistor or an NMOS transistor, a high breakdown voltage specification or a standard breakdown voltage specification, etc. I understand.

  The power transmission processing unit 11b refers to the gate net, source net, drain net and bias net on the device data, and the signal potential data 10b, and the voltage value of the fixed voltage terminal is connected to the terminal By sequentially transmitting through the device, a process of determining the voltage value of each terminal of the device is performed.

  After determining the voltage value of each terminal of each device by the power transmission processing unit 11b, the device determination unit 11c refers to the voltage value of each terminal and compares the voltage value between the terminals to Detect a device that has a typical through current or breakdown voltage error. The device determination unit 11c then outputs to the output data unit 12 an error report file including information such as the content of the error and the hierarchical device name and position of the device in which the error has occurred.

  Here, more specific operations of the power transmission processing unit 11b and the device determination unit 11c will be described. First, as a representative example in the case where static through current can occur, for example, the following cases (1) and (2) can be considered, and a representative example in the case where occurrence of a device withstand voltage violation can occur. For example, the following (3) may be considered.

(1) When a gate-to-source error occurs In a PMOS transistor, the maximum voltage at its gate terminal is lower than the maximum voltage at its source and drain terminals, or in the NMOS transistor, the minimum voltage at its gate terminal is When the voltage becomes higher than the minimum voltage of the source and drain terminals, the transistor is turned on in a static state, and a through current can be generated. An example of the circuit in this case is shown in FIG.

  Note that the circuit symbols used in the description of this embodiment including FIG. 4 and the like are defined in advance in FIG. In FIG. 3, for each of the PMOS transistor and the NMOS transistor, a circuit symbol having a standard breakdown voltage and a circuit symbol having a high breakdown voltage are defined.

  FIG. 4 is a diagram illustrating an example of a circuit that causes a gate-to-source error in the circuit verification apparatus according to the embodiment of the present invention. FIG. 4A illustrates an example of a circuit that causes an error when the input is not fixed. ) Shows an example of a circuit that causes an error when the input is fixed to “H”, and (c) shows an example of a circuit that causes an error when the input is fixed to “L”.

  4A to 4C, a power supply terminal Vdd and a reference potential terminal Vss serving as fixed voltage terminals are provided, and a fixed voltage is applied to a CMOS circuit 400 including a standard breakdown voltage specification PMOS transistor MP40 and NMOS transistor MN40. A CMOS circuit 401 having a power supply terminal Vpp and a reference potential terminal Vbb which are high-voltage-specification PMOS transistors MP41 and NMOS transistors MN41 is connected by a design error or the like.

  Therefore, when the input of the CMOS circuit 400 in FIG. 4A is at the “H” level, or when the input of the CMOS circuit 400 is fixed at the “H” level as shown in FIG. The MN 40 is turned on and the input of the CMOS circuit 401 becomes 0.0V. However, the transistor MN41, which is supposed to be turned off, is turned on because the voltage value of the reference potential terminal (source terminal) Vbb is −2.0 V, and in the static state, the transistor MN41 is turned on from the power supply terminal Vpp of the CMOS circuit 401. A through current is generated at the potential terminal Vbb.

  In addition, when the input of the CMOS circuit 400 in FIG. 4A is at the “L” level, or when the input of the CMOS circuit 400 is fixed at the “L” level as shown in FIG. 4C, the PMOS transistor MP40. Becomes ON, and the input of the CMOS circuit 401 becomes 1.5V. However, the transistor MP41 that is supposed to be turned off is turned on because the voltage of its power supply terminal (source terminal) Vpp is 3.3V, and in a static state, the transistor MP41 is turned on from the power supply terminal Vpp of the CMOS circuit 401 to the reference potential terminal Vbb. Through current is generated in

(2) When a source-to-substrate error occurs In a PMOS transistor, when the voltage of its substrate (N-type well) is lower than the minimum voltage of its source and drain terminals, or in the NMOS transistor, its substrate (P-type) When the voltage of the well) is higher than the maximum voltage of the source and drain terminals, a forward-biased parasitic diode is formed between the source / drain terminals and the substrate, and a static through current can be generated. An example of this is shown in FIG.

  FIG. 5 is a diagram illustrating an example of a circuit that causes a source-to-board error in the circuit verification apparatus according to the embodiment of the present invention. In FIG. 5, high breakdown voltage specification PMOS transistors MP50 and MP51 and high breakdown voltage specification NMOS transistors MN50 and MN51 are connected from the power supply terminal Vpp to the reference potential terminal Vbb. ) Is connected to the power supply terminal Vpp, and the substrate terminal of the NMOS transistor MN51 is connected to the reference potential terminal Vbb. However, due to a design error or the like, the substrate terminal of the PMOS transistor MP51 is connected to the power supply terminal Vdd, and the substrate terminal of the NMOS transistor MN50 is connected to the reference potential terminal Vss.

  As a result, when either the PMOS transistor MP50 or the NMOS transistor MN51 is turned on, in the static state, between the source terminal (3.3V) and the substrate terminal (1.5V) of the PMOS transistor MP51, the NMOS A forward parasitic diode is formed between the source terminal (−2.0 V) and the substrate terminal (0.0 V) of the transistor MN50, and a through current is generated.

(3) When a device power supply withstand voltage error occurs When a maximum voltage is applied to each terminal of a PMOS and NMOS transistor, device destruction occurs. An example of this is shown in FIG.

  FIG. 6 is a diagram illustrating an example of a circuit detected as a device power supply withstand voltage error in the circuit verification apparatus according to the embodiment of the present invention. FIG. 6A is an example of a circuit detected when the input is not fixed. (B) is a figure which shows an example of the circuit detected when an input is fixed to "H".

  6 (a) and 6 (b), a power supply terminal Vdd and a reference potential terminal Vss are provided in a CMOS circuit 600 having a power supply terminal Vpp and a reference potential terminal Vbb and comprising a high breakdown voltage specification PMOS transistor MP60 and NMOS transistor MN60. And a CMOS circuit 601 composed of a PMOS transistor MP61 and an NMOS transistor MN61 with standard breakdown voltage specifications are connected due to a design error or the like.

  For this reason, when the input of the CMOS circuit 600 in FIG. 6A is at the “L” level or when the input is fixed to the “L” level (not shown), the PMOS transistor MP60 is turned on, and the CMOS circuit 601 is turned on. The input is 3.3V. However, this voltage exceeds the gate withstand voltage values of the PMOS and NMOS transistors MP61 and MN61 in the CMOS circuit 601, and device breakdown can occur in these transistors.

  Further, when the input of the CMOS circuit 600 in FIG. 6A is at the “H” level or when the input is fixed at the “H” level as shown in FIG. 6B, the NMOS transistor MN60 is turned on and the CMOS circuit is turned on. The input of 601 is -2.0V. However, this voltage exceeds the gate withstand voltage value of the PMOS transistor MP61 or NMOS transistor MN61 in the CMOS circuit 601, and device breakdown can occur in this transistor.

  Therefore, in order to detect these errors (1) to (3), the power transmission processing unit 11b and the device determination unit 11c perform, for example, processing as shown in FIG. FIG. 7 is a processing flowchart showing an example of the operation of the apparatus of FIG. 1 in the circuit verification apparatus according to the embodiment of the present invention. Hereinafter, the processing flow shown in FIG. 7 will be described.

  In S700, the power transmission processing unit 11b sorts the power signals. That is, the voltage values of the fixed voltage terminals based on the signal potential data 10b of FIG. 1 are rearranged in the order of high or low according to the contents to be verified. Then, the process proceeds to S701.

  In step S <b> 701, the power transmission processing unit 11 b ignores the OFF-fixed device. That is, the device fixed to OFF is recognized from the voltage value of the terminal of the fixed voltage based on the signal potential data 10b of FIG. 1 and the device data of FIG. In the subsequent processing, the voltage value is not transmitted to this device, and a device connected only to this device is not determined as a gate-to-source error. That is, for example, the situation shown in FIGS. 8 and 9 is meant. FIG. 8 is a diagram illustrating an example of a circuit that does not need to be detected as a gate-to-source error in the circuit verification apparatus according to the embodiment of the present invention. FIG. 9 is a diagram illustrating an example of a circuit that does not need to be detected as a source-to-board error in the circuit verification apparatus according to the embodiment of the present invention.

  In FIG. 8, in addition to the configuration of FIG. 4 which is an example of the gate-to-source error, a fixed device OFF (high voltage-resistant PMOS transistor) MP82 is connected to the power supply terminal Vpp side. The PMOS transistor MP82 can be recognized as being fixed OFF because the gate terminal and the source terminal are both connected to the power supply terminal Vpp (3.3V). In the case of FIG. 8, since no static through current is generated as in FIG. 4, it is not necessary to detect the NMOS transistor MN81 as a gate-to-source error.

  In addition, in FIG. 9, the device on the power supply terminal Vpp side (PMOS transistor with high breakdown voltage specification) MP90 and the device on the reference potential terminal Vbb side (with high breakdown voltage specification) are compared to the configuration in FIG. (NMOS transistor) MN91 is fixed OFF. The PMOS transistor MP90 has both a gate terminal and a source terminal connected to the power supply terminal Vpp (3.3V), and the NMOS transistor MN91 has both a gate terminal and a source terminal connected to the power supply terminal Vbb (−2.0V). Therefore, both can be recognized as OFF fixed. In the case of FIG. 9, a static through current toward the substrate as shown in FIG. 5 does not occur in the high breakdown voltage specification PMOS transistor MP91 and the high breakdown voltage specification NMOS transistor MN90. There is no need to detect.

  Then, when detecting an error of static through current generation in the PMOS transistor, the process proceeds to S710, and when detecting an error of static through current generation in the NMOS transistor, the process proceeds to S720. When detecting the device breakdown voltage violation of the NMOS transistor, the process proceeds to S730.

  In S710, the power transmission processing unit 11b shorts the source / drain terminals of the PMOS transistor in order of increasing voltage value and transmits the voltage value of the fixed voltage terminal. That is, the PMOS transistor (first conductivity type transistor) is recognized from the device data of FIG. 2, and the PMOS transistors other than those fixed to OFF are regarded as ON. Then, for example, it is determined whether or not the source net in FIG. 2 is connected to a power supply terminal (fixed voltage terminal). If it is connected, the voltage value of the power supply terminal is regarded as ON. Transmission is performed via a PMOS transistor.

  At this time, for example, such a process is performed first from a power supply terminal having a high voltage value, and the second transfer process is not performed for the PMOS transistor that has been transferred even once. Thus, each terminal of the PMOS transistor has the highest voltage value it can take (first function). For example, the processing here will be described with reference to FIG. 4A. First, the voltage value 3.3 V of the power supply terminal Vpp is transmitted to the node ND41 via the PMOS transistor MP41. Next, the voltage value of 1.5 V at the power supply terminal Vdd is transmitted to the node ND40 via the PMOS transistor MP40. Then, the process proceeds to S711.

  In step S711, the device determination unit 11c detects an error in the generation of a static through current of the PMOS transistor. That is, after the voltage value is transmitted, the gate-source error as shown in FIG. 4 and the source-to-substrate error as shown in FIG. 5 are detected by referring to the voltage values of the respective terminals of the PMOS transistor. At this time, a transistor whose source terminal or drain terminal is in a floating state is not detected as a gate-to-source error in relation to the transistor fixed at OFF.

  For example, the process here will be described with reference to FIG. 4A. After the process of S710, the voltage value of 3.3 V of the source terminal (power supply terminal Vpp) of the PMOS transistor MP41 and the gate terminal (node ND40) The voltage value is compared with 1.5V. As a result, this transistor is determined to be ON, and is detected as a gate-to-source error.

  In S720, the power transmission processing unit 11b shorts the source / drain terminals of the NMOS transistor in order of the lower voltage values, and transmits the voltage value of the fixed voltage terminal. That is, the NMOS transistor (second conductivity type transistor) is recognized from the device data shown in FIG. 2, and the NMOS transistors other than those fixed to OFF are regarded as ON. Then, for example, it is determined whether or not the source net of FIG. 2 is connected to a reference potential terminal (fixed voltage terminal). If connected, the voltage value of the reference potential terminal is set to ON. It is transmitted through the regarded NMOS transistor.

  At this time, for example, such a process is performed first from a reference potential terminal having a low voltage value, and the second transfer process is not performed on the NMOS transistor that has been transferred even once. Thus, each terminal of the NMOS transistor has the lowest voltage value it can take (second function). For example, the processing here will be described with reference to FIG. 4A. First, the voltage value −2.0 V of the reference potential terminal Vbb is transmitted to the node ND41 via the NMOS transistor MN41. Next, the voltage value 0.0V of the reference potential terminal Vss is transmitted to the node ND40 through the NMOS transistor MN40. Then, the process proceeds to S721.

  In step S721, the device determination unit 11c detects an error in static through current generation of the NMOS transistor. That is, after the voltage value is transmitted, the gate-source error as shown in FIG. 4 and the source-to-substrate error as shown in FIG. 5 are detected by referring to the voltage values at the respective terminals of the NMOS transistor. At this time, a transistor whose source terminal or drain terminal is in a floating state is not detected as a gate-to-source error in relation to the transistor fixed at OFF.

  For example, the processing here will be described with reference to FIG. 4A. After the processing of S720, the voltage value −2.0 V of the source terminal (reference potential terminal Vbb) of the NMOS transistor MN41 and the gate terminal (node ND40). ) Is compared with a voltage value of 0.0V. As a result, this transistor is determined to be ON, and is detected as a gate-to-source error.

  In S730, the power transmission processing unit 11b short-circuits the source / drain terminals of the MOS (PMOS, NMOS) transistors in order of higher voltage values and transmits the voltage values of the fixed voltage terminals. That is, MOS transistors other than those fixed to OFF are regarded as ON. Then, for example, it is determined whether or not the source net of FIG. 2 is connected to a fixed voltage terminal, and if it is connected, the voltage value of the fixed voltage terminal is regarded as ON. Communicate through.

  At this time, for example, such a process is performed first from a power supply terminal having a high voltage value, and the second transmission process is not performed on the MOS transistor that has performed the transmission process even once. Thus, each terminal of the MOS transistor has the highest voltage value it can take (third function). Then, the process proceeds to S731.

  In S731, the device determination unit 11c detects a device breakdown voltage violation of the MOS transistor. That is, after the voltage value is transmitted, the voltage value of each terminal of the MOS transistor is referred to and compared with the device parameter (voltage value information) of the transistor, thereby detecting a device power supply withstand voltage error as shown in FIG. .

  Further, an example in which the processing flow of the power transmission processing unit 11b and the device determination unit 11c as described above is made more concrete is shown in FIGS. FIG. 10 is a process flow diagram showing an example of detailed operations of the power transmission processing unit and the device determination unit of FIG. 1 in the circuit verification apparatus according to the embodiment of the present invention, and showing the processing of the main routine. . 11 shows an example of detailed operations of the power transmission processing unit and the device determination unit in FIG. 1 in the circuit verification apparatus according to the embodiment of the present invention, and is a processing flow diagram showing processing of the subroutine in FIG. It is.

  In the description of FIGS. 10 and 11, a case where a device power supply withstand voltage error is detected using the circuit shown in FIG. 12, for example, will be described as an example. FIG. 12 is a diagram illustrating an example of a circuit for explaining the operations of FIGS. 10 and 11 in the circuit verification device according to the embodiment of the present invention.

  First, in the circuit shown in FIG. 12, high breakdown voltage specification PMOS transistors D # 1 and D # 2 are connected in series between a power supply terminal Vpp and a node N2, and a standard breakdown voltage is connected between the power supply terminal Vdd and the node N2. A specification PMOS transistor D # 3 is connected, and a standard breakdown voltage specification NMOS transistor D # 4 is connected between the node N2 and the reference potential terminal Vss. The gate terminal inputs of these transistors are variable.

  In the case of this circuit, when the PMOS transistors D # 1 and D # 2 are turned ON, the node N2 becomes 3.3 V. Therefore, device breakdown occurs in the standard breakdown voltage specification transistors D # 3 and D # 4. Possible occurrence. However, in the prior art, since it is necessary to perform various verifications by giving a pattern to each gate terminal input, for example, verification is performed with a pattern in which the transistors D # 1 and D # 2 are OFF (the gate terminal input is 'H'). There was a problem that a verification failure occurred when performing the above.

  However, if the processing flow as described in FIG. 7 is used, in this case, since the processing is performed first from the power supply terminal having a high voltage value, the voltage value of the node N2 at the time of verification can be set to 3.3V. . That is, in more detail, for example, a main routine flow as shown in FIG. 10 described below may be performed.

  In S100, the power transmission processing unit 11b sorts the voltage values of the fixed voltage terminals based on the signal potential data 10b of FIG. 1 in the order of the voltage values. In the example of FIG. 12, sorting is performed in the order of high voltage values. Then, the process proceeds to S101.

  In S101, the power transmission processing unit 11b sets the attention potential to the first voltage value. In the example of FIG. 12, the highest voltage value is set to 3.3V. Then, the process proceeds to S102.

  In S102, the power transmission processing unit 11b performs a check process (subroutine) shown in FIG. 11 on the device connected to the target potential. In the example of FIG. 12, the subroutine of FIG. 11 is executed for the transistor D # 1 connected to 3.3V. In the example of FIG. 12, there is one transistor connected to 3.3V, but when there are a plurality of transistors, the subroutine is executed for all of them. After executing this subroutine, the process returns to S103.

  In S103, the power transmission processing unit 11b determines whether there is another voltage value. If there is, the process proceeds to S104, and if not, the process proceeds to S105.

  In S104, the power transmission processing unit 11b sets the target potential to the next voltage value. In the example of FIG. 12, it is set to 1.5 V, which is the next highest voltage value.

  In S105, the device determination unit 11c sets the target device as the first device. Then, the process proceeds to S106.

  In S106, the device determination unit 11c determines whether or not there is an error in the device of interest. That is, with reference to the voltage value of each terminal of the device of interest, the presence or absence of a gate-to-source error, a source-to-substrate error, or a device power supply withstand voltage error is determined. If there is an error, the process proceeds to S107, and if not, the process proceeds to S108.

  In S107, the device determination unit 11c outputs an error report file. This error report file includes the content of an error such as a gate-to-source error and the location of the device where the error occurred. Then, the process proceeds to S108.

  In S108, the device determination unit 11c determines whether there is another device. If yes, the process proceeds to S109, and if not, the process ends.

  In S109, the device determination unit 11c sets the target device as the next device. Then, the process proceeds to S106.

  The contents of the subroutine flow shown in FIG. 11 will be described below.

  In step S1020, the power transmission processing unit 11b sets the target device as the first device. In the example of FIG. 12, when the target potential is 3.3 V, the transistor D # 1 is the first device. However, in the case of FIG. 12, since there is one transistor connected to 3.3V, there is no next device in S1026 described later. Then, the process proceeds to S1021.

  In S1021, the power transmission processing unit 11b determines whether or not the voltage values of the terminals such as the source terminal and the drain terminal are fixed. If it is confirmed, the process proceeds to S1025. Otherwise, the process proceeds to S1022. In the example of FIG. 12, the voltage value of the drain terminal (node N1) of the transistor D # 1 is not fixed, so that is not the case.

  In step S1022, the power transmission processing unit 11b determines whether the device of interest is fixed OFF. If it is fixed to OFF, the process proceeds to S1025. Otherwise, the process proceeds to S1023. In the example of FIG. 12, the transistor D # 1 is not fixed OFF.

  In step S1023, the power transmission processing unit 11b transmits the potential of interest to the device. In the example of FIG. 12, 3.3 V of the power supply terminal Vpp is transmitted to the node N1 through the transistor D # 1. Then, the process proceeds to S1024.

  In step S1024, the power transmission processing unit 11b performs this check processing recursively on the device connected to the transmission destination net. In the example of FIG. 12, a check process is performed on the transistor D # 2 connected to the transmission destination net, and 3.3V is transmitted to the node N2. Then, when the node N2 becomes 3.3V, the check process is also performed on the transistors D # 3 and D # 4 connected to the net. In this case, each terminal (source terminal and drain terminal) is checked. Since the voltage value is determined, the process proceeds to S1025 by S1021.

  In step S1025, the power transmission processing unit 11b determines whether there is another device. If there is, the process proceeds to S1026, and if not, the process returns to S103. In the example of FIG. 12, since there is only one device connected to the target potential 3.3V of the transistor D # 1, there is no other device.

  In step S1026, the power transmission processing unit 11b sets the target device as the next device, and the process proceeds to step S1021.

  In the example of FIG. 12, after the check process as described above, the process returns to S103, and the process of setting the target potential to 1.5V and the process of setting the target potential to 0.0V are performed in S104. However, since the voltage value of each terminal in each of the transistors D # 1 to D # 4 has already been determined, all of S1021 becomes “Y”, and the voltage value is not transmitted thereafter.

  After that, by the processing of S105 to S109, the transistors D # 1 to D # 4 are sequentially set as devices of interest, and the voltage value of each terminal in each transistor is referred to. A report file is output. Thus, the transistors D # 3 and D # 4 in FIG. 12 are determined to be device power supply withstand voltage errors, and the error report file is output.

  As described above, for example, the following effects (1) to (5) can be obtained by using the circuit verification apparatus as described in the above description.

  (1) Focusing on the voltage values of the power supply terminal and the reference potential terminal, etc., and verifying with a simple process of simply transmitting the voltage value without giving an input pattern to the device, high-speed processing Can be easily applied to a large-scale circuit.

  (2) It is possible to easily identify a device in which a static through current error or a device breakdown voltage error has occurred.

  (3) Regardless of the input pattern to the device, it is possible to comprehensively verify the presence or absence of static through-current generation or the occurrence of device breakdown due to the worst-case voltage conditions. This makes it possible to prevent a verification failure depending on the input pattern.

  (4) Since the circuit netlist can be verified, an abnormality can be found at an early stage of design development.

  (5) The above (1) to (4) make it possible to detect a particularly simple design mistake at an early stage, so that the design development period can be shortened and the cost can be reduced.

  Next, an application example of the circuit verification device of FIG. 1 is shown in FIG. FIG. 13 is a block diagram showing an example of a configuration obtained by modifying the circuit verification device in FIG. 1 in the circuit verification device according to the embodiment of the present invention.

  The circuit verification apparatus shown in FIG. 13 includes, for example, a specified error list 13 in the input data unit 10, an error selection unit 14 in the data processing unit 11, and an output data unit 12 in addition to the configuration in FIG. An error report file 15 indicating the content of the selected error is provided. The specified error list 13 is a list of devices that are output as errors in another general circuit verification apparatus. In practice, depending on the setting of the verification device, etc., the designated error list 13 includes many devices that are not true errors.

  The error selection unit 14 compares the input specified error list 13 with the error report files 12a, 12b, and 12c obtained by the circuit verification apparatus of FIG. 1, and selects matching devices and mismatching devices. If they match, classification is performed according to the error contents of the circuit verification device of FIG. This classification result is output as an error report file 15 of selected errors.

  In general, the number of devices included in the specified error list 13 is very large, and a visual check operation by a designer or the like is usually performed on these devices. And this work requires a lot of time and labor. Therefore, the time and labor can be reduced by selecting and classifying the contents of the designated error list 13 by the error selection unit 14.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the description so far, the condition of the voltage value that is the worst for the device for each verification content is defined by either the high order voltage sort or the low order sort, but for each terminal of the device, It is also possible to define the condition of the worst voltage value in such a way that this high order sort or low order sort can be selected. In addition, in the case where verification is performed for a circuit in which almost no OFF-fixed device is included, a function for detecting an OFF-fixed device may not be provided.

  The circuit verification device of the present invention can be widely applied as a device for verifying design errors of semiconductor products such as memory products, logic products, and system LSIs having a transistor level netlist. The present invention is not limited to this, and can be applied to a board or a module board on which a semiconductor product such as a transistor is mounted as a device for verifying a design error of the board.

In the circuit verification apparatus of one embodiment of this invention, it is a block diagram which shows an example of the structure. FIG. 2 is an explanatory diagram illustrating an example of processing contents of a circuit development processing unit in FIG. 1 in the circuit verification device according to the embodiment of the present invention. In the circuit verification apparatus of one embodiment of this invention, it is a figure which defines the circuit symbol in the circuit diagram used for the description. FIG. 4 is a diagram illustrating an example of a circuit that causes a gate-to-source error in the circuit verification device according to the embodiment of the present invention, where (a) is an example of a circuit that causes an error when the input is not fixed, and (b) An example of a circuit that causes an error when “H” is fixed, and (c) shows an example of a circuit that causes an error when the input is fixed to “L”. It is a figure which shows an example of the circuit which becomes a source-to-board error in the circuit verification apparatus of one embodiment of this invention. FIG. 2 is a diagram illustrating an example of a circuit detected as a device power supply withstand voltage error in the circuit verification apparatus according to the embodiment of the present invention, where (a) is an example of a circuit that is detected when the input is not fixed, and (b) It is a figure which shows an example of the circuit detected when an input is fixed to "H". FIG. 2 is a process flow diagram showing an example of the operation of the apparatus shown in FIG. It is a figure which shows an example of the circuit which does not need to detect as a gate pair source error in the circuit verification apparatus of one embodiment of this invention. It is a figure which shows an example of the circuit which does not need to detect as a source-to-board error in the circuit verification apparatus of one embodiment of this invention. In the circuit verification apparatus of one embodiment of this invention, it shows an example of detailed operation | movement of the power transmission process part of FIG. 1, and a device determination part, and is a process flow figure which shows the process of a main routine. FIG. 11 is a process flow diagram illustrating an example of detailed operations of the power transmission processing unit and the device determination unit in FIG. 1 in the circuit verification device according to the embodiment of the present invention, and illustrating processing of a subroutine in FIG. 10. FIG. 12 is a diagram illustrating an example of a circuit for explaining the operations of FIGS. 10 and 11 in the circuit verification device according to the embodiment of the present invention. FIG. 2 is a block diagram illustrating an example of a configuration obtained by modifying the circuit verification device in FIG. 1 in the circuit verification device according to the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Input data part 10a Circuit data 10b Signal potential data 10c Device parameter 11 Data processing part 11a Circuit development processing part 11b Power supply transmission processing part 11c Device judgment part 12 Output data part 12a, 12b, 12c, 15 Error report file 13 Specification error list 14 Error selection unit 400, 401, 600, 601 CMOS circuit MP40, 41, 50, 51, 60, 61, 80 to 82, 90, 91 PMOS transistor D # 1 to # 3 PMOS transistor MN40, 41, 50, 51, 60, 61, 80, 81, 90, 91 NMOS transistor D # 4 NMOS transistor Vpp, Vdd Power supply terminal Vbb, Vss Reference potential terminal ND40, ND41, N1, N2 nodes

Claims (6)

A circuit data holding means, and voltage transfer setting means, a determination processing unit, the judgment result output and consists of a computer system having means, in circuit diagram or layout in the design phase constituted by connecting a plurality of transistors A circuit verification device for detecting connection errors in
The circuit data holding means includes a circuit connection information extracted circuit diagram or layout or found to be verified, the information of a plurality of fixed voltage values used in the circuit, the fixed voltage is applied in the circuit Holding fixed voltage terminal information and characteristic information required for each of the transistors,
The voltage transmission setting means refers to the circuit connection information, the fixed voltage value information, the fixed voltage terminal information, and the characteristic information from the circuit data holding means,
Comparing the voltage value between the terminals for each of said transistors when the predetermined fixed voltage is applied to each of (a) before Symbol fixed voltage terminal, the relationship voltage value between the terminals is fixed to off the transistor to identify a certain transistor,
(B) For each terminal other than the fixed voltage terminal in each circuit portion including the remaining transistors other than the transistor identified as being fixed off, assuming that the transistor is on a fixed voltage value is considered to be transmitted through the transistor, respectively set as a voltage value of the terminal,
The determination processing means includes:
(C) When the voltage value between the terminals is compared for each of the remaining transistors at the terminal voltage value set in (b), and the voltage value between the terminals is in a relationship that causes an error caused by the transistor. Determine that there is an error in the connection to the transistor ,
The determination result output means includes
A circuit verification device that outputs error information obtained by the determination processing means . The circuit verification device according to claim 1,
The plurality of transistors include a plurality of first conductivity type transistors supplied with a plurality of high potential side fixed voltages and a plurality of second conductivity type transistors supplied with a plurality of low potential side fixed voltages. ,
The voltage transmission setting means includes a first transmission setting function for transmitting the plurality of high-potential-side fixed voltages through the first conductivity type transistors, and the plurality of low transmission levels through the second conductivity type transistors. A second transmission setting function for transmitting a fixed voltage on the potential side,
The determination processing means includes a first determination processing function for determining each of the transistors in the first conductivity type transistor group after performing the processing by the first transmission setting function, and the second transmission setting function. A second determination processing function for determining each of the transistors in the group of transistors of the second conductivity type after performing the processing;
It said first transmission setting function, the each of the transistors in the group of the first conductivity type transistor, the (b) on-state assumed first conductivity type transistor via of the plurality the high potential when the Each of the plurality of high-voltage-side fixed voltages is transmitted to each of the plurality of high-voltage-side fixed voltages, and each of the first-conductivity-type transistors is complementary to the second-conductivity-type transistors. is set as the voltage value of the connected connection nodes,
Wherein the first determination processing function, the first after processing by the transfer setting function, the by (c), the forward direction of the diode voltage values for related or substrate terminals through current occurs in the transistor between the terminal Is determined to have an error in the connection to the transistor,
Said second transmission setting function, the each of the transistors in the group of the second conductivity type transistor, the (b) low through the second conductivity type transistor, assuming that on-state of the plurality in potential Each of the plurality of low-potential-side fixed voltages is transmitted to each of the plurality of low-potential-side fixed voltages. The second conductivity-type transistors are complementary to the first-conductivity-type transistors. is set as the voltage value of the connected connection nodes,
The second determination processing function, the second after processing by the transfer setting function, the by (c), the forward direction of the diode voltage values for related or substrate terminals through current occurs in the transistor between the terminal when in relation but being formed, the circuit verification apparatus according to claim <br/> determining that there is an error in the connection to the transistor. The circuit verification device according to claim 1,
The information held by the circuit data holding means includes the breakdown voltage value of each transistor,
Said determination processing unit Oite the (c), comparing the voltage value between the terminals for each of the remaining transistor is compared with the breakdown voltage of each transistor and a voltage value between the terminals, the withstand voltage violations A circuit verification device that determines an error when there is a relationship . The circuit verification device according to claim 2,
With reference to the information on the fixed voltage value held by the circuit data holding means , the voltage values are set in descending order in the first transmission setting function and in low order in the second transmission setting function. Each sorted,
Oite said (b), sequentially searches the presence or absence of setting of the voltage value for each of said connection node, said voltage value to a connection node that is determined to not set, a transistor connected to the connection node by setting the fixed voltage value to be transmitted via the transistor assuming that the on-state in order of voltage value for changing the arrangement, the circuit characterized by sequentially setting to Rukoto a voltage value for said connection node Verification device. In the circuit verification apparatus according to any one of claims 1 及至 4,
A specified error list is further included as information held by the circuit data holding means ,
Said determination processing unit, further wherein said transistor Therefore it is determined that the error (c), the circuit verification apparatus, wherein the designation error list indicating the transistor makes a determination of whether the same or not. Connection in circuit diagram or layout at design stage, comprising a computer system comprising circuit data holding means, first and second voltage transmission setting means, first and second determination processing means, and determination result output means A circuit verification device for detecting an error,
The circuit data holding means, a plurality of first transistors having a first conductivity type, the circuit diagram or configured appropriately connecting a plurality of second transistors having a second conductivity type corresponding to the circuit diagram Circuit connection information extracted from the layout; a plurality of high-potential-side power supply voltage information applied to the plurality of first transistors; a plurality of low-potential-side power supply voltage information applied to the plurality of second transistors; and first and characteristic information required for each of the second transistor maintains the,
The first voltage transmission setting unit uses the circuit connection information, the high-potential-side power supply voltage information, and the characteristic information from the circuit data holding unit, for each of the plurality of first transistors.
(A -1) of the plurality of intended for each of the first transistor to the most voltage value in the high-potential-side power supply voltage is given a higher first power supply voltage, short-circuit between two terminals except the control terminal when assumed through the first transistor to said first power supply voltage transmitted, respectively set as a voltage value of said first power supply voltage to the unconnected side terminal and,
(B -1) of the plurality of intended for each of the first transistor the next voltage value in the high-potential-side power supply voltage is given a higher second power supply voltage, before SL assuming short-circuiting between the two terminals and said second power supply voltage transmitted via the first transistor when the sets respectively as a voltage value of said second power supply voltage to the unconnected side terminal,
The first determination processing means includes:
For (c -1) wherein (a -1) and (b -1) respectively processed with the plurality of first bets transistor in which all of the voltage is set for the pins of the voltage value between the terminals, It is determined based on the characteristic information whether a voltage value that can cause a through current or a voltage value that can cause a device withstand voltage violation ,
The second voltage transmission setting unit uses the circuit connection information, the low-potential-side power supply voltage information, and the characteristic information from the circuit data holding unit, for each of the plurality of second transistors.
(A-2) For each of the second transistors to which the third power supply voltage having the lowest voltage value among the plurality of low-potential-side power supply voltages is applied, it is assumed that the two terminals other than the control terminal are short-circuited. When the third power supply voltage transmitted through the second transistor is set as a voltage value of a terminal not connected to the third power supply voltage,
(B-2) When assuming that the two terminals are short-circuited for each of the second transistors to which the fourth power supply voltage having the next lowest voltage value is applied among the plurality of low-potential-side power supply voltages, Setting the fourth power supply voltage transmitted through the second transistor as a voltage value of a terminal on the side not connected to the fourth power supply voltage,
The second determination processing means includes
(C-2) With respect to each of the plurality of second transistors in which all the voltages of the respective terminals have been set in accordance with the processes of (a-2) and (b-2), the voltage value between the terminals passes through. A circuit verification device that determines whether a voltage value at which a current can occur or a voltage value at which a device withstand voltage violation can occur is based on the characteristic information .

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