JP4345889B2 - Flotox型eepromの製造方法 - Google Patents
Flotox型eepromの製造方法 Download PDFInfo
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- JP4345889B2 JP4345889B2 JP2003378220A JP2003378220A JP4345889B2 JP 4345889 B2 JP4345889 B2 JP 4345889B2 JP 2003378220 A JP2003378220 A JP 2003378220A JP 2003378220 A JP2003378220 A JP 2003378220A JP 4345889 B2 JP4345889 B2 JP 4345889B2
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- oxide film
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- manufacturing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
Description
メモリセル部のトンネルインプラ領域上のトンネルウィンドウ領域と周辺アクティブ領域の酸化膜は同時にドライエッチングされるため、エッチング面積の増大に伴いエッチング終点検出の制御が容易になる。そして、酸化膜は、増速酸化を利用し、同時形成される周辺アクティブ領域の酸化膜より厚く形成されているため、周辺アクティブ領域のドライエッチングの終点検出時において、トンネルウィンドウ部には酸化膜が残存しており、基板エッチングダメージを低減することが可能となる。したがって、ドライエッチングを用いることにより、トンネルウィンドウ部の微細化を、エッチングダメージを回避しながら実現できる。
2、22 フィールド酸化膜
3、23 チャンネルストップ領域
4、24 トンネルインプラ領域
5、10、25 ゲート酸化膜
6、28 レジスト
7、29 トンネルウィンドウ開口部
8、30 トンネルウィンドウ領域
9、31 トンネル酸化膜
26,27、32 酸化膜
Claims (4)
- シリコン基板上のアクティブ領域のメモリセルの一部分に拡散領域を形成し、酸化処理により前記拡散領域上の酸化膜厚が前記拡散領域以外のアクティブ領域上の酸化膜厚より厚くなるように形成し、レジストを塗布し前記拡散領域上の一部分及び前記メモリセル以外の周辺トランジスタ形成領域のアクティブ領域を開口し、ドライエッチング法により前記周辺トランジスタ領域の酸化膜が除去されるまでエッチングし、前記メモリセルの開口部に残存する酸化膜をウエットエッチング法により除去し、前記レジストを除去することを特徴とする局所的に薄い酸化膜を有するEEPROMの製造方法。
- 前記局所的に薄い酸化膜を有するEEPROMはFLOTOX型であることを特徴とする請求項1記載のEEPROMの製造方法。
- 前記拡散領域上の酸化及び前記拡散領域以外のアクティブ領域上の酸化は同時に行なわれることを特徴とする請求項1記載のEEPROMの製造方法。
- 前記拡散領域上の酸化は増速酸化であることを特徴とする請求項3記載のEEPROMの製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003378220A JP4345889B2 (ja) | 2003-11-07 | 2003-11-07 | Flotox型eepromの製造方法 |
US10/797,127 US7030025B2 (en) | 2003-11-07 | 2004-03-11 | Method of manufacturing flotox type eeprom |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003378220A JP4345889B2 (ja) | 2003-11-07 | 2003-11-07 | Flotox型eepromの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005142408A JP2005142408A (ja) | 2005-06-02 |
JP4345889B2 true JP4345889B2 (ja) | 2009-10-14 |
Family
ID=34544454
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003378220A Expired - Fee Related JP4345889B2 (ja) | 2003-11-07 | 2003-11-07 | Flotox型eepromの製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7030025B2 (ja) |
JP (1) | JP4345889B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005236062A (ja) * | 2004-02-20 | 2005-09-02 | Nec Electronics Corp | 不揮発性半導体記憶装置の製造方法 |
JP2006228873A (ja) * | 2005-02-16 | 2006-08-31 | Oki Electric Ind Co Ltd | 不揮発性半導体メモリの製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4477825A (en) | 1981-12-28 | 1984-10-16 | National Semiconductor Corporation | Electrically programmable and erasable memory cell |
US4701776A (en) | 1983-08-29 | 1987-10-20 | Seeq Technology, Inc. | MOS floating gate memory cell and process for fabricating same |
JPS61228672A (ja) | 1985-04-02 | 1986-10-11 | Nec Corp | 絶縁ゲ−ト型不揮発性半導体メモリ及びその製造方法 |
JPH04145666A (ja) | 1990-10-08 | 1992-05-19 | Nec Corp | 電気的に消去書込み可能な不揮発性半導体記憶装置 |
JP2672189B2 (ja) | 1990-11-30 | 1997-11-05 | シャープ株式会社 | 不揮発性ランダムアクセスメモリ及びメモリセルアレイ |
EP0655778A3 (en) * | 1993-11-25 | 1996-01-03 | Matsushita Electronics Corp | Method of manufacturing semiconductor memory devices. |
US6165846A (en) * | 1999-03-02 | 2000-12-26 | Zilog, Inc. | Method of eliminating gate leakage in nitrogen annealed oxides |
US6372525B1 (en) * | 1999-12-20 | 2002-04-16 | Taiwan Semiconductor Manufacturing Company | Wafer-level antenna effect detection pattern for VLSI |
JP2001210730A (ja) | 2000-01-25 | 2001-08-03 | Oki Electric Ind Co Ltd | 不揮発性半導体記憶装置の製造方法 |
-
2003
- 2003-11-07 JP JP2003378220A patent/JP4345889B2/ja not_active Expired - Fee Related
-
2004
- 2004-03-11 US US10/797,127 patent/US7030025B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005142408A (ja) | 2005-06-02 |
US7030025B2 (en) | 2006-04-18 |
US20050101152A1 (en) | 2005-05-12 |
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