JP4311089B2 - Electro-optical device, driving method of electro-optical device, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical device, a driving method of the electro-optical device, and an electronic apparatus, and more particularly to time-division driving.
[0002]
[Prior art]
For example, Patent Literature 1 and Patent Literature 2 disclose an active matrix electro-optical device using time-division driving in order to reduce the number of output pins of a driver IC and to secure a pitch between output pins. Yes. Time-division driving is a technology that time-sequentially outputs time-series data for a plurality of pixels output from a higher-level circuit such as a driver IC and distributes the individual data to corresponding data lines.
[0003]
[Patent Document 1]
JP-A-11-327518
[Patent Document 2]
JP 2001-134245 A.
[0004]
[Problems to be solved by the invention]
An object of the present invention is to stabilize circuit operation in an electro-optical device using time-division driving.
[0005]
Another object of the present invention is to eliminate the time restriction on data writing in an electro-optical device using time-division driving, and to easily cope with high definition.
[0006]
[Means for Solving the Problems]
In order to solve such a problem, the first invention provides an output line for outputting data for a plurality of pixels in time series, a plurality of signal lines provided corresponding to the output lines, and an output line. A plurality of corresponding data lines, each of which is divided into a plurality of data lines each having a pixel connected thereto, and time-series data output to the output line are time-divided and time-divided A time-division circuit that distributes data to a plurality of signal lines, a setting circuit that is provided between the signal lines and the data lines, inputs the signal line data, and sets the potential level of the data lines, and is connected to the signal lines An electro-optical device is provided that includes a potential supply unit that supplies a predetermined potential to the signal line in order to regulate the floating state of the signal line.
[0007]
Here, in the first invention, the potential supply unit may supply a predetermined potential to the signal line via a pull-up resistor or a pull-down resistor, or via a switching element that conducts according to a control signal. A predetermined potential may be supplied to the signal line.
[0008]
In the first invention, the setting circuit may be an inverter or a level shifter level shifter that converts the potential amplitude of the signal line into a potential amplitude necessary for driving the pixel. In addition, the setting circuit may be an analog multiplexer configured with an analog switch, or may be a latch circuit that latches signal line data.
[0009]
In the first invention, at least one latch circuit that is provided on a part of the plurality of data lines and latches the data output from the setting circuit at a timing according to the control signal may be further provided. In this case, it is preferable that at least one latch circuit is provided at least on the data line in which the order in which time-divided data is distributed is first.
[0010]
The second invention is an output line for outputting data for a plurality of pixels in time series, and a plurality of data lines provided corresponding to the output lines, each of which is connected to a pixel. A time division circuit that time-divides a plurality of data lines and time-series data output to the output line, and distributes the time-divided data to the plurality of data lines, and is provided in a part of the plurality of data lines. And at least one latch circuit for latching data output from the time division circuit at a timing according to the control signal.
[0011]
Here, in the second invention, it is preferable that at least one latch circuit is provided at least in the data line in which the order in which the time division circuit outputs the time-division data to the plurality of signal lines is the earliest. .
[0012]
A third invention provides an electronic apparatus in which the electro-optical device according to the first or second invention described above is mounted.
[0013]
According to a fourth aspect of the present invention, there is provided a first step of outputting data for a plurality of pixels to an output line in a time series, time division of time series data output to the output line, and time division of the data obtained by time division With the second step of allocating to a plurality of signal lines provided corresponding to the output line, and a setting circuit provided between the signal line and the data line connected to the pixel, the signal line data is input. An electro-optical device driving method comprising: a third step of setting the potential level of the data line; and a fourth step of supplying a predetermined potential to the signal line in order to regulate the floating state of the signal line. To do.
[0014]
According to a fifth aspect of the present invention, there is provided a first step of outputting data for a plurality of pixels to an output line in time series, time-sequentially outputting time series data output to the output line, and An electro-optic having a second step of allocating to a plurality of data lines provided corresponding to the output line, and a third step of latching a part of the data output to the plurality of data lines at a predetermined timing A method for driving an apparatus is provided.
[0015]
Here, in the fifth invention, it is preferable that the third step is a step of latching at least the data output to the data line in which the order in which the time-divided data is distributed is first.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 is a block diagram of the electro-optical device according to the present embodiment. The display unit 1 is an active matrix display panel in which a liquid crystal element is driven by a switching element such as a TFT (thin film transistor). In the display unit 1, pixels 2 for m dots × n lines are arranged in a matrix (in a two-dimensional plane). Further, the display unit 1 includes n scanning lines Y1 to Yn each extending in the row direction (X direction) and m data each extending in the column direction (Y direction). Lines X1 to Xm are provided, and the pixels 2 are arranged corresponding to these intersections.
[0017]
FIG. 2 is an equivalent circuit diagram of the pixel 2 using liquid crystal. One pixel 2 includes a TFT 21 that is a switching element, a liquid crystal capacitor 22, and a storage capacitor 23. The source of the TFT 21 is connected to one data line X, and its gate is connected to one scanning line Y. Regarding the pixels 2 arranged in the same column, the sources of the respective TFTs 21 are connected to the same data line X. For the pixels 2 arranged in the same row, the gates of the respective TFTs 21 are connected to the same scanning line Y. The drain of the TFT 21 is commonly connected to a liquid crystal capacitor 22 and a storage capacitor 23 provided in parallel. The liquid crystal capacitor 22 includes a pixel electrode 22a, a counter electrode 22b, and a liquid crystal (liquid crystal layer) sandwiched between the electrodes 22a and 22b. The storage capacitor 23 is formed between the pixel electrode 22a and a common capacitor electrode (not shown), and is supplied with the potential Vcs. The storage capacitor 23 suppresses leakage of charges accumulated in the liquid crystal. A potential corresponding to data is applied to the pixel electrode 22 a side via the TFT 21. When data is supplied from the data line X to the pixel 2 in the data writing period, the liquid crystal capacitor 22 and the storage capacitor 23 are charged and discharged. Thereby, the transmittance of the liquid crystal layer is set according to the potential difference between the pixel electrode 22a and the counter electrode 22b, and the gradation of the pixel 2 is set.
[0018]
The control circuit 5 synchronously controls the scanning line driving circuit 3 and the data line driving circuit 4 based on external signals such as a vertical synchronizing signal Vs, a horizontal synchronizing signal Hs, and a dot clock signal DCLK input from a host device (not shown). . Under this synchronization control, the scanning line driving circuit 3 and the data line driving circuit 4 perform display control of the display unit 1 in cooperation with each other.
[0019]
The scanning line driving circuit 3 is mainly composed of a shift register, an output circuit, etc., and performs scanning of the scanning lines Y1 to Yn by outputting a scanning signal SEL to the scanning lines Y1 to Yn. The scanning signal SEL takes a binary signal level of a high potential level (hereinafter referred to as “H level”) or a low potential level (hereinafter referred to as “L level”), and corresponds to a pixel row to which data is to be written. The scanning line Y is set to the H level, and all other scanning lines Y are set to the L level. Thereby, in a predetermined period (1F), line-sequential scanning is performed in which pixel rows to which data is to be written are sequentially selected from the top to the bottom.
[0020]
The data line driving circuit 4 cooperates with the scanning line driving circuit 3 to output data to be supplied to the pixel row to which data is to be written to the data lines X1 to Xm. As shown in FIG. 1, the data line driving circuit 4 is composed of a driver IC 41 and i circuit units 42 corresponding to the number of output pins PIN1 to PINi of the driver IC 41. The driver IC 41 is provided outside the display panel in which the pixels 2 are formed in a matrix, and output lines DO1 to DOi are connected to i output pins PIN1 to PINi provided therein. The i circuit units 42 provided in units of output lines are preferably formed integrally with the display panel, for example, with low-temperature polysilicon in order to reduce manufacturing costs.
[0021]
The driver IC 41 incorporates main circuits such as a shift register, a latch circuit, and a selector switch group for generating time-series data for a plurality of pixels. The driver IC 41 simultaneously outputs data for a pixel row to which data is written this time and performs dot sequential latching of data relating to a pixel row to which data is to be written next time. First, in one horizontal scanning period (1H), m pieces of data corresponding to the number m of data lines X are sequentially latched. In the next 1H, the latched m pieces of data are output simultaneously. These output data are grouped by a predetermined number (six in this embodiment) in the changeover switch group, and are output from corresponding output pins PIN1 to PINi as time-series data for six pixels. .
[0022]
In the present embodiment, the pixel 2 is driven using subfield driving, which is a type of time axis modulation method. FIG. 3 is a schematic explanatory diagram of subfield driving. As an example, the data defining the gradation of the pixel 2 is 16 gradation data composed of 4 bits. One frame, which is the minimum display unit of an image, is divided into four subfields SF1 to SF4. In relation to the gradation to be displayed, the subfields SF1 to SF4 are set to a length that gives a weight of 1: 2: 4: 8. However, this weighting may be adjusted according to the characteristics of the liquid crystal, for example, 0.9: 2.1: 3.9: 8: 1.
[0023]
The display gradation of the pixel 2 is determined according to the combination of the subfields SF that sets the pixel 2 to the ON state, and this combination is uniquely specified by the gradation value of the data. Hereinafter, the sub-field SF that supplies the on-voltage Von for driving the pixel 2 when performing a certain gradation display is referred to as “on / sub-field SFon”. Further, a subfield SF that supplies an off voltage Voff different from the on voltage Von is referred to as “off subfield SFoff”. For example, when the gradation value is 9, the on subfield SFon is SF1 with weight 1 and SF4 with weight 8, and the off subfield SFoff is SF2 with weight 2 and SF3 with weight 4. In this case, the total weight of the two subfields SF1 and SF4 is 9, and gradation display corresponding to this weighting is performed. The effective voltage acting on the pixel 2 depends on the length of the on-subfield SFon occupying one frame, and the effective voltage increases as this length increases. As a result, for example, in the case of a liquid crystal operating in a normally black mode, the luminance becomes higher (white display) as the on / subfield SFon becomes longer. The driver IC 41 determines either the on voltage Von or the off voltage Voff in each of the subfields SF1 to SF4 according to the gradation to be displayed, and outputs binary digital data from the output lines DO1 to DOi. Output to the outside.
[0024]
Note that the number of subfields SF, the setting of weights, or the combination method according to the gradation value shown in FIG. 3 is merely an example, and the weights of all subfields SF are set to be the same. (Equally spaced subfield drive).
[0025]
In this embodiment, the time-division driving method is used in order to reduce the number of output pins of the driver IC 41 and ensure the pitch between adjacent pins. As shown in FIG. 1, the upper output lines DO1 to DOi and the lower data lines X1 to Xm are in a one-to-many connection relationship. That is, the data lines X1 to Xm are grouped every six lines, and each group is associated with one output line DO. The circuit unit 42 time-divides the time-series data output from the driver IC 41 in the previous stage, and distributes the individual data obtained thereby to each of the six data lines X in the same group. Go. The i circuit units 42 provided in units of output lines have the same configuration, and all operate in parallel. Therefore, in the following description, attention is paid only to the circuit system of the output line DO1. I will explain.
[0026]
FIG. 4 is a principal circuit diagram of the data line driving circuit 4 according to the present embodiment, and shows the configuration of a single circuit unit 42 located at the subsequent stage of the driver IC 41 (see FIG. 1). The circuit unit 42 includes a time division circuit 43, a potential supply unit 44, and an inverter 45.
[0027]
The time division circuit 43 time-divides the time-series data for six pixels supplied to the output line DO1 and distributes the data to each of the six signal lines SL1 to SL6. The time division circuit 43 has six selection switches corresponding to the signal lines SL1 to SL6 constituting one group, and each selection switch has selection signals SS1 to SS6 from the control circuit 5. The conduction is controlled by any of the above. These selection signals SS1 to SS6 define the ON period of the selection switch in the same group and are synchronized with the time-series signal output from the driver IC 41.
[0028]
The inverter 45 is provided for each signal line between the signal line SL and the data line X, and functions as a setting circuit that sets the potential level of the data line X in accordance with the data supplied to the signal line SL. . The reason for providing such an inverter 45 is to secure the current supply capability to the data line X, thereby speeding up charging / discharging of the data line X and shortening the time required for data writing. As a result, even in the time-division driving method, data can be written in a short time, and it is easy to cope with high definition.
[0029]
FIG. 5 is a timing chart of time division driving. First, the data write target in the selection period (1H) when the scanning signal SEL of the uppermost scanning line Y1 is H level is the pixels P (1,1) to P (6,1), that is, the uppermost scanning line Y1. And six pixels corresponding to each intersection of the data lines X1 to X6. From the driver IC 41, data for 6 dots relating to P (1,1) to P (6,1) is output to the output line DO1 in time series. In synchronization with this output, the selection signals SS1 to SS6 are sequentially sequentially set to the H level, and the six selection switches constituting the time division circuit 43 are alternately turned on with an on time offset from each other ( (The turn-on order is SS1, SS2,..., SS6) As a result, the time-series data is time-divided into six, and becomes one-dot data sequentially to the corresponding signal lines SL1 to SL6. It will be distributed. The distributed data is supplied to the corresponding data line X through level inversion in an inverter 45 provided for each signal line. The data line X is quickly charged / discharged by the current supply capability of the inverter 45, and the potential is set to a potential level corresponding to the data.
[0030]
Data write targets in the selection period (1H) when the scanning signal SEL of the second scanning line Y2 is at the H level are pixels P (1,2) to P (6,2), that is, the second scanning line Y2. And six pixels corresponding to each intersection of the data lines X1 to X6. The driver IC 41 outputs data for 6 dots relating to P (1,2) to P (6,2) in time series to the output line DO1. The output time-series data is time-divided into six and then distributed to the signal lines SL1 to SL6. The distributed data is supplied to the corresponding data line X after level inversion in the inverter 45. As a result, the data line X is charged / discharged to a potential level corresponding to the time-divided data. The same applies to the subsequent steps, and data writing for 6 dots in each pixel row is performed line-sequentially until the lowermost scanning line Yn is selected. Such line-sequential data writing is performed four times during one frame when one frame is divided into four subfields SF1 to SF4.
[0031]
Here, as the signal line SL and the data line X are electrically separated by the inverter 45, a potential supply unit 44 is connected to each signal line SL. In the present embodiment, the potential supply unit 44 includes a pull-up resistor R and a capacitor C. A pull-up resistor R provided between a predetermined power supply potential Vdd and the signal line SL is provided to regulate the floating state of the signal line SL, and the signal line SL is connected via the pull-up resistor R. Is supplied with the power supply potential Vdd. Further, the capacitor C provided between the predetermined reference potential Vss and the signal line SL is for stabilizing the potential of the signal line SL, and may be a positively formed capacitor element. The wiring capacitance of the signal line SL itself may be used. The reason for providing such a pull-up resistor R is to prevent the through current from flowing through the inverter 45 by suppressing the fluctuation of the input level of the inverter 45. When the pull-up resistor R is not provided, when the selection switch in the time division circuit 43 is off, the signal line SL corresponding to the selection switch is in a floating state in which no potential is supplied. When noise is applied to the signal line SL in the floating state, an excessive through current may flow through the inverter 45, resulting in malfunction and increase in power consumption. In order to prevent such a phenomenon, a pull-up resistor R is provided to suppress the fluctuation of the potential of the signal line SL and to prevent the occurrence of a through current in the inverter 45.
[0032]
According to the present embodiment, in order to regulate the floating state of the signal line SL, the power supply potential Vdd is supplied to the signal line SL via the pull-up resistor R configuring the potential supply unit 44. Thereby, the operation of the inverter 45 can be stabilized without being affected by noise.
[0033]
In this embodiment, the potential supply unit 44 is mainly composed of the pull-up resistor R. However, the pull-up resistor R may be replaced with a pull-down resistor whose one end is connected to the ground potential Vss. An effect can be obtained.
[0034]
Further, according to the present embodiment, the data line X can be charged and discharged quickly by interposing the inverter 45 having a large current supply capability between the signal line SL and the data line X. Therefore, even in the case of time-division driving that involves time restrictions in the switching operation of the time-division circuit 43 (this restriction becomes prominent when used in combination with subfield driving), data can be sufficiently written. Therefore, it becomes easy to cope with high definition. Note that the number of inverters 45 provided between the signal line SL and the data line X may be plural, and in particular, in order to prevent the inversion of the logic level of the signal, it may be set to an even number. Good.
[0035]
(Second Embodiment)
FIG. 6 is a principal circuit diagram of the data line driving circuit 4 according to the second embodiment, and shows a configuration of a single circuit unit 42 located at the subsequent stage of the driver IC 41 (FIGS. 8 to 11 described later). The same applies to. In the present embodiment, the potential supply unit 44 is configured by a reset circuit instead of the pull-up resistor R described above. Specifically, a switching transistor SW is provided for each signal line between a predetermined reset potential Vrst and the signal line SL, and conduction of these six switching transistors SW is controlled by a control signal RST. Since the other points are the same as those in the first embodiment, the same reference numerals as those shown in FIG.
[0036]
FIG. 7 is a timing chart of time division driving according to the present embodiment. The control signal RST is set to the H level in a period from when the last selection signal SS6 falls to the L level until the first selection signal SS1 rises to the H level in the next selection period. Therefore, in the off period in which all the selection switches in the time division circuit 43 are turned off, the switching transistors SW are turned on all at once by the control signal RST, and the reset potential Vrst is supplied to all the signal lines SL1 to SL6. As a result, the signal lines SL1 to SL6 can be prevented from being in a floating state during the off period of the time division circuit 43, so that the operation of the inverter 45 in the subsequent stage can be stabilized as in the first embodiment. .
[0037]
In the present embodiment, the example in which the reset potential Vrst is supplied during the driving operation of the pixel 2 has been described. However, in the initial state immediately after the electro-optical device is turned on and before the driving operation is started, such a reset potential Vrst is supplied. Vrst may be supplied.
[0038]
In each embodiment described below, a pull-up resistor (pull-down resistor) according to the first embodiment or a reset circuit according to the second embodiment is used as the potential supply unit 44 that regulates the floating state of the signal line SL. Either of these may be applied.
[0039]
(Third embodiment)
FIG. 8 is a main part circuit diagram of the data line driving circuit 4 according to the third embodiment. In the present embodiment, as a setting circuit for setting the potential level of the data line X, a level shifter 46 that converts the data potential from a logic level to a drive level necessary for driving the pixel 2 is used instead of the inverter 45. A potential supply unit 44 is provided on the signal line SL before the level shifter 46.
[0040]
The level shifter 46 separates the power supply systems so that the circuit systems before and after that can be driven by different power supply systems, and the potential amplitude | Vdd−Vss | at the logic level is changed to the potential amplitude | Vdd2−Vss | at the drive level of the pixel 2. And convert. The circuit system before the level shifter 46 is driven at the logic level, that is, the first power supply potential Vdd (for example, 1.8 V). Further, the circuit system subsequent to the level shifter 46 has a second power supply potential Vdd2 (for example, 3.0 V) that is higher than the first power supply potential Vdd in the present embodiment. Drive with. An inverter 47 provided immediately before the level shifter 46 inverts the potential level of the data output from the output pin PIN1. The signal from the output pin PIN1 is supplied as it is to the I terminal (input terminal) of the level shifter 46, and the signal whose level is inverted by the inverter 47 is supplied to the / I terminal (inverted input terminal).
[0041]
The level shifter 46 includes, for example, six transistors, and two transistor rows are provided in parallel between the second power supply potential Vdd2 and the reference potential Vss. One transistor array is composed of two p-channel transistors Tp1, Tp2 and an n-channel transistor Tn1, and the other transistor array is composed of two p-channel transistors Tp3, Tp4 and an n-channel transistor Tn2. Yes. The second power supply potential Vdd2 is applied to the sources of the transistors Tp1 and Tp3, and the reference potential Vss is applied to the sources of the transistors Tn1 and Tn2. The source of the transistor Tp2 is connected to the drain of the transistor Tp1, and the drain of the transistor Tp2 is connected to the drain of the transistor Tn1. The source of the transistor Tp4 is connected to the drain of the transistor Tp3, and the drain of the transistor Tp4 is connected to the drain of the transistor Tn2. The gates of the two transistors Tp2 and Tn1 are commonly connected to the I terminal, and the connection node a connecting them is connected to the gate of the transistor Tp3. Similarly, the gates of the two transistors Tp4 and Tn2 are commonly connected to the / I terminal, and the connection node b connecting them is commonly connected to the gate of the transistor Tp1 and the O terminal (output terminal). Yes. The gate of the transistor Tp3 is connected to the connection node a.
[0042]
As shown in the table below, the level shifter 46 converts a logic level signal input from the I terminal into a drive level signal for the pixel 2, and outputs this to the subsequent data line X via the O terminal. .
[Table 1]
(Operation table of level shifter 46)
I terminal (SL1) H level (Vdd) L level (Vss)
Tp1 OFF state ON state
Tp2 OFF state ON state
Tp3 ON state OFF state
Tp4 ON state OFF state
Tn1 ON state OFF state
Tn2 OFF state ON state
O terminal (X1) H level (Vdd2) L level (Vss)
According to the present embodiment, the potential supply unit 44 is provided in the signal line SL before the level shifter 46, thereby restricting the floating state of the signal line SL. As a result, the operation of the level shifter 46 using the potential of the signal line SL as an input can be stabilized.
[0043]
(Fourth embodiment)
FIG. 9 is a main part circuit diagram of the data line driving circuit 4 according to the fourth embodiment. In the present embodiment, an analog multiplexer 48 constituted by an analog switch is used as a setting circuit for setting the potential level of the data line X. A potential supply unit 44 is provided on the signal line SL before the analog multiplexer 48.
[0044]
The analog multiplexer 48 has a configuration in which two analog switches TM1 and TM2 are connected in series between two fixed potentials Va and Vb. The levels of these potentials Va and Vb are set to drive levels necessary for driving the pixel 2. The signal of the output line DO1 is supplied to the gate of the p-channel transistor of the analog switch TM1 and the gate of the n-channel transistor of the analog switch TM2. An inverted signal of the output line DO1 is supplied to the gate of the n-channel transistor of the analog switch TM1 and the gate of the p-channel transistor of the analog switch TM2 via the inverter 48a. The potential level (Va or Vb) at the connection node of the two analog switches TM1 and TM2 is output to the data line X as an output signal of the analog multiplexer 48.
[0045]
As shown in the table below, the analog multiplexer 48 converts the logic level signal input from the input terminal (DO1) into a signal of the driving level of the pixel 2, which is output from the output terminals (connection nodes of TM1 and TM2). , Output to the data line X.
[Table 2]
(Operation table of analog multiplexer 48)
Input terminal (SL1) H level (Vdd) L level (Vss)
TM1 p-channel transistor OFF state ON state
TM1 n-channel transistor OFF state ON state
TM2 p-channel transistor ON state OFF state
TM2 n-channel transistor ON state OFF state
Output terminal (X1) H level (Va) L level (Vb)
According to the present embodiment, the potential supply unit 44 is provided in the signal line SL in the previous stage of the analog multiplexer 48 to restrict the floating state of the signal line SL. As a result, the operation of the level shifter 46 using the potential of the signal line SL as an input can be stabilized.
[0046]
When the analog multiplexer 48 is used as the setting circuit, it can be applied not only to subfield driving (digital driving) but also to voltage gradation method (analog driving).
[0047]
(Fifth embodiment)
FIG. 10 is a main part circuit diagram of the data line driving circuit 4 according to the fifth embodiment. In the present embodiment, a latch circuit 49 is used as a setting circuit for setting the potential level of the data line X. The latch circuit 49 includes two inverters having one output as the other input, latches the data on the signal line SL, and outputs the potential level to the data line X. A potential supply unit 44 is provided on the signal line SL in the previous stage of the latch circuit 49.
[0048]
Similar to the above-described embodiments, in this embodiment, the operation of the latch circuit 49 using the potential of the signal line SL as an input can be stabilized by regulating the floating state of the signal line SL.
[0049]
In the first to fifth embodiments described above, the inverter 45, the level shifter 46, the analog multiplexer 48, and the latch circuit 49 are described as examples of the setting circuit. However, the present invention is not limited to this. For example, the present invention can be widely applied to a setting circuit for setting the potential level of the data line X using data of the signal line SL as an input, including an amplifier. .
[0050]
(Sixth embodiment)
FIG. 11 is a principal circuit diagram of the data line driving circuit 4 according to the sixth embodiment, and shows a configuration of a single circuit unit 42 located at the subsequent stage of the driver IC 41. In the present embodiment, the second latch circuit 50a in which the data latch timing is controlled by the latch signal LAT and the inverted latch signal / LAT in the subsequent stage of the above-described latch circuit 49 (hereinafter referred to as the first latch circuit 49). , 50b is added to the two-stage latch configuration.
[0051]
The second latch circuits 50a and 50b are not provided corresponding to all the data lines X1 to X6, but a part thereof, specifically, the data time-divided by the time-division circuit 43 is distributed. It is provided only for the data line X1 that is the first to be assigned and the data line X2 that is assigned next. Regarding the circuit system of the data lines X1 and X2, the output of the first latch circuit 49 is sent to the second latch circuits 50a and 50b via the analog switch 51 controlled to be conductive by the latch signal LAT and the inverted latch signal / LAT. Entered. These latch circuits 50a and 50b rewrite data to be latched when the latch signal LAT is H level (inverted latch signal / LAT is L level), and the latch signal LAT is L level (inverted latch signal / LAT is H level). Level), the data is retained. The output of the latch circuit 50a is supplied to the data line X1, and the output of the latch circuit 50b is supplied to the data line X2.
[0052]
The second latch circuits 50a and 50b latch the data output from the first latch circuit 49 at a timing according to the latch signal LAT. FIG. 12 is a timing chart of time division driving according to the present embodiment. Since the selection signals SS1, SS2,..., SS6 are sequentially set to the H level in this order, the time-series data for 6 pixels in the output line DO1 is the signal lines SL1, SL2,. Sorted in the order of SL6. Here, the data distributed to the signal lines SL3 to SL6 are supplied as they are to the data lines X3 to X6 where the second latch circuits 50a and 50b are not provided via the first latch circuit 49. On the other hand, the data lines X1 and X2 provided with the second latch circuits 50a and 50b are previously held in the second latch circuit 50 when data is allocated to the signal lines SL1 and SL2. Data is still being supplied. Then, when the latch signal LAT rises to the H level, the second latch circuits 50a and 50b take in the current data, thereby supplying the current data to the data lines X1 and X2.
[0053]
According to the present embodiment, a sufficient writing period can be ensured even in time-division driving that involves time restrictions in data writing. This point will be described in comparison with the timing chart shown in FIG. 5 (when the second latch circuits 50a and 50b are not provided). In the case of FIG. 5, the data writing period for the pixel rows P (1,1) to P (6,1) corresponding to the uppermost scanning line Y1 is a period during which the scanning line Y1 is at the H level. . However, since the ON time of the selection switch in the time division circuit 43 is offset, the data writing period differs for each of the data lines X1 to X6, and the writing period becomes shorter as the order of allocation becomes slower. For the data line X6 with the strictest time restriction, the data line X6 is charged and discharged within the period of Δt shown in FIG. 5 to write data to the pixel P (6,1). Need to be completed. If data cannot be sufficiently written to the pixel P (6, 1) within this period Δt, it is necessary to delay the selection end timing te of the scanning line Y1. However, if this timing te is delayed, it is necessary to delay the transfer start timing of the time-series data for the next pixel rows P (1, 2) to P (6, 2), which hinders the speeding up of the driving operation. Such a problem of insufficient data writing becomes obvious because the period Δt tends to be shortened as the display becomes higher in definition.
[0054]
On the other hand, in the case of FIG. 12, first, at the timing t1 when the selection signal SS1 rises to the H level, the data of the pixel P (1,2) is distributed to the signal line SL1. However, since the latch signal LAT remains at the L level at this timing t1, the second latch circuit 50a corresponding to the data line X1 transfers the data of the pixel P (1,1) currently held to the data line X1. Continue to output. At the same time, since the uppermost scanning line Y1 is still selected, data writing to the pixel rows P (1,1) to P (6,1) is continued. Next, at the timing t2 when the selection signal SS2 rises to the H level, the data of the pixel P (2,2) is distributed to the signal line SL2. However, at this timing t2, since the latch signal LAT remains at the L level, the second latch circuit 50b corresponding to the data line X2 transfers the data of the pixel P (2,1) currently held to the data line X2. Continue to output. At the same time, at this timing t2, since the uppermost scanning line Y1 is still selected, the data writing to the pixel rows P (1,1) to P (6,1) is continued. At timing t3, the latch signal LAT rises from L level to H level. Then, selection of the uppermost scanning line Y1 is completed, and selection of the next scanning line Y2 is started. At timing t3, the data on the signal lines SL1 and SL2 are latched by the second latch circuits 50a and 50b and output to the data lines X1 and X2.
[0055]
As can be seen from the above description, in the present embodiment, by providing the latch circuits 50a and 50b, the selection end timing te 'of the scanning line Y1 is set to the next pixel rows P (1,2) to P (6,2). Can be set after the transfer start timing t1. Therefore, the above-described period Δt can be set long, and the time restriction relating to data writing can be effectively eliminated. As a result, it is easy to cope with high definition even with time-division driving with time constraints.
[0056]
In the present embodiment, two second latch circuits are used. However, the number of the second latch circuits is not limited to this, and at least one second latch circuit is provided on the data line X1 having the first data distribution order. It is enough if it is done. In addition, if the number of second latch circuits is increased in accordance with this order, the period Δt can be set longer.
[0057]
In the present embodiment, the configuration in which the latch circuit 49 is provided in the previous stage of the second latch circuit has been described. However, the present invention is not limited to this, and the preceding circuit may be the above-described inverter 45, level shifter 46, or the like, or the preceding circuit may be omitted.
[0058]
In each of the above-described embodiments, the case where a liquid crystal element is used has been described as an example. However, the present invention is not limited to this, and an organic EL element, a digital micromirror device (DMD), or plasma emission is used. The present invention can also be applied to various electro-optical elements using fluorescence or the like by electron emission.
[0059]
Furthermore, the electro-optical device according to each of the above-described embodiments can be mounted on various electronic devices including, for example, a television, a projector, a mobile phone, a mobile terminal, a mobile computer, a personal computer, and the like. When the above-described electro-optical device is mounted on these electronic devices, the commercial value of the electronic devices can be further increased, and the product appeal of electronic devices in the market can be improved.
[0060]
【The invention's effect】
According to the present invention, in time-division driving, a predetermined potential is supplied to a signal line to regulate the floating state of the signal line, thereby stabilizing the operation of the setting circuit that receives signal line data. it can. In addition, by latching a part of the time-divided data at a predetermined timing, it is possible to eliminate time restrictions related to data writing and to easily cope with high definition.
[Brief description of the drawings]
FIG. 1 is a block diagram of an electro-optical device.
FIG. 2 is an equivalent circuit diagram of a pixel using liquid crystal.
FIG. 3 is a schematic explanatory diagram of subfield driving.
FIG. 4 is a main part circuit diagram of the data line driving circuit according to the first embodiment;
FIG. 5 is a timing chart of time division driving according to the first embodiment.
FIG. 6 is a main part circuit diagram of a data line driving circuit according to a second embodiment;
FIG. 7 is a timing chart of time-division driving according to the second embodiment.
FIG. 8 is a main part circuit diagram of a data line driving circuit according to a third embodiment;
FIG. 9 is a timing chart of time division driving according to the fourth embodiment.
FIG. 10 is a main part circuit diagram of a data line driving circuit according to a fifth embodiment;
FIG. 11 is a main part circuit diagram of a data line driving circuit according to a sixth embodiment;
FIG. 12 is a timing chart of time division driving according to the sixth embodiment.
[Explanation of symbols]
1 Display section
2 pixels
3 Scanning line drive circuit
4 Data line drive circuit
5 Control circuit
41 Driver IC
42 Circuit unit
43 Time division circuit
44 Potential supply unit
45 inverter
46 Level Shifter
47 Inverter
48 Analog multiplexer
49 Latch circuit
50a, 50b second latch circuit
51 Analog switch

Claims (15)

In an electro-optical device,
An output line for outputting data for a plurality of pixels in time series;
A plurality of signal lines provided corresponding to the output lines;
A plurality of data lines provided corresponding to the output lines, the plurality of data lines each having the pixel connected to each of the data lines;
A time division circuit that time-divides the time-series data output to the output line and distributes the time-division data to the plurality of signal lines;
A setting circuit which is provided between the signal line and the data line, and which sets the potential level of the data line by using the data of the signal line as an input;
An electro-optical device, comprising: a potential supply unit that is connected to the signal line and supplies a predetermined potential to the signal line in order to regulate a floating state of the signal line. The electro-optical device according to claim 1, wherein the potential supply unit supplies the predetermined potential to the signal line via a pull-up resistor or a pull-down resistor. The electro-optical device according to claim 1, wherein the potential supply unit supplies the predetermined potential to the signal line via a switching element that is turned on in response to a control signal. The electro-optical device according to claim 1, wherein the setting circuit is an inverter. 4. The electro-optical device according to claim 1, wherein the setting circuit is a level shifter level shifter that converts a potential amplitude of the signal line into a potential amplitude necessary for driving the pixel. 5. . 4. The electro-optical device according to claim 1, wherein the setting circuit is an analog multiplexer configured with an analog switch. The electro-optical device according to claim 1, wherein the setting circuit is a latch circuit that latches data of the signal line. 2. The apparatus according to claim 1, further comprising at least one latch circuit that is provided in a part of the plurality of data lines and latches data output from the setting circuit at a timing according to a control signal. 8. The electro-optical device described in any one of 1 to 7. 9. The electro-optical device according to claim 8, wherein the at least one latch circuit is provided at least on the data line in which the order in which the time-divided data is distributed is first. In an electro-optical device,
An output line for outputting data for a plurality of pixels in time series;
A plurality of data lines provided corresponding to the output lines, the plurality of data lines each having the pixel connected to each of the data lines;
A time-division circuit that time-divides the time-series data output to the output line, and distributes the time-division data to the plurality of data lines;
An electro-optical device comprising: at least one latch circuit that is provided in a part of the plurality of data lines and latches data output from the time division circuit at a timing according to a control signal. apparatus. 11. The electro-optical device according to claim 10, wherein the at least one latch circuit is provided at least on the data line in which the order in which the time-divided data is distributed is first. An electronic apparatus comprising the electro-optical device according to claim 1 mounted thereon. In the driving method of the electro-optical device,
A first step of outputting data for a plurality of pixels to an output line in time series;
A second step of time-dividing the time-series data output to the output line, and distributing the time-division data to a plurality of signal lines provided corresponding to the output line;
A third step of setting the potential level of the data line by using the data of the signal line as an input by a setting circuit provided between the signal line and the data line connected to the pixel;
And a fourth step of supplying a predetermined potential to the signal line in order to regulate a floating state of the signal line. In the driving method of the electro-optical device,
A first step of outputting data for a plurality of pixels to an output line in time series;
A second step of time-dividing the time-series data output to the output line, and distributing the time-division data to a plurality of data lines provided corresponding to the output line;
And a third step of latching a part of the data output to the plurality of data lines at a predetermined timing. 15. The method according to claim 14, wherein the third step is a step of latching at least data output to the data line in which the order in which the time-divided data is distributed is first. Driving method of electro-optical device.

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