JP4272664B2 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
- Publication number
- JP4272664B2 JP4272664B2 JP2006178593A JP2006178593A JP4272664B2 JP 4272664 B2 JP4272664 B2 JP 4272664B2 JP 2006178593 A JP2006178593 A JP 2006178593A JP 2006178593 A JP2006178593 A JP 2006178593A JP 4272664 B2 JP4272664 B2 JP 4272664B2
- Authority
- JP
- Japan
- Prior art keywords
- stem
- lead
- mounting substrate
- anode
- semiconductor module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000003990 capacitor Substances 0.000 claims abstract description 37
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 230000002093 peripheral effect Effects 0.000 claims description 13
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000001816 cooling Methods 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 6
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 6
- 238000012544 monitoring process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 229910052742 iron Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000005679 Peltier effect Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Led Device Packages (AREA)
Description
ステムの下面の一部領域に取付けられ、アノードリード及びカソードリードが下方へ貫通する貫通部が形成された実装基板と、この実装基板の下面に形成され、一端部が各貫通部の周辺を覆う接続部であり他端部が互いに対向する電極である一対の配線導体膜と、実装基板の下面における電極相互間に取付けられたコンデンサと、アノードリード及びカソードリードと対向する配線導体膜の接続部とを電気的に接続する導電性材料とを備えている。
Claims (2)
- 板状のステムの上側にアノード端子とカソード端子とを有する半導体素子を設け、該半導体素子をその下端に有する開口部が前記ステムの上面に固定されたキャップで覆い、前記ステムに対して、その上端が前記半導体のアノード端子及びカソード端子に接続されるとともにその下端が前記ステムの下方に位置するアノードリード及びカソードリードを取付けた半導体モジュールにおいて、
前記ステムの下面の一部領域に取付けられ、前記アノードリード及びカソードリードが下方へ貫通する貫通部が形成された実装基板と、
この実装基板の下面に形成され、一端部が前記各貫通部の周辺を覆う接続部であり他端部が互いに対向する電極である一対の配線導体膜と、
前記実装基板の下面における前記電極相互間に取付けられたコンデンサと、
前記アノードリード及びカソードリードと対向する配線導体膜の接続部とを電気的に接続する導電性材料と
を備えたことを特徴とする半導体モジュール。 - 前記実装基板の前記貫通部が、前記実装基板の外周縁の一部で形成されていることを特徴とする請求項1記載の半導体モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006178593A JP4272664B2 (ja) | 2006-06-28 | 2006-06-28 | 半導体モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006178593A JP4272664B2 (ja) | 2006-06-28 | 2006-06-28 | 半導体モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008010587A JP2008010587A (ja) | 2008-01-17 |
JP4272664B2 true JP4272664B2 (ja) | 2009-06-03 |
Family
ID=39068543
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006178593A Active JP4272664B2 (ja) | 2006-06-28 | 2006-06-28 | 半導体モジュール |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4272664B2 (ja) |
-
2006
- 2006-06-28 JP JP2006178593A patent/JP4272664B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2008010587A (ja) | 2008-01-17 |
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