JP4258671B2 - Integrated circuit and circuit setting generation method thereof - Google Patents

Description

  The present invention relates to an integrated circuit including a reconfigurable integrated circuit and a circuit setting generation method thereof.

  In recent years, with the miniaturization of semiconductor processes, the variation in element characteristics within a chip has increased, and there is concern about a decrease in performance yield. The performance yield is a value obtained by dividing the number of chips that can satisfy the required performance by the number of manufactured chips. As for non-patent documents 1 and patent documents 1 and 2, the variation between chips (or a correlation with a wide range) is corrected after the chip is manufactured by controlling the threshold value of the transistor by the back bias. Is effective. However, when non-correlated variations occur in the chip, particularly for each transistor, it is necessary to reduce the unit of bias control, which causes a problem of increasing circuit overhead.

On the other hand, in a reconfigurable integrated circuit such as a field-programmable gate array (FPGA), the circuit function can be changed any number of times after the chip is manufactured, so a different approach is possible.
A reconfigurable integrated circuit is generally constructed by laying tiles 100 composed of a programmable switch matrix 102 and functional blocks 101 as shown in FIG. 1 like 105, and 104, 103 vertical and horizontal spaces between each tile. Connected in the direction wiring channel.

Functional blocks store programmable logic gates, LUTs (Look Up Tables), adders, multipliers, storage elements, and other circuits that are connected to each other through a switch matrix to achieve a single circuit function. It can be realized.
The switch matrix and functional blocks can be programmed by the setting memory. Configuration memory includes volatile memory such as SRAM (static random access memory), DRAM (dynamic random access memory), flash EEPROM (electronically erasable and programmable read only memory), MRAM (magnetic random access memory), FeRAM Some use (ferroelectric random access memory), and currently use SRAM or flash EEPROM.

Usually, the user describes the required functions using a function description language such as HDL (Hardware description language) or programming language, and generates information that determines the functions of the reconfigurable integrated circuit using a mapping tool or compiler By writing this in the setting memory of the reconfigurable integrated circuit, a desired circuit function can be realized on the reconfigurable integrated circuit.
A process for assigning a function described by a user to a plurality of functional blocks included in a reconfigurable integrated circuit and connecting them to each other is called mapping, and a tool for automatically performing this is called a mapping tool.

Reconfigurable integrated circuits include fine-grain reconfigurable integrated circuits such as FPGAs whose circuit configuration can be changed in units of gates, and coarse-grained reconfigurable circuits that can change circuit configurations in units such as ALU (arithmetic logic unit) and multipliers. There are configurable integrated circuits and reconfigurable integrated circuits that mix them.
In addition, multiple configuration memories that can be switched instantaneously are built in, and a dynamically reconfigurable integrated circuit that realizes multiple circuit functions in a time-sharing manner on one reconfigurable integrated circuit by switching the setting memory is also reconfigured A type of possible integrated circuit.

  As the simplest variation avoidance setting method in a reconfigurable integrated circuit, a method of measuring circuit variations in advance and assigning circuit elements having good characteristics to the most critical part for determining circuit performance can be considered. What is important in realizing such a variation avoidance technique in a reconfigurable integrated circuit is diagnosis of variation for each chip (examine the characteristics of each circuit element) and variation. This mapping is taken into account.

  The diagnosis of variation in the reconfigurable integrated circuit can be performed by setting an element characteristic measuring circuit such as a ring oscillator on the reconfigurable integrated circuit. However, with such a method, it takes a lot of time for diagnosing fine-grained variation, and it is difficult to deal with non-correlated variation for each transistor.

By integrating the circuit for variability diagnosis in a reconfigurable integrated circuit in advance, it is considered that more rapid variability diagnosis can be performed. This is difficult because the detection circuit itself varies.
Conventionally, since the number of possible circuit states in a reconfigurable integrated circuit is remarkably large, the difficulty of fault diagnosis has been raised as one of the causes of cost increase. It is clear that the diagnosis of variation is a more difficult problem because it requires continuous numerical detection rather than binary detection as in failure diagnosis. Thus, it is clear that adding variation diagnostics to the process of manufacturing a reconfigurable integrated circuit results in a significant cost increase.

  In addition, separate mapping for each chip has a problem that it takes a very long time to manufacture a product on which the chip is mounted, and there is a problem of stability of an automatic mapping tool. It is difficult for the algorithm of the automatic mapping tool to stably provide an optimal solution. When mapping is performed for each chip, it is necessary to leave a performance margin in consideration of the instability of the solution, resulting in performance degradation.

On the other hand, in the prior application (Patent Document 3) by the present inventors, in a reconfigurable integrated circuit, a plurality of circuit settings having the same performance stochastically for the same function but following different random variables are prepared. Disclosed is a method and system for improving performance yield by implementing and testing each circuit setting on a chip and using only circuit settings that can achieve the target performance. This method is low-cost because it does not require variation diagnosis, and the number of circuit settings to be prepared is less than the method of setting circuits on a chip-by-chip basis, so the stability problem of the automatic mapping tool can be greatly reduced. It is. If this method has the same performance stochastically for the same function but can create as many circuit settings as possible according to different random variables as quickly and stably as possible, the method of Patent Document 3 will further improve the performance yield. It becomes possible.
JP 2000-286387 A JP 2004-20325 A Japanese Patent Application No. 2006-173378 DR Ditzel, “Power Reduction using LongRun2 in Transmeta's Efficiency Processor”, Spring Processor Forum Presentation, 2006.

However, in the method disclosed in Patent Document 3, it is necessary to prepare a plurality of circuit settings in advance.
Accordingly, it is an object of the present invention to provide an integrated circuit and a circuit setting generation method thereof that can easily obtain a plurality of circuit settings only by once setting the circuit with a mapping tool.

In order to solve the above problems, the present invention provides the following means.
(1) at least a portion of the wiring between the array of the basic tiles constituting the reconfigurable integrated circuit, n (n is an integer of 1 or more) are connected to the dimension of the torus Rutotomoni uniform each connection An integrated circuit characterized by being made with an appropriate wiring length .
(2) n horizontal or vertical lines of the basic tile array constituting the reconfigurable integrated circuit (n is an integer of 1 or more) are connected to the dimension of the torus Rutotomoni uniform each connection An integrated circuit characterized by being made with an appropriate wiring length .
(3) In an array of sub-arrays of basic tiles constituting the reconfigurable integrated circuit, part or all of the sub-array n (n is one or more an integer) are connected to the dimension of the torus Rutotomoni each connection Is an integrated circuit characterized by having a uniform wiring length .
(4) integrated circuits horizontal or vertical sub-arrays, characterized in that connected Rutotomoni each connected to torus have been made with a uniform wire length.
(5) integrated circuit torus connected to Rutotomoni each connected array or sub-array has been made with a uniform wire length, characterized in that it is logically connected by more than one length wire segments.
(6) For the integrated circuit described in (1) or (2), a plurality of different circuit settings having the same function implemented on a reconfigurable integrated circuit but different in performance are set to one A circuit setting generation method for an integrated circuit, wherein the circuit setting is generated by moving the circuit setting along a direction connected to a torus of an array of basic tiles.
(7) For the integrated circuit described in (3) or (4), a plurality of different circuit settings having the same function implemented on a reconfigurable integrated circuit but different in performance are set to one A circuit setting generation method for an integrated circuit, wherein the circuit setting is created by moving the circuit setting along a direction connected in a torus shape in all subarrays.

According to the present invention, since a part of the array is connected by the torus-like wiring, and each connection is made with a uniform wiring length, the circuit setting moved in the torus plane is always the circuit setting before moving. Probably the same performance. Moving moves changes the position of the critical path (signal path that determines performance) on the reconfigurable integrated circuit of that circuit setting, so the performance of the moved circuit setting is different from that of the original circuit setting. Follow random variables. Therefore, once a circuit setting is created by an automatic mapping tool, a desired plurality of circuit settings can be obtained by moving the circuit setting within the torus plane.

  FIG. 2 shows a tile array of reconfigurable integrated circuits connected by a two-dimensional torus. When embedding a 2D torus in a 2D plane to ensure that the probabilistic performance does not change when moving the circuit settings before moving, between logically adjacent tiles in the torus plane It is necessary to make all the connection lengths uniform, so that one tile is skipped in the order on the torus surface in the axial direction on the two-dimensional plane, and when reaching the end, this time the torus surface starts from the opposite direction. Place the tile at the position you skipped first in the above order (see 204 coordinates).

Incidentally, an important feature in manufacturing an array-type reconfigurable integrated circuit is that it can be realized simply by arranging the same tiles. However, a reconfigurable integrated circuit having this two-dimensional torus-like wiring also has the advantage of being 200 These tiles can be easily realized by simply arranging tiles such as 203 and connecting them so as to loop the wiring channels at the ends.

The configuration of FIG. 2 seems to require twice as many wirings in the 201 horizontal and 202 vertical directions as compared to the configuration of FIG. 1, but this is a torus that halves the total wiring amount. This is offset by the effect of the line wiring. In addition, the physical distance between adjacent tiles is twice as long as that in the configuration of FIG. 1 (actually, the number of switches is reduced by half due to the torus-like wiring, and the tile area is reduced, so that it is smaller than twice. However, the main cause of the path delay of such a reconfigurable integrated circuit is the switch delay, and the increase in delay due to the double metal wiring length is several percent. Rather, the formation of the torus reduces the maximum path delay because the maximum number of switch passing stages is halved.

  On the other hand, if the circuit setting is moved in the torus plane, the input / output positions of the chip IO pad and the circuit may change significantly, resulting in inconvenience. In order to avoid this problem, it is possible to introduce a torus-like wiring into only a part of the array to limit the area where the circuit setting moves.

  FIG. 3 shows a configuration in which only the horizontal direction of the array is connected by a torus-like wiring. 300 in FIG. 3 represents a tile, the horizontal wiring channel 301 is doubled as in FIG. 2, and the vertical wiring channel 302 is one, similar to the wiring channel in FIG. However, each wiring channel is composed of a plurality of wiring tracks). The tile array 303 is formed by arranging tiles 300, and the wiring channels at both ends in the horizontal direction are looped and connected. In the coordinate system 304, the horizontal direction is the same as in FIG. 2, and the vertical direction is the same as in FIG. In this configuration, the circuit settings are movable only in the horizontal direction, and the number of different circuit settings obtained by movement is halved compared to the case of the two-dimensional torus, but the movement of the input / output positions of the circuit is horizontally It can be limited to.

  It is also possible to form a sub-array as shown in FIG. 4 and connect the inside with a torus (FIG. 4 omits functional blocks). In the tile 400, 401 and 404 indicate connections inside the subarray, and 402 and 403 indicate wiring channels for connection between the subarrays. When the tiles 400 are arranged in 4 × 4 and the subarray 405 is formed, 401 and 404 are connected so as to loop at the end of the subarray. The sub-arrays 405 are further arranged in 2 × 2, for example, to constitute the entire array 406 (see FIG. 5). In this configuration, the circuit setting causes the circuits in each subarray to move simultaneously in the same direction. This reduces the number of different circuit settings obtained by movement down to the number of tiles in the subarray, but the input / output movement range of the circuit can also be limited to within the subarray range.

In the configuration of FIG. 4 as well, it is conceivable that the torus is connected only in the horizontal direction within the sub-array as in the configuration of FIG.
The possibility of the configuration in FIGS. 2 to 4 is a trade-off problem between the IO latency and the variation correction power, which varies depending on the IO latency required by the main application of the reconfigurable integrated circuit. However, in many cases, the delay of the IO pad is much larger than the wiring delay inside the chip, so that the IO latency does not become a problem.

  FIG. 6 shows a reconfigurable integrated circuit connected by a two-dimensional torus. Here, for example, it is assumed that the delay time for the signal to pass through each switch matrix in FIG. 6 varies as shown in FIG. 7 (the numerical values written in each cell in FIG. 7 indicate the delay time of each switch matrix). ing). At this time, if the critical path that determines the performance of the circuit passes through the seven-stage switch matrix as shown in FIG. 8, the delay time is 76. On the other hand, if the entire circuit is translated in the x and y directions by −2 in the torus plane, the path of FIG. 8 moves to the position of FIG. 9, the delay time is reduced to 50, and variations are avoided.

  That is, if one circuit setting is generated by an automatic mapping tool, a plurality of circuit settings can be easily created by moving in the torus plane and having stochastically the same performance but different random variables. Furthermore, the performance yield can be improved by testing the plurality of created circuit settings according to the invention of Patent Document 3 and using the circuit settings at positions that satisfy the performance requirements.

  In recent reconfigurable integrated circuits, it is common to connect with a plurality of segment length wirings in order to reduce delay caused by passing through the switch matrix. FIG. 10a shows a one-dimensional array connected by length 2 wiring segments. Although not shown in the two-dimensional case, it can be easily realized by connecting in the vertical direction similarly to the horizontal wiring in FIG. 10a. In addition, the case where a wiring segment having a length of 2 or more is used can be easily realized.

  A wiring segment having a length of 2 is a wiring connected by skipping a switch matrix of one tile. At first glance, a one-dimensional array connected by two wire segments of length is similar to a one-dimensional array connected by a torus (Fig. 10b), but in the case of a torus, the wiring must be folded at the end of the array. And the point that connection from the inner point of the wiring segment to the switch matrix is unnecessary. Connection to the switch matrix at the inner point of the wiring segment is necessary to ensure connectivity between any two functional blocks.

  On the other hand, the connection of the torus can also be constituted by a plurality of lengths of wiring segments. The distance between tiles in the torus plane is called a logical distance. FIG. 10c shows a one-dimensional torus array composed of logically length 2 wiring segments. Since the one-dimensional torus is embedded in a straight line, a logical length of 2 corresponds to a physical distance of 4. Since the wiring segment that exits the tile of coordinate x in the torus is always connected to the tile of (x + 2) mod a (array size), the wiring is looped at the end of the array as such. FIG. 10 c shows only the case of a wiring segment having a logical length of 2 with a one-dimensional torus. However, in the case of two dimensions, a case of a longer wiring segment can be easily realized. Further, the present invention can be easily applied to the configuration as shown in FIGS.

Industrial applicability

  It can be used for a system LSI having a reconfigurable integrated circuit such as an FPGA as a core, and mobile terminals, digital home appliances, communication devices, servers, storages, supercomputers, and the like, which are their main application fields.

It is a general structural example of a reconfigurable integrated circuit. It is an example of a tile array connected by a two-dimensional torus. It is an example of the tile array connected with the torus only in the horizontal direction. It is an example of a tile array constituting subarrays connected by a 4 × 4 two-dimensional torus. This is an example of a tile array in which subarrays 405 are arranged in 2 × 2. This is an example of an 8x8 2D tora style array. 8 is an example of a switch matrix delay for each tile of an 8x8 2D Tora style array. FIG. 8 is an example of a delay path in an 8 × 82 dimensional tora style array having the delay of FIG. 8 is an example of a delay path obtained by translating the delay path in FIG. 7 by −2 in the x and y directions, respectively. It is an example of the array which has several wiring segment length.

Explanation of symbols

100 tile 101 functional block 102 switch matrix 103 horizontal wiring 104 vertical wiring 105 tile array 200 tile 201 horizontal wiring channel 202 vertical wiring channel 203 tile array 204 coordinate system 300 tile 301 horizontal wiring channel 302 vertical direction Wiring channel 303 tile array 304 coordinate system 400 tile 401 horizontal wiring channel in sub-array 402 horizontal wiring channel between sub-arrays 403 vertical wiring channel in sub-array 404 vertical wiring channel between sub-arrays 405 connected by a two-dimensional torus Subarray

Claims (7)

At least a portion of the wiring between the basic tiles constituting the reconfigurable integrated circuit array, n (n is 1 or more an integer), respectively connected to the dimension of the torus Rutotomoni connected uniform wire length An integrated circuit characterized in that it is made of . Wiring in the horizontal direction or the vertical direction of the base tile constituting the reconfigurable integrated circuit array, n (n is 1 or more an integer), respectively connected to the dimension of the torus Rutotomoni connection is uniform wiring An integrated circuit characterized by being made in length . In an array of sub-arrays of basic tiles constituting the reconfigurable integrated circuit, part or all of the sub-array n (n is one or more an integer) is uniform connected Rutotomoni each connected to dimension torus An integrated circuit characterized by being made of a wiring length . The integrated circuit of claim 3, wherein the horizontal or vertical sub-array is connected to Rutotomoni each connected to torus have been made with a uniform wire length. Torus connected to Rutotomoni each connected array or sub-array has been made with a uniform wiring length is logically of claims 1 to 4, characterized in that it is connected by more than one length wire segments The integrated circuit according to any one of claims.   The integrated circuit according to claim 1 or 2, wherein a plurality of different circuit settings according to a random variable having the same function that is realized on a reconfigurable integrated circuit but having different performances, a single circuit setting as a basic tile A method for generating a circuit setting of an integrated circuit, wherein the circuit setting is generated by moving the array along a direction connected to a torus. The integrated circuit according to claim 3 or 4, wherein a plurality of different circuit settings according to a random variable having the same function implemented on a reconfigurable integrated circuit but different in performance are assigned to all the circuit settings. A circuit setting generation method for an integrated circuit, wherein the circuit setting is generated by moving the subarray along a direction connected in a torus shape.

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