JP4250283B2 - Interrupt processing circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interrupt processing circuit that sequentially processes interrupt requests from a plurality of interrupt inputs having the same importance according to priority.
[0002]
[Prior art]
The interrupt processing circuit accepts and processes interrupt requests from external factors. When interrupt processing is started, the current processing is interrupted and the interrupt processing is executed. The original process that was interrupted later is resumed. A conventional interrupt processing circuit has a plurality of interrupt inputs, as represented by an interrupt controller of model number 8259 manufactured by Intel, for example, and priorities determined in hardware for each interrupt input are determined. Is given.
[0003]
The interrupt controller of model No. 8259 adopts a method called automatic rotation. For example, as disclosed in Japanese Patent Laid-Open No. 4-363748, this method sets the priority order of interrupt inputs currently being interrupted at the end of the processing, that is, a microprocessor (hereinafter referred to as a CPU). ) Is the lowest when an EOI (End Of Interrupt) is received, and a predetermined priority order is sequentially assigned to other interrupt inputs.
[0004]
In this case, the priority order can be changed by software to some extent, but in general, it is difficult to dynamically change the priority order according to the situation. In particular, if the priority is determined in advance when the interrupt input has the same level of importance, since the interrupt processing for the interrupt request from the higher-order interrupt input is performed sequentially, the lower-order There was a situation where processing for interrupt requests from interrupt inputs was delayed, causing inconvenience.
[0005]
Hereinafter, the conventional interrupt processing circuit and its problems will be described by taking the interrupt processing circuit adopting the above-described automatic rotation as an example.
FIG. 8 is a block diagram showing an example of the internal structure of a conventional interrupt processing circuit.
The interrupt processing circuit 36 shown in the figure employs automatic rotation, and includes an IRR register 12, a priority assignment circuit 16, an ISR register 18, and a control circuit 20.
[0006]
In the interrupt processing circuit 36, first, the IRR register 12 is an interrupt request register. In the example shown in the figure, when an interrupt request is generated from the interrupt inputs IR0 to IR5, the corresponding bit of the IRR register 12 is set to '1' and the interrupt processing circuit 36 interrupts the IRR register 12. When the process is started, the corresponding bit is reset to “0”. The output from the IRR register 12 is input to the priority order assignment circuit 16.
[0007]
Subsequently, the priority order assigning circuit 16 assigns a priority order to each of the interrupt inputs IR0 to IR5 when receiving the signal EOI from the CPU.
The ISR register 18 is an in-service register and is bi-directionally connected to the priority assignment circuit 16. In the ISR register 18, the bit corresponding to the interrupt processing currently being processed by the interrupt processing circuit 36 is set to “1”, and when the processing is completed, the corresponding bit is reset to “0”.
[0008]
Finally, the control circuit 20 controls the operation of the entire interrupt processing circuit 36 and interfaces with the interrupt processing circuit 36 and the CPU. The control circuit 20, the IRR register 12, and the priority assignment circuit 16 Are connected bidirectionally, and a control signal from the control circuit 20 is input to the ISR register 18. An interrupt request signal INT is input from the control circuit 20 to the CPU, and an interrupt permission signal INTA is input from the CPU to the interrupt processing circuit 36.
[0009]
As shown by the value of the signal PRI in FIG. 9A, the interrupt inputs IR5 to IR0 have a higher priority as the interrupt input is given a smaller number. Here, as shown in FIG. 5B, when interrupt requests are simultaneously made from the interrupt inputs IR0, 3 and 5, the values of the corresponding bits 0, 3 and 5 of the IRR register become '1'. To do. Since the interrupt input IR0 has the highest priority at this time, the interrupt processing circuit 36 first accepts an interrupt request from the interrupt input IR0.
[0010]
Upon receiving the interrupt input IR0, the interrupt processing circuit 36 sets the value of the bit corresponding to the interrupt input IR0 of the ISR register to “1”, and the control circuit 20 sends an interrupt request signal INT to the CPU. Make an interrupt request. When it is approved by the CPU, an interrupt permission signal INTA is given from the CPU, and the interrupt processing circuit 36 issues an interrupt vector or the like to the CPU. In response to this, the CPU interrupts the currently executing process and executes the interrupt process corresponding to the interrupt input IR0.
[0011]
Here, it is assumed that the interrupt input IR2 is further input during the interrupt process corresponding to the interrupt input IR0. At this time, as shown in FIG. 9C, the values of the bits 2, 3, and 5 corresponding to the interrupt inputs 2, 3, and 5 are “1”. At this time, since the priority of the interrupt input IR2 is lower than that of the IR0, the interrupt process corresponding to the interrupt input IR0 currently being processed is not interrupted and the process does not shift to the process corresponding to the IR2.
[0012]
After that, when the interrupt processing corresponding to the interrupt input IR0 is completed and the interrupt processing circuit 36 receives the signal EOI issued by the CPU, the priority corresponding to the interrupt input IR0 is lowest in the automatic rotation method. Thus, the priorities of the other interrupt inputs IR1 to IR5 are increased one by one. That is, as shown in FIG. 4D, the priority of the interrupt input IR1 is the highest, then the priority of IR2 to 5, and the priority of IR0 is changed to the lowest.
[0013]
Accordingly, the interrupt processing circuit 36 accepts the next interrupt request from the interrupt inputs IR3 and IR5 having the same importance prior to the interrupt input IR2. Is an interrupt request from the interrupt input IR2 as shown in the timing chart of FIG. This means that, in the worst case, the interrupt input IR5 having the lowest priority may wait for the time during which the three processes IR2, 3, and 4 will be completed.
[0014]
In addition, when the number of interrupt inputs (interrupt factors) that can be accepted by the interrupt processing circuit 36 is not a small number of 6 as in the above example, but is a larger number, the time that must be waited is accordingly. Could only be longer. Accordingly, in the conventional interrupt processing circuit 36, software must be created in consideration of such a worst case, and this has a problem that it becomes a restriction at the time of software coding.
[0015]
On the other hand, there is another method for solving the above problem. As shown in FIG. 11, an OR gate 38 is inserted in the preceding stage of the IRR register 12. For example, two interrupt inputs IR00 and IR01 are set as one interrupt input IR0, which is solved by software for processing them. In this case, at the beginning of the interrupt process that is the target of the interrupt input, check which interrupt input is the request, and read the memory or register that previously stored the interrupt factor processed last time. The process branches after making the judgment.
[0016]
However, in this method, in order to add the OR gate 38, both hardware and software have to be changed, which is troublesome, and the interrupt request from which interrupt input is determined by software. Because it is necessary, there are drawbacks such as a long interrupt response time.
[0017]
[Problems to be solved by the invention]
An object of the present invention is to solve the problems based on the prior art, and when an interrupt request is made from a plurality of interrupt inputs having the same priority, the order in which the interrupt requests are made and the priority thereof, It is an object of the present invention to provide an interrupt processing circuit capable of reassigning the priority order to the interrupt input according to the above.
[0018]
[Means for Solving the Problems]
To achieve the above object, the present invention stores an interrupt request from a plurality of interrupt inputs, and resets the value of a corresponding bit when an interrupt process is started,
An ISR register that stores an interrupt input corresponding to the interrupt process currently being processed;
An ILR register for storing the value of the IRR register at the time when the interrupt processing is started;
The interrupt request stored in the ILR register among the plurality of interrupt inputs based on the values of the IRR register, the ISR register, and the ILR register each time the interrupt process currently being processed ends . Although no interrupt request is stored in the ILR register for an interrupt input of 1, an interrupt request is made after the interrupt process currently being processed is started. request have rows reallocate priority providing a second higher priority compared to the interrupt input stored, then determine the interrupt request from the high interrupt input highest priority to be processed A priority assignment circuit to
There is provided an interrupt processing circuit characterized by comprising a control circuit for controlling the entire operation and interfacing with a microprocessor.
Here, the priority assignment circuit further to the second interrupt input, given compared to high priority on third interrupt input the interrupt request to the IRR register is not stored and Turkey is preferred.
The priority assignment circuit further includes a Turkey gives the lowest priority to an interrupt input which is remembers the ISR register is preferred.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
In the following, the interrupt processing circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
[0020]
FIG. 1 is a block diagram of an embodiment of an interrupt processing circuit according to the present invention.
The interrupt processing circuit 10 in the illustrated example stores the status of the interrupt request when the interrupt process occurs, and responds to the interrupt input that was requested when the interrupt process occurred when the interrupt process ends. It operates to preferentially assign a high priority, and includes an IRR register 12, an ILR register 14, a priority assignment circuit 16 ', an ISR register 18, and a control circuit 20.
[0021]
The interrupt processing circuit 10 of the present invention shown in the figure has six interrupt inputs IR0 to IR5 to facilitate comparison with the conventional interrupt processing circuit 36 shown in FIG. 14 is the same as the conventional interrupt processing circuit 36 except for the point that it has 14 and the function of the priority assignment circuit 16 'are slightly different, and is a component having the same function. The IRR register 12, the ISR register 18, and the control circuit 20 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0022]
In the interrupt processing circuit 10, the ILR register 14 is an interrupt request storage register, and the output from the IRR register 12 is input to the ILR register 14. As described above, when the interrupt process is started, the value of the bit corresponding to the IRR register 12 is reset to “0”. In this embodiment, the ILR register 14 stores the value of the IRR register 12 after the bit value corresponding to the started interrupt processing is reset to “0”.
[0023]
The output from the ILR register 14 is input to the priority assignment circuit 16 ′ together with the output from the IRR register 12. The priority order assignment circuit 16 ′ uses a priority order register (to be described later) to finish each interrupt process, and from a microprocessor (hereinafter referred to as “CPU”) (not shown) a signal EOI (meaning the end of the interrupt process). Each time End Of Interrupt) is input, the priority order is reassigned to the interrupt inputs IR0 to IR5.
[0024]
Next, FIG. 2 shows a block diagram of an embodiment of a priority order assignment circuit used in the interrupt processing circuit of the present invention.
As shown in the figure, the priority order assignment circuit 16 ′ includes a priority order register 22, a priority order determination circuit 24, and a priority order change circuit 26. The figure also shows an AND gate 28 that takes the logical product of outputs IRR0 to INR from the IRR register 12 and outputs ILR0 to ILR from the ILR register 14.
[0025]
First, the priority order register 22 stores a signal PRI for assigning priority orders of the interrupt inputs IR0 to IR5. The state of the signal PRI is a permutation n! Where n is the number of interrupt inputs. As described above, since n = 6 in this embodiment, the number of permutations of the signal PRI is 6! = 720. Therefore, the assigned priority order may be stored as it is as the signal PRI, but it is preferable to encode the signal PRI in order to prevent the circuit from becoming large.
[0026]
In the illustrated example, an example in which the number of interrupt inputs n = 6 is shown, but in practice, there may be a larger number of interrupt inputs. In this case, since the circuit scale is increased as described above, in order to prevent this, not only the signal PRI is encoded, but two to three interrupt inputs are provided for all interrupt inputs. By combining the present invention as a group and applying the present invention to each group, a practically sufficient effect can be obtained.
[0027]
Subsequently, based on the signal PRI from the priority register 22, the priority determination circuit 24 is requested to interrupt the output from the AND gate 28 at “1”, that is, almost simultaneously with the interrupt process currently being processed. Alternatively, an interrupt request is made between the start of the previous interrupt process and the end thereof, and the interrupt inputs IR0 to IR5 having the highest priority for which the interrupt process has not yet started are determined. The determination result is input to the ISR register 18 and the priority change circuit 26 as a determination output signal.
[0028]
The priority change circuit 26 outputs the determination output signal output from the priority determination circuit 24 and input to the ISR register 18, the values of the IRR register 12 and the ILR register 14, and the signal PRI output from the priority register 22. And determine a new priority according to the following procedure. This new priority is stored in the priority register 22 at the timing when the signal EOI is input from the CPU, and is used to determine the priority of the next interrupt process.
[0029]
The procedure for determining priority by the priority changing circuit 26 will be described below.
Procedure 1) Lower the bit of which “1” is set in the ISR register 18, that is, the priority of the interrupt input corresponding to the interrupt process currently being processed.
Procedure 2) Among the bits for which "1" is set in the ILR register 14, the higher priority is assigned in order from the bit assigned the higher priority by the current priority register 22.
[0030]
Note that “1” is set to the bit of the IRR register 12 corresponding to the bit for which “1” is set in the ILR register 14. Therefore, in the above procedure 2), the AND gate 28 makes a bit for which both are set to '1', that is, an interrupt request is made almost simultaneously with the interrupt process currently being processed, or the previous interrupt process. An interrupt request is made during the period from the start to the end, and a bit corresponding to an interrupt input that has not yet started interrupt processing is detected.
[0031]
Procedure 3) '1' is set in the IRR register 12, and the bit not subject to the procedure 2) (the value of the IRR register 12 is '1' and the value of the ILR register 14 is '0') Among the bits corresponding to the interrupt input for which an interrupt request has been made after the interrupt process being currently processed is started, a higher priority is assigned by the current priority register 22. The highest priority is assigned in order from the existing bit.
[0032]
Procedure 4) Bits not subject to the above procedures 1) to 3) (bits with the value of the IRR register 12 being “0” and the value of the ILR register 14 being “0”), that is, an interrupt request has been made. A bit corresponding to a non-interrupt request is assigned a predetermined priority, for example, in ascending order of numerical values of the subscripts of the interrupt inputs IR0 to IR5, or a higher priority by the current priority register 22. The highest priority is sequentially assigned in order from the bit being set.
[0033]
Step 5) Finally, the priority assigned according to the above steps 1) to 4) or the encoded value is stored in the priority register 22.
[0034]
The configuration of the interrupt processing circuit 10 of the present invention is basically as described above.
Next, the operation of the interrupt processing circuit 10 of the present invention will be described.
[0035]
As shown by the value of the signal PRI in FIG. 3 (a), the interrupt inputs IR5 to 0 have higher priority as the interrupt inputs given the same small numbers. Here, as shown in FIG. 5B, interrupt requests are simultaneously made from the interrupt inputs IR0, 3, and 5, and the values of the bits 0, 3, and 5 of the corresponding IRR registers 12 become "1". Suppose. Since the interrupt input IR0 has the highest priority at this time, the interrupt processing circuit 10 first accepts an interrupt request from the interrupt input IR0.
[0036]
When receiving the interrupt input IR0, the interrupt processing circuit 10 resets the bit corresponding to the interrupt input IR0 of the IRR register 12 to “0” and sets the value of the bit corresponding to the interrupt input IR0 of the ISR register 18 to “0”. Set to '1'. As shown in FIG. 3C, the value of the IRR register 12 after reset is stored in the ILR register 14 at this time. Then, the control circuit 20 makes an interrupt request to the CPU. The subsequent operation is as described above.
[0037]
Here, it is assumed that the interrupt input IR2 is further input during the interrupt process corresponding to the interrupt input IR0. As shown in FIG. 3 (d), the value of the IRR register 12 at this time is the value of the bits 2, 3, and 5 corresponding to the interrupt inputs 2, 3, and 5, respectively. The value of bit 2 of 14 remains “0”. Since the interrupt input IR2 has a lower priority than the IR0, the interrupt process corresponding to the interrupt input IR0 currently being processed is interrupted and the process does not shift to the process corresponding to the IR2.
[0038]
After that, when the interrupt processing corresponding to the interrupt input IR0 is completed and the interrupt processing circuit 10 receives the signal EOI issued by the CPU, the priority order allocation circuit 16 ′, as shown in FIG. First, according to the procedure 1), the priority corresponding to the interrupt input IR0 is set to the lowest '5'. According to the procedure 2), the highest priority is assigned to the interrupt input IR3 from the value of the ILR register 14 and the state of the signal PRI. “0” is assigned, and the second highest priority “1” is assigned to the interrupt input IR5.
[0039]
Subsequently, according to the procedure 3), the third priority “2” is assigned to the interrupt input IR2 from the value of the IRR register 12 and the signal PRI, and the priority assigned by the signal PRI according to the procedure 4). In the order of ranking, the fourth highest priority “3” is assigned to the interrupt input IR1, and the fifth highest priority “4” is assigned to the interrupt input IR4. The assigned priority order is stored in the priority order register 22 according to the procedure 5).
[0040]
Similarly, the interrupt processing circuit 10 accepts the interrupt input IR3, and similarly resets the bit corresponding to the interrupt input IR3 of the IRR register 12 to “0” as shown in FIG. 4 (f). The value of the bit corresponding to the interrupt input IR3 of the ISR register 18 is set to '1'. The value of the IRR register 12 after reset is stored in the ILR register 14 at this time. Then, the control circuit 20 makes an interrupt request to the CPU. The subsequent operation is the same.
[0041]
Here, when the interrupt input IR1 is further input during the interrupt processing corresponding to the interrupt input IR3, the value of the IRR register 12 at this time becomes the interrupt input as shown in FIG. The values of bits 1, 2, 5 corresponding to 1, 2, 5 respectively become “1”, but the value of bit 1 of the ILR register 14 remains “0”. Since the interrupt input IR1 has a lower priority than the IR3, the interrupt process corresponding to the interrupt input IR3 currently being processed is interrupted and the process does not shift to the process corresponding to the IR1.
[0042]
Thereafter, when the interrupt processing corresponding to the interrupt input IR0 is completed and the interrupt processing circuit 10 receives the signal EOI issued by the CPU, the priority allocation circuit 16 ′ interrupts according to the procedures 1) to 5). Priorities are assigned to the inputs IR0 to IR5, respectively. That is, as shown in FIG. 4 (h), the highest priority is assigned to the interrupt input IR5, and the priority is assigned in the order of the interrupt inputs IR2, 1, 4, 0, 3 in the same manner.
[0043]
As described above, in the interrupt processing circuit 10 of the present invention, when an interrupt request is made from a plurality of interrupt inputs at the same time, a plurality of interrupt requests are made in accordance with the priorities stored in the priority register in advance and at different timings. When an interrupt request is made from an interrupt input, the priorities are reassigned in accordance with the order in which the interrupt requests are made, and as shown in the timing chart of FIG. Interrupt processing is started in the order of 2,1.
[0044]
Next, FIG. 6 shows a configuration circuit diagram of an embodiment of the priority determination circuit.
First, FIG. 2 shows a priority determination circuit 24 used in the interrupt processing circuit 10 of the present invention when there are two interrupt inputs, and comprises an AND gate 30 and two AND-OR gates 32. Has been. 2 is the AND gate 28 shown in FIG. 2, and outputs of the AND gate 28 corresponding to the bits 0 and 1 are used as signals IN0 and IN1, respectively.
[0045]
In the figure, a signal PRI is an output from the priority order register 22 and is obtained by encoding a value indicating the priority order. Therefore, when the signal PRI is “0”, the interrupt input IR0 has priority, and when the signal PRI is “1”, the interrupt input IR1 has priority. Signals IS0, 1 are determination output signals input to the ISR register 18, and are determined as shown in the truth table of FIG. 7 according to the states of the signal PRI and the signals IN0, 1.
[0046]
As already described, in the conventional interrupt processing circuit, the priority order is fixed to some extent for each interrupt input. On the other hand, in the interrupt processing circuit 10 of the present invention, the state of the interrupt request when the interrupt process occurs is stored, and at the end of the interrupt process, the interrupt that was interrupted when the interrupt process occurred Since the operation is performed so as to preferentially assign a high priority to the input, there is an advantage that an interrupt request from a low-order interrupt input is not waited more than necessary.
[0047]
The interrupt processing circuit of the present invention is basically as described above.
The interrupt processing circuit of the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications and changes may be made without departing from the spirit of the present invention. It is.
[0048]
【The invention's effect】
As described above in detail, the interrupt processing circuit according to the present invention is configured to process a plurality of interrupt inputs based on the values of the IRR register, the ISR register, and the ILR register each time the interrupt process currently being processed is completed. The priority is reassigned, and the interrupt request from the interrupt input with the highest priority to be processed next is determined.
Thus, according to the interrupt processing circuit of the present invention, when an interrupt request is made from a plurality of interrupt inputs having the same priority, the interrupt is made according to the order in which the interrupt requests are made and the priority. Processing can be performed, and the occurrence of inconvenience that processing for interrupt requests from low-order interrupt inputs is delayed can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of an interrupt processing circuit according to the present invention.
FIG. 2 is a block configuration diagram of an embodiment of a priority assignment circuit used in the interrupt processing circuit of the present invention.
FIGS. 3A to 3E are tables of an embodiment corresponding to the operation of the interrupt processing circuit of the present invention shown in FIG.
4 (f) to (h) are tables of an embodiment corresponding to the subsequent operation of the interrupt processing circuit of the present invention shown in FIG.
FIG. 5 is a timing chart of an embodiment showing the operation of the interrupt processing circuit of the present invention.
FIG. 6 is a configuration circuit diagram of an embodiment of a priority determination circuit used in the interrupt processing circuit of the present invention.
7 is a truth table of one embodiment showing the operation of the priority determination circuit shown in FIG. 6. FIG.
FIG. 8 is a block diagram of an example of a conventional interrupt processing circuit.
9 (a) ~ (d) is a table of an example corresponding to the operation of the conventional interrupt processing circuit shown in FIG.
FIG. 10 is a timing chart showing an example of the operation of a conventional interrupt processing circuit.
FIG. 11 is a block diagram of another example of a conventional interrupt processing circuit.
[Explanation of symbols]
10, 36 Interrupt processing circuit 12 IRR register 14 ILR registers 16, 16 'Priority assigning circuit 18 ISR register 20 Control circuit 22 Priority register 24 Priority judging circuit 26 Priority changing circuit 28, 30 AND gate 32 AND-OR Gate 38 OR gate

Claims (3)

An IRR register that stores interrupt requests from a plurality of interrupt inputs and that resets the value of the corresponding bit when the interrupt processing is started;
An ISR register that stores an interrupt input corresponding to the interrupt process currently being processed;
An ILR register for storing the value of the IRR register at the time when the interrupt processing is started;
The interrupt request stored in the ILR register among the plurality of interrupt inputs based on the values of the IRR register, the ISR register, and the ILR register each time the interrupt process currently being processed ends . Although no interrupt request is stored in the ILR register for an interrupt input of 1, an interrupt request is made after the interrupt process currently being processed is started. request have rows reallocate priority providing a second higher priority compared to the interrupt input stored, then determine the interrupt request from the high interrupt input highest priority to be processed A priority assignment circuit to
An interrupt processing circuit comprising a control circuit for controlling the entire operation and interfacing with a microprocessor. The priority assignment circuit further to the second interrupt input, the interrupt request to the IRR register and Turkey given a higher priority as compared to the third interrupt input which is not stored The interrupt processing circuit according to claim 1. The priority assignment circuit further interrupt processing circuit according to claim 1, wherein the benzalkonium given lowest priority to the interrupt inputs are remembers the ISR register.

Images