JP4231275B2 - Silicon wafer manufacturing method, manufacturing apparatus thereof, and silicon wafer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a silicon wafer, a manufacturing apparatus therefor, and a silicon wafer, and more particularly to a manufacturing method, a manufacturing apparatus, and a silicon wafer manufactured by these that can reduce the size of void defects and the density of void defects. .
[0002]
[Background Art and Problems to be Solved by the Invention]
Silicon crystals are produced by pulling and growing by CZ (Czochralski method). The pull-grown silicon crystal ingot is sliced into silicon wafers. A semiconductor device is manufactured through a device process for forming a device layer on the surface of a silicon wafer.
[0003]
However, crystal defects called “Grown-in defects” (defects introduced during crystal growth) occur during the growth of silicon crystals.
[0004]
In recent years, with the progress of high integration and miniaturization of semiconductor circuits, it is no longer allowed for such a glow-in defect to exist near the surface layer of a silicon wafer in which devices are formed. For this reason, the possibility of producing defect-free crystals has been studied.
[0005]
In general, crystal defects included in a silicon crystal and deteriorating device characteristics are the following three types of defects.
[0006]
a) Void (cavity) defect, which is called COP (Crytstal Originated Particle), etc., which is caused by agglomeration of pores.
[0007]
b) OSF (Oxidation Induced Stacking Fault)
c) Dislocation loop clusters formed by aggregation of interstitial silicon (interstitial silicon type dislocation defects, I-defect).
[0008]
A defect-free silicon single crystal is recognized or defined as a crystal that does not contain or substantially does not contain any of the above three types of defects.
[0009]
It is known that the behavior of the above three types of defects changes as follows depending on the growth conditions. This will be described with reference to FIG. In FIG. 2, the horizontal axis represents a growth condition V / G1, which will be described later. If G1 is fixed, it can be considered as a function of the growth rate V. 2, 100A, 100B, 100C, 100D, and 100E conceptually indicate the sizes and densities of various defects between the center and the end (edge) of the silicon wafer 100 obtained from the silicon crystal 10. The center and edge of the silicon wafer 100 correspond to the crystal center and the crystal edge (crystal periphery) of the silicon crystal 10.
[0010]
i) When the growth rate V is high, as shown by 100A and 100B in FIG. 2, the vacancy-type point defects are excessive in the silicon crystal 10, and only void defects are generated.
[0011]
ii) When the growth rate V is reduced, a ring-like OSF (R-OSF) is generated near the outer periphery of the silicon crystal 10, and a void defect is present inside the R-OSF portion.
[0012]
iii) When the growth rate V is further reduced, the radius of the ring-shaped OSF (R-OSF) decreases, a region in which no defect exists outside the ring-shaped OSF portion, and a dislocation loop cluster is generated outside the region. -A structure in which void defects exist inside the OSF part.
[0013]
iV) When the growth rate V is further reduced, as shown in 100E, a dislocation loop raster exists in the entire silicon crystal 10.
[0014]
It is considered that the phenomenon described above occurs because the silicon crystal 10 changes from the state of excess vacancy type point defects to the state of excess interstitial silicon type point defects as the growth rate V decreases. It is understood that the change starts from the outer periphery of the silicon crystal 10.
[0015]
Among the above three types of defects, the void defect a) in particular is a cause of element isolation failure and the like in a miniaturized device, and thus reduction thereof is particularly required.
[0016]
Void defects are caused by agglomeration of atomic vacancies (point defects) taken from a silicon melt during crystal growth by reaching critical supersaturation during crystal cooling. It is called particle defect), COP (crystal-originated particle), FPD (flow pattern defect), LSTD (laser scattering tomography defect), or the like.
[0017]
At present, as shown in FIGS. 2A and 2B, the silicon crystal 10 is formed in a region where void defects are present on the entire surface of the silicon wafer. In the silicon wafer 100 obtained from the silicon crystal 10, there is COP in which void defects are manifested on the surface. There is a demand for defect-free integrity of the surface layer of a silicon wafer. In particular, at the present time when miniaturization has progressed to a device line width close to the COP size, it is necessary to reduce COP.
[0018]
If the silicon crystal 10 having no defect is manufactured, a silicon wafer having no COP can be obtained. However, the production of silicon crystals for that purpose has the disadvantages that very precise pulling control is required and the productivity is also inferior.
[0019]
Here, there is a method of “growing a defect-free layer on the wafer surface by epitaxial growth” as one method for obtaining a silicon wafer that does not contain a glow-in defect such as COP in the vicinity of the surface layer where the device circuit is formed. However, this method has a problem that the manufacturing cost is higher than that of a polished wafer because an epitaxial growth layer forming step is included. Similarly, the method of annealing in a hydrogen or argon atmosphere can also make the vicinity of the wafer surface layer a defect-free layer that does not contain COP or the like. However, since an annealing process is included, the cost is similarly high compared to a polished wafer. Invite.
[0020]
In order to guarantee the quality of the device, it is not always necessary to completely remove the COP. If the size can be reduced below a certain level, the yield of device defects can be improved. That is, if the COP size is made smaller than the device line width, there is no problem in element isolation, and the influence on device defects is small. Specifically, a COP of about 0.10 μm or more measured by a particle counter is regarded as a problem and needs to be reduced, but it has been found that the influence is small for a COP having a size lower than that.
[0021]
As described above, the COP is not completely eliminated in consideration of the manufacturing cost and the price advantage, but the polished wafer in which the COP is miniaturized and the COP having a larger size is reduced than usual although the COP exists. It is becoming necessary to manufacture.
[0022]
Here, the formation mechanism of the void defect will be described with reference to FIG. FIG. 1A conceptually shows defects in the silicon crystal 10 that is pulled and grown from the silicon melt 5, and FIG. 1B corresponds to the temperature in the axial direction of the silicon crystal 10 corresponding to FIG. And the relationship between the point defect density and the void defect density. In FIG. 1B, Cv is the vacancy concentration in the silicon crystal 10, and Cv, eq is the thermal equilibrium concentration of the vacancies in the silicon crystal 10. When vacancies are excessively taken in, the supersaturation degree (Cv / Cv, eq) of the vacancies increases with a decrease in temperature, and void defects are formed when the critical value is reached.
[0023]
As shown in FIG. 1, in the vicinity of the melting point of silicon (about 1350 ° C.) (˜about 1150 ° C.), the void supersaturation has not reached the critical value, so no void defect is formed as a point defect. When the hole supersaturation reaches a critical value, void defects begin to occur and the void defect density gradually increases and reaches a certain density in the void defect generation temperature zone (about 1150 ° C. to about 1080 ° C.).
[0024]
Thus, the generation and growth of void defects are strongly influenced by the thermal history experienced by the silicon crystal during crystal growth. In particular, the axial temperature gradient G1 near the melting point, the axial temperature gradient G2 in the void defect generation temperature zone, and the growth rate V of the silicon crystal 10 are important parameters for controlling the density and size of the void defects.
[0025]
It is known that the size and density of void defects are affected by growth conditions V / G1 and V · G2 representing the thermal history during crystal pulling. Of these, the growth condition V / G1 affects the amount of vacancies forming void defects, and determines the concentration of vacancies initially introduced. The growth condition V · G2 is the crystal cooling rate in the void defect generation temperature zone, and affects the growth of void defects.
[0026]
The relationship between the growth condition V / G1 (V · G2), the point defect (vacancy) concentration, and the defect type is represented by the conceptual diagram shown in FIG.
[0027]
At present, as shown by 100A and 100B in FIG. 2, the cooling rate V · G2 in the void defect generation temperature zone is a high V / G1 region in which the OSF region escapes to the outer periphery of the crystal and the vacancy concentration is relatively stable. Is controlled to control the density and size of void defects (normal conditions).
[0028]
As shown in FIG. 3, the relationship between the density and size of void defects is generally inversely proportional, and the defect size becomes smaller as the cooling rate V · G 2 increases, and the defect density depends on the cooling rate V · G 2. It gets bigger as it gets smaller. In the high V / G1 region, the total vacancy concentration constituting the void defect is almost constant, and V / G1 hardly affects the defect density and size as shown in 100A and 100B only by the cooling rate V · G2. Is determined.
[0029]
However, in the region close to the critical value where V / G1 changes from the void defect region to the OSF region, as shown in 100C and 100D, as V / G1 approaches the critical value and the total vacancy concentration decreases, the V / G1 decreases. The effect of reducing the defect size by the influence appears (low V / G1 effect). That is, in the region where V / G1 is close to the critical value, the size of the void defect becomes smaller as V / G1 is smaller and V · G2 is larger. This mechanism will be described.
[0030]
A void defect is formed after the supersaturation degree of a void | hole exceeds a critical value. When the total vacancy concentration is low, the temperature when the supersaturation degree C′v / Cv, eq of the vacancy exceeds a critical value (critical supersaturation degree) becomes low as shown by a one-dot chain line in FIG. For this reason, the formation temperature of void defects is lowered, the growth rate of void defects (vacancy aggregation rate) is lowered, and the void size is not increased. In addition, the elimination of void supersaturation is delayed, and excess voids are absorbed. As a result, void nuclei are newly generated. As a result, the void defect density increases, but the void defect size does not increase.
[0031]
Further, considering the performance guarantee of the silicon wafer, it is necessary to uniformly create a state in which the void defect size is small in the radial direction (from the center to the end) of the silicon wafer 100. Since the silicon crystal 10 is removed from the surface, the radial distribution of the axial temperature gradient G1 near the melting point is small at the crystal center and becomes larger toward the outer periphery of the silicon crystal. For this reason, if the distribution difference of G1 is large, V / G1 is relatively low in the peripheral portion of the silicon wafer 100 only by reducing the growth rate V in order to achieve low V / G1, and R in the peripheral portion is R. -OSF may occur or the defect size and density may partially increase because the void defect size and void defect density become non-uniform in the wafer surface.
[0032]
Next, the prior art disclosed in the patent document will be described.
[0033]
(Prior art 1)
Patent Document 1 (Japanese Patent Laid-Open No. 2001-278692) describes the size by controlling the growth conditions V / G1, V · G2 (however, defined by the void defect generation temperature zone transit time) at the center of the silicon crystal. An invention is described that reduces the large COP. However, in Patent Document 1, the temperature gradient G1 is defined at the crystal center, and the radial distribution of the temperature gradient G1 is not considered at all. For this reason, as described above, there is a possibility that R-OSF is generated in the peripheral portion of the wafer, or the defect size and density are partially increased in the wafer surface. Patent Document 1 describes a technique in which a temperature cylinder G1 is increased by providing a cooling cylinder for rapidly cooling a growing silicon crystal.
[0034]
(Prior art 2)
Patent Document 2 (Japanese Patent Laid-Open No. 2000-313695) describes an invention in which the radial distribution (ΔV / G1) of the growth condition V / G1 is set to 10% or less to reduce COP. However, as will be described later, the growth rate V cannot be increased to a certain level or more simply by controlling the parameter of the radial distribution (ΔV / G1) of the growth condition V / G1. There is a risk that productivity may be impaired due to a limit in pulling speed.
[0035]
(Prior art 3)
In Patent Document 3 (Japanese Patent Laid-Open No. 2001-261495) relating to the present applicant, the critical value and the radial distribution of V / G1 are determined depending on the shape of the solid-liquid interface that is the boundary between the silicon crystal 10 and the silicon melt. It is described to change.
[0036]
The prior arts 1 and 2 described above do not consider the shape of the solid-liquid interface at all. That is, in the prior arts 1 and 2, the defect size and density cannot be controlled accurately unless changes in the radial distribution of the critical value and V / G1 are captured in consideration of the shape of the solid-liquid interface.
[0037]
The present invention has been made in view of such circumstances, and it is a solution to improve the yield of device defects by enabling the size and density of void defects to be accurately controlled below a certain level without impairing productivity. To do.
[0038]
[Means, actions and effects for solving the problems]
The first invention is
In a silicon wafer manufacturing method in which a silicon crystal is pulled and grown from a silicon melt, and a silicon wafer is obtained from the pulled and grown silicon crystal,
With the axial temperature gradient G1 in the vicinity of the melting point of the silicon crystal increased, the solid-liquid interface that is the boundary between the melt and the silicon crystal during pulling the silicon crystal is made convex upward with respect to the melt surface. The growth condition V / G1 (V: growth rate, G1: axial temperature gradient in the vicinity of the melting point of the silicon crystal) is reduced to near the critical value,
Pulling up and growing silicon crystals
It is characterized by.
[0039]
The second invention is the first invention,
By cooling the silicon crystal with a cooler, the solid-liquid interface is raised with respect to the melt surface when the growth rate V is in the range of 97% to 75% of Vmax (the limit growth rate at which the silicon crystal can grow without deformation). With the convex shape, the growth condition V / G1 is lowered to near the critical value,
Pulling and growing silicon crystals that do not have OSF (oxidation-induced stacking fault) regions on the entire surface of the silicon wafer
It is characterized by.
[0040]
The third invention is the first invention,
By cooling the silicon crystal with a cooler, the growth condition V / G1 is lowered to near the critical value with the axial temperature gradient G1 near the melting point of the silicon crystal being increased.
It is characterized by.
[0041]
A fourth invention is the first invention,
By applying a magnetic field to the silicon melt, the solid-liquid interface is made convex upward with respect to the melt surface.
It is characterized by.
[0042]
A fifth invention is the first invention,
The silicon crystal is cooled by a cooler, and the rotation speed of the silicon crystal or the rotation speed of the crucible containing the silicon melt is adjusted to make the solid-liquid interface convex upward with respect to the melt surface.
It is characterized by.
[0043]
The sixth invention
In a silicon wafer manufacturing method in which a silicon crystal is pulled and grown from a silicon melt, and a silicon wafer is obtained from the pulled and grown silicon crystal,
By cooling the silicon crystal with a cooler, the growth condition V / G1 is lowered to near the critical value with the axial temperature gradient G1 in the vicinity of the melting point of the silicon crystal being increased.
Pulling up and growing a silicon crystal that does not have an OSF (oxidation-induced stacking fault) region in at least the region from the center of the silicon wafer to the inner 10 mm from the outer periphery.
It is characterized by.
[0044]
A seventh invention is the sixth invention,
The oxygen concentration in the silicon crystal is 12.5 × 10 ¹⁷ atoms / cm ³ (1979 ASTM) to be controlled below
It is characterized by.
[0045]
In an eighth aspect based on the sixth aspect,
In order to prevent OSF nuclei from appearing in the OSF in the silicon wafer, the silicon wafer is subjected to heat treatment at 1000 ° C or higher.
It is characterized by.
[0046]
A ninth invention is the sixth invention,
The silicon wafer is heat-treated at 1000 ° C or higher in a non-oxidizing atmosphere so that OSF nuclei do not appear in the OSF and disappear on the silicon wafer surface layer.
It is characterized by.
[0047]
The tenth invention is
In a silicon wafer manufacturing apparatus in which a silicon crystal is pulled and grown by a pulling mechanism from a silicon melt and a silicon wafer is obtained from the silicon crystal that has been pulled and grown.
A cooler for cooling the silicon crystal is provided above the silicon melt,
By adjusting the silicon crystal pulling speed by the pulling mechanism and the cooling amount of the cooler,
With the axial temperature gradient G1 in the vicinity of the melting point of the silicon crystal increased, the solid-liquid interface that is the boundary between the melt and the silicon crystal during pulling the silicon crystal is made convex upward with respect to the melt surface. The growth condition V / G1 (V: growth rate, G1: axial temperature gradient in the vicinity of the melting point of the silicon crystal) is reduced to near the critical value,
Pulling up and growing silicon crystals
It is characterized by.
[0048]
In an eleventh aspect based on the tenth aspect,
By cooling the silicon crystal with a cooler, the solid-liquid interface is raised with respect to the melt surface when the growth rate V is in the range of 97% to 75% of Vmax (the limit growth rate at which the silicon crystal can grow without deformation). With the convex shape, the growth condition V / G1 is lowered to near the critical value,
Pulling and growing silicon crystals that do not have OSF (oxidation-induced stacking fault) regions on the entire surface of the silicon wafer
It is characterized by.
[0049]
The twelfth invention
In a silicon wafer manufacturing apparatus in which a silicon crystal is pulled and grown from a silicon melt and a silicon wafer is obtained from the silicon crystal that has been pulled and grown,
A cooler for cooling the silicon crystal is provided above the silicon melt,
By adjusting the silicon crystal pulling speed by the pulling mechanism and the cooling amount of the cooler,
With the axial temperature gradient G1 in the vicinity of the melting point of the silicon crystal being increased, the growth condition V / G1 is reduced to near the critical value,
Pulling up and growing a silicon crystal that does not have an OSF (oxidation-induced stacking fault) region in at least the region from the center of the silicon wafer to the inner 10 mm from the outer periphery.
It is characterized by.
[0050]
In a thirteenth aspect based on the tenth aspect or the twelfth aspect,
The cooler is disposed to surround the silicon crystal at a distance of 30 mm to 500 mm from the silicon melt.
It is characterized by.
[0051]
In a fourteenth aspect based on the tenth aspect or the twelfth aspect,
A heat shielding plate is provided above the silicon melt, and a gap between the lower end of the heat shielding plate and the surface of the silicon melt is set to 20 mm to 100 mm.
It is characterized by.
[0052]
The fifteenth invention
A silicon wafer obtained by pulling and growing from a silicon melt,
There is no OSF (oxidation induced stacking fault) region on the entire surface of the silicon wafer, and the average void defect density on the entire surface of the silicon wafer is 5 × 10. ⁶ / cm ³ The following is a silicon wafer having an average void defect size of 100 nm or less on the entire surface of the silicon wafer.
[0053]
The sixteenth invention
A silicon wafer obtained by pulling and growing from a silicon melt,
There is no OSF (oxidation-induced stacking fault) region in the silicon wafer surface from at least the center of the surface to 10 mm inside the outer periphery, and at least 10 mm from the center to the inner periphery of the silicon wafer surface. Up to the area
The average void defect density at 5 × 10 ⁶ / cm ³ A silicon wafer having an average void defect size of 100 nm or less.
[0054]
In the first invention, the second invention, the third invention, the fourth invention, the fifth invention, the tenth invention, the eleventh invention, the thirteenth invention, and the fourteenth invention, a silicon wafer in which no OSF region exists in the wafer surface is manufactured. Is done.
[0055]
In the present invention, the pulling speed V of the silicon crystal 10 by the pulling mechanism 4 is adjusted, and the cooling amount of the cooler 30 is adjusted to increase the axial temperature gradient G1 in the vicinity of the melting point of the silicon crystal 10 so that the growth speed V In the state where the solid-liquid interface is convex upward with respect to the melt surface in the range of 97% to 75% of Vmax (the limit growth rate at which the silicon crystal can grow without deformation), the growth condition V / G1 Is lowered to near the critical value, and the silicon crystal 10 is pulled and grown. In addition to adjusting the cooling amount of the cooler 30, the silicon crystal rotation speed S / R and the crucible rotation speed C / R are adjusted as necessary, so that the solid-liquid interface has a convex shape with respect to the melt surface. Is done. Further, by applying a magnetic field to the silicon melt instead of adjusting the cooling amount of the cooler 30, the solid-liquid interface is made convex upward with respect to the melt surface.
[0056]
By cooling the silicon crystal 10 with the cooler 30, G1 increases, and the speed V when V / G1 is lowered to near the critical value can be maintained at 75% or more of Vmax (FIG. 10). FIG. 10 shows the relationship between the growth rate of the silicon crystal 10 having a diameter of 200 mm and the solid-liquid interface shape. In FIG. 10, Vmax corresponds to 1.48 mm / min, and a value of V that is 75% of Vmax corresponds to 1.11 mm / min. However, in order to obtain the effect of reducing the void defect size, it is desirable that the pulling speed V is a low speed near the lower limit speed (75% of Vmax) that does not generate OSF (FIG. 12). Even though the speed is low, the speed is sufficiently high compared with the lower limit pulling speed (0.76 mm: FIG. 8) that does not generate OSF under normal pulling conditions without the cooler 30, and productivity is not inferior.
[0057]
According to the present invention, since the growth condition V / G1 is lowered to the vicinity of the critical value in a state where the solid-liquid interface is convex upward with respect to the melt surface, as in FIG. The distribution of V / G1 in the wafer surface in the radial direction becomes uniform to a certain level or more, so that OSF is not generated in the wafer surface, and the size and density of void defects are reduced by the low V / G1 effect. can do. Moreover, since the speed V is maintained higher than the normal condition, V · G2 increases, and the defect size can be further reduced by the high V · G2 effect (see FIG. 3). Therefore, a silicon wafer indicated by 100D in FIG. 2 is obtained, and the size and density of void defects over the entire surface of the silicon wafer 100D can be reduced to the level indicated by the oblique lines in FIG. In FIG. 2, the width of the silicon wafer 100D in the drawing is narrower than the widths of the silicon wafers 100A and 100B obtained under normal conditions. The V / G1 is made uniform in the wafer surface, and the void defect size and density are It is shown that the wafer is uniformly reduced in the wafer plane.
[0058]
Moreover, in the present invention, since the solid-liquid interface is convex upward using the cooler 30, the apparatus cost can be reduced compared to the case where the same thing is achieved by applying a horizontal magnetic field.
[0059]
In the sixth invention, the seventh invention, the eighth invention, the ninth invention, the twelfth invention, the thirteenth invention, and the fourteenth invention, the OSF is at least in the region from the center of the silicon wafer surface to the inner 10 mm from the outer periphery. A silicon wafer that does not exist is manufactured.
[0060]
In the present invention, the growth speed V of the silicon crystal 10 by the pulling mechanism 4 is adjusted and the cooling amount of the cooler 30 is adjusted to increase the axial temperature gradient G1 near the melting point of the silicon crystal. The silicon crystal 10 is pulled and grown by reducing the condition V / G1 to near the critical value.
[0061]
According to the present invention, by cooling the silicon crystal 10 with the cooler 30, G1 increases, and the velocity V when V / G1 is lowered to near the critical value can be maintained high. However, since the OSF region is allowed to be generated in the outer peripheral portion of the silicon crystal 10, the solid-liquid interface has a slightly convex shape as shown in FIG. 10, and the pulling speed V is as shown in FIG. It is about 70% of Vmax, which is lower than the case where the presence of the OSF region is not allowed. For this reason, the effect of reducing the void defect size is further enhanced by further lowering the pulling speed V. Although it is low speed, it is at the same level as the lower limit pulling speed (0.76 mm: FIG. 8) that does not generate OSF under normal pulling conditions, and productivity is not inferior.
[0062]
According to the present invention, since V / G1 is lowered to near the critical value, a low V / G1 effect can be obtained, and the size and density of void defects can be reduced. Moreover, since the speed V is kept high at the same level as the normal condition, V · G2 increases and the defect size can be further reduced by the high V · G2 effect (see FIG. 3). For this reason, a silicon wafer indicated by 100C in FIG. 2 is obtained, and the size and density of void defects in the area from at least the center of the silicon wafer 100C to the inner side 10 mm from the outer periphery are indicated by the hatched levels in FIG. Can be made smaller.
[0063]
In FIG. 2, the width of the silicon wafer 100C in the drawing is narrower than the widths of the silicon wafers 100A and 100B obtained under normal conditions. The V / G1 is made uniform in the wafer surface, and the void defect size and density are It is shown that the wafer is uniformly reduced in the wafer plane.
[0064]
The fifteenth invention is manufactured by the manufacturing method and the manufacturing apparatus of the first invention, the second invention, the third invention, the fourth invention, the fifth invention, the tenth invention, the eleventh invention, the thirteenth invention, and the fourteenth invention. It is a silicon wafer. The silicon wafer 100D of the present invention is manufactured so that there is no OSF region on the entire surface of the silicon wafer from the center to the end. 5 indicate the range of the average void defect density and the average void defect size on the entire surface of the silicon wafer 100D of the present invention. The silicon wafer 100D of the present invention has an average void defect density of 5 × 10 6 over the entire wafer surface. ⁶ / cm ³ The average void defect size is 100 nm or less.
[0065]
The sixteenth invention is a silicon wafer manufactured by the manufacturing method and manufacturing apparatus of the sixth invention, seventh invention, eighth invention, ninth invention, twelfth invention, thirteenth invention, and fourteenth invention. The silicon wafer 100C of the present invention is manufactured so that there is no OSF region in the region from at least the center of the silicon wafer to the inner 10 mm from the outer periphery. 5 indicates the range of the average void defect density and the average void defect size in the inner region of the R-OSF of the silicon wafer 100C of the present invention. The silicon wafer 100C of the present invention has an average void defect density in the inner region of the R-OSF of 5 × 10 ⁶ / cm ³ The average void defect size is 100 nm or less.
[0066]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0067]
FIG. 15 is a side view showing an example of the configuration of the silicon crystal manufacturing apparatus used in the embodiment.
[0068]
As shown in FIG. 15, the single crystal pulling apparatus 1 of the embodiment includes a CZ furnace (chamber) 2 as a single crystal pulling container.
[0069]
In the CZ furnace 2, there is provided a quartz crucible 3 for melting a polycrystalline silicon raw material and storing it as a melt 5. The quartz crucible 3 is covered with a graphite crucible 11 on the outside. A main heater 9 that heats and melts the polycrystalline silicon material in the quartz crucible 3 is provided outside and on the side of the quartz crucible 3. An auxiliary heater (bottom heater) 19 is provided at the bottom of the quartz crucible 3 to assist in heating the bottom of the quartz crucible 3 to prevent the melt 5 at the bottom of the quartz crucible 3 from solidifying. The outputs (power; kW) of the main heater 9 and the auxiliary heater 19 are controlled independently, and the heating amount for the melt 5 is adjusted independently. For example, the temperature of the melt 5 is detected, and the outputs of the main heater 9 and the auxiliary heater 19 are controlled so that the detected temperature is a feedback amount and the temperature of the melt 5 becomes the target temperature.
[0070]
A heat insulating cylinder 13 is provided between the main heater 9 and the inner wall of the CZ furnace 2.
[0071]
A pulling mechanism 4 is provided above the quartz crucible 3. The pulling mechanism 4 includes a pulling shaft 4a and a seed chuck 4c at the tip of the pulling shaft 4a. The seed crystal 14 is gripped by the seed chuck 4c.
[0072]
In the quartz crucible 3, polycrystalline silicon (Si) is heated and melted. When the temperature of the melt 5 is stabilized, the pulling mechanism 4 operates to pull up the silicon crystal 10 (silicon single crystal) from the melt 5. That is, the pulling shaft 4 a is lowered and the seed crystal 14 held by the seed chuck 4 c at the tip of the pulling shaft 4 a is immersed in the melt 5. After the seed crystal 14 is adjusted to the melt 5, the pulling shaft 4a moves up. As the seed crystal 14 held by the seed chuck 4c rises, the silicon crystal 10 grows. At the time of pulling up, the quartz crucible 3 is rotated at the rotation speed C / R by the rotating shaft 110. The pulling shaft 4a of the pulling mechanism 4 rotates at the rotation speed S / R in the opposite direction or the same direction as the rotation shaft 110.
[0073]
The rotating shaft 110 can be driven in the vertical direction, and the quartz crucible 3 can be moved up and down to move to an arbitrary position.
[0074]
By shutting off the outside air from the CZ furnace 2, the inside of the furnace 2 is maintained in a vacuum (for example, about 20 Torr). That is, argon gas 7 as an inert gas is supplied to the CZ furnace 2 and is exhausted from the exhaust port of the CZ furnace 2 by a pump. Thereby, the inside of the furnace 2 is depressurized to a predetermined pressure.
[0075]
Various evaporants are generated in the CZ furnace 2 during the single crystal pulling process (one batch). Therefore, the argon gas 7 is supplied to the CZ furnace 2 and exhausted together with the evaporated substance outside the CZ furnace 2 to remove the evaporated substance from the CZ furnace 2 and clean it. The supply flow rate of the argon gas 7 is set for each process in one batch.
[0076]
As the silicon crystal 10 is pulled up, the melt 5 decreases. As the melt 5 decreases, the contact area between the melt 5 and the quartz crucible 3 changes, and the amount of dissolved oxygen from the quartz crucible 3 changes. This change affects the oxygen concentration distribution in the silicon crystal 10 to be pulled up. Therefore, in order to prevent this, the polycrystalline silicon raw material or the single crystal silicon raw material may be additionally supplied into the quartz crucible 3 in which the melt 5 is reduced after or during the pulling.
[0077]
Above the quartz crucible 3 and around the silicon crystal 10, a heat shielding plate 8 (gas rectifying cylinder) having a substantially inverted truncated cone shape is provided. The heat shielding plate 8 is supported by the heat insulating cylinder 13. The heat shielding plate 8 guides an argon gas 7 as a carrier gas supplied from above into the CZ furnace 2 to the center of the melt surface 5a, and further passes through the melt surface 5a so that the peripheral portion of the melt surface 5a. Lead to. The argon gas 7 is discharged together with the gas evaporated from the melt 5 from an exhaust port provided in the lower part of the CZ furnace 2. For this reason, the gas flow rate on the liquid surface can be stabilized, and the oxygen evaporated from the melt 5 can be maintained in a stable state.
[0078]
The heat shielding plate 8 insulates and shields the seed crystal 14 and the silicon crystal 10 grown by the seed crystal 14 from radiant heat generated in high-temperature portions such as the quartz crucible 3, the melt 5, and the main heater 9. Further, the heat shielding plate 8 prevents impurities (for example, silicon oxide) generated in the furnace from adhering to the silicon crystal 10 and hindering single crystal growth. The size of the gap 20 between the lower end of the heat shielding plate 8 and the melt surface 5a can be adjusted by raising and lowering the rotating shaft 110 and changing the vertical position of the quartz crucible 3. Further, the gap 20 may be adjusted by moving the heat shielding plate 8 in the vertical direction by the lifting device.
[0079]
A cooler 30 is provided above the silicon melt 5 at a distance of 30 mm to 500 mm from the silicon melt 5 so as to cool the silicon crystal 10 so as to surround the silicon crystal 10.
[0080]
By adjusting the gap 20, the pulling speed V of the pulling shaft 4a, and the cooling amount of the cooler 30, V / G1 (V: growth rate, G1: axial temperature gradient near the melting point of the silicon crystal 10) as will be described later. , V · G2 (V: growth rate, G2: axial temperature gradient in the void defect generation temperature zone of the silicon crystal), growth rate V, axial temperature gradient G1 near the melting point of the silicon crystal 10, and Each parameter of the radial distribution of the axial temperature gradient G1 in the vicinity of the melting point is controlled.
[0081]
During the pulling, the oxygen concentration (atoms / cm) in the silicon crystal 10 is adjusted by adjusting the crucible rotation speed C / R, the pulling shaft rotation speed S / R, the argon gas flow rate, the furnace pressure, and the like. ³ ) Is controlled.
[0082]
The ingot of the silicon crystal 10 manufactured by the apparatus of FIG. 15 is cut by a cutting device, and the silicon wafer 100 is collected.
[0083]
(First embodiment)
100D shown in FIG. 2 represents the silicon wafer of the first embodiment. The silicon wafer 100D of the embodiment is manufactured so that the OSF region does not exist on the entire surface of the silicon wafer from the center to the end.
[0084]
5 indicates the range of the average void defect density and the average void defect size in the entire surface of the silicon wafer 100D of the first embodiment. The silicon wafer 100D of the first embodiment has an average void defect density of 5 × 10 6 over the entire wafer surface. ⁶ / cm ³ The average void defect size is 100 nm or less.
[0085]
The silicon crystal 10 of the first embodiment has a diameter of 200 mm and is grown at a speed V of 1.11 to 1.45 mm / min.
[0086]
As described above, according to the first embodiment, the average void defect density on the entire surface of the silicon wafer is 5 × 10 5. ⁶ / cm ³ In the following, since the average void defect size is 100 nm or less, it is possible to eliminate device characteristic deterioration due to void defects. In addition, since there is no OSF region on the entire surface of the silicon wafer, it is possible to eliminate device characteristic deterioration caused by OSF. Moreover, since the silicon crystal 10 is pulled and grown at a high speed of 1.11 to 1.45 mm / min, productivity can be improved.
[0087]
Next, the conditions for manufacturing the silicon wafer 100D are examined.
[0088]
As described above, at present, as shown by 100A and 100B in FIG. 2, in the V / G1 region where the OSF region is released to the outer periphery of the crystal and the vacancy concentration is relatively stable, in the void defect generation temperature range. The density and size of void defects are controlled by changing the cooling rate V · G2.
[0089]
As shown in FIG. 3, the relationship between the density and size of void defects is generally inversely proportional, and the defect size decreases as the cooling rate V · G 2 increases (high V · G 2 effect). Increases as the cooling rate V · G2 decreases. In the region of high V / G1, the total vacancy concentration constituting the void defect is almost constant, and V / G1 hardly affects the defect as shown by 100A and 100B in FIG. Density and size are determined.
[0090]
FIG. 6 shows the relationship between the cooling rate at 1100 ° C. and the defect size when V / G1 is more than twice the critical value. Thus, at high V / G1, it is possible to reduce the defect size by simply changing V · G2 representing the cooling rate (high V · G2 effect).
However, in the region close to the critical value where V / G1 changes from the void defect region to the OSF region, as shown in 100C and 100D, as V / G1 approaches the critical value and the total vacancy concentration decreases, the V / G1 decreases. The effect of reducing the defect size by the influence appears (low V / G1 effect). In the region where V / G1 is close to the critical value, the size of the void defect decreases as V / G1 decreases and V · G2 increases.
[0091]
Therefore, in order to reduce the defect size, a method of mainly increasing V · G2 and a method of mainly decreasing V / G1 can be considered. However, since only V / G2 cannot be increased and V / G1 can be decreased only by changing only the growth rate V, a method of increasing G1 as described later is required.
[0092]
FIG. 7 is a view showing the distribution of V / G1 between the center of the silicon wafer and the outer periphery (end) of the silicon wafer. This will be described below with reference to FIG.
[0093]
An effective method for increasing V · G2 is to increase G2 by the cooler 30 and increase the critical speed Vmax of the growth speed V that allows the silicon crystal 10 to grow without deformation, and pull it up at high speed. (Method {circle around (1)}).
[0094]
This method {circle around (1)} has the advantage that the pulling speed is fast and the productivity is improved.
[0095]
However, as indicated by the broken line in FIG. 7A, the method (1) has a V / G1 much larger than the critical value and the low V / G1 effect cannot be obtained. There is a limit to the conversion.
[0096]
In the method of reducing V / G1, the low V / G1 effect cannot be realized unless V / G1 is lowered to a critical value near the defect type where the defect type changes from void defect to OSF. This corresponds to moving the silicon wafer end of the silicon wafer 100A to near the critical value in FIG.
[0097]
Under normal pulling conditions, as shown by the solid line in FIG. 7A, even if V / G1 at the outer periphery of the silicon wafer is lowered to a critical value, the difference from V / G1 at the center of the silicon wafer is large. At the center of the silicon wafer, the V / G1 is high and the low V / G1 effect cannot be obtained. For this reason, there is a limit to reducing the void defect size and reducing the density at the center of the silicon wafer.
[0098]
In order to solve this problem, the following method can be considered.
[0099]
・ Method ▲ 2 ▼
As shown by a solid line in FIG. 7B, the OSF region and the defect-free region are allowed to enter the outer peripheral portion of the silicon wafer, and the V / G1 at the center portion of the silicon wafer is lowered to reduce the low V / G1 effect. obtain.
[0100]
・ Method ▲ 3 ▼
As shown by the solid line in FIG. 7C, V / G1 in the silicon wafer surface is made uniform to a certain level or more so that the difference in V / G1 between the center and the outer periphery of the silicon wafer becomes small. V / G1 is lowered over the entire wafer surface to obtain a low V / G1 effect. This method {circle around (3)} is a method corresponding to the prior art 2 described above.
[0101]
According to the above method (2), the number of void defects is reduced by narrowing the void defect existing area in the wafer surface. However, this silicon crystal 10 has a problem that an OSF region exists. By keeping the oxygen concentration in the silicon crystal 10 low, OSF nuclei can be made apparent in the OSF in the silicon wafer 100 after the heat treatment, but there is a possibility that the gettering ability is insufficient due to insufficient oxygen precipitation. Further, the productivity is inferior because the growth rate V is reduced as compared with the case of pulling up the normal silicon crystal 10.
[0102]
According to the method (3), the void defect size is reduced on the entire wafer surface. However, the condition for making V / G1 in the wafer surface uniform to a certain level or more makes the pulling speed V slower than in the case of manufacturing under normal conditions. According to the experiments by the present inventors, when the silicon crystal 100 having a diameter of 200 mm is pulled and grown, the pulling speed V cannot be made higher than 0.8 mm / min. Thus, according to method (3), the productivity may be inferior.
[0103]
Next, prior art 1 will be examined.
[0104]
FIG. 4 shows the range of the growth conditions V / G1, V · G2 at the center of the silicon crystal 10 of the prior art 1 by hatching. In the prior art 1, V · G2 is defined by the void defect occurrence temperature zone passage time L / V (L: temperature region length) which is the reciprocal thereof.
[0105]
FIG. 4 plots the transit time L / V in the void defect formation temperature zone against V / G1, and the particle density of 0.10 μm size or more is 1 / cm. ² Threshold line y = 0.28 / (x−0.225) ² (X: horizontal axis, y: vertical axis). The area indicated by the oblique lines with the threshold line as the boundary has no generation of R-OSF, and the particle density of 0.10 μm size or more is 1 / cm. ² It becomes as follows.
[0106]
Here, according to Prior Art 3, it is described that the radial distribution of the critical value, V / G1, changes depending on the shape of the solid-liquid interface that is the boundary between the silicon crystal 10 and the silicon melt.
[0107]
The hatched area shown in FIG. 4 is an area where the defect size decreases and decreases in density at a critical value under a certain condition. Depending on the shape of the solid-liquid interface, the hatched area shown in FIG. Densification is not always true.
[0108]
Further, V / G1 of the prior art 1 is a value at the center of the crystal, and no consideration is given to the radial distribution of V / G1. For this reason, if the shape of the solid-liquid interface changes, even if the V / G1 value is the same at the center of the crystal, the V / G1 radial distribution will be different. It may become the OSF area. Also, if the solid-liquid interface shape is different, there may be a difference in the void defect size at the crystal edge.
[0109]
As described above, the hatched area in FIG. 4 shown in the prior art 1 is always a void defect area on the entire wafer surface, and it cannot be said that the defect size is always reduced and the density is not lowered.
[0110]
That is, even if the prior art 1 is applied, although the void defect size and density are reduced by reducing the crystal central portion to low V / G1 according to the conditions shown in FIG. 4, as in FIG. 7B. Thus, it is considered that the V / G1 at the crystal edge is lower than the critical value and the R-OSF is generated by lowering the crystal center at V / G1.
[0111]
FIG. 8 shows the experimental results of examining the change in the shape of the solid-liquid interface under normal pulling conditions (no magnetic field applied, no cooler installed). The horizontal axis of FIG. 8 is the distance (radial direction distance) from the center of the silicon crystal 10, and the vertical axis is the height X of each part of the solid-liquid interface. The solid-liquid interface height X and the solid-liquid interface center height (projection amount) Xcen are defined in FIG. When the solid-liquid interface center height Xcen is a positive value, the solid-liquid interface is convex upward, and when the solid-liquid interface center height Xcen is a negative value, the solid-liquid interface is convex downward. FIG. 8 shows the solid-liquid interface shape at each growth rate when the growth rate V is changed in the range of 0.53 mm / min to 1.14 mm / min, the growth rate at which OSF is generated, and the solid-liquid interface shape at that time. Is shown.
[0112]
As shown in FIG. 8, under a normal condition, the solid-liquid interface gradually changes from a convex shape upward to a convex shape downward as the pulling speed V is decreased in order to achieve low V / G1. When the pulling speed V is lowered to the critical value at which R-OSF is generated, the solid-liquid interface shape becomes convex downward. The pulling speed V at this time was 0.76 mm / min.
[0113]
FIG. 20 shows the experimental results of examining changes in the shape of the solid-liquid interface when a silicon crystal having a diameter different from that in FIG. 8 is pulled and grown under normal pulling conditions (no magnetic field applied, no cooler installed). The horizontal and vertical axes in FIG. 20 correspond to the horizontal and vertical axes in FIG. FIG. 20 shows the solid-liquid interface shape at each growth rate when the growth rate V is changed to 0.35 mm / min, 0.41 mm / min, and 0.48 mm / min, respectively. It can be seen that the solid-liquid interface shape is convex downward in this growth rate region.
[0114]
Here, when the solid-liquid interface has an upwardly convex shape, the inventors have a uniform G1 distribution over a certain level, and the radial distribution of V / G1 is uniform over a certain level. However, on the contrary, when the solid-liquid interface has a downwardly convex shape, the G1 distribution varies within the wafer surface, and it has been found that the radial distribution of V / G1 is not uniform.
[0115]
Under normal conditions, as shown in FIG. 8, when V / G1 is lowered to a critical value, the solid-liquid interface becomes convex downward, so that there is a difference in G1 distribution in the wafer surface, and R-OSF is at the wafer edge. This is likely to occur. That is, even if the crystal center portion is lowered to V / G1 in the same manner as in FIG. 7B, V / G1 at the crystal edge portion falls below the critical value and R-OSF is generated.
[0116]
In order to avoid this, it is conceivable to apply a horizontal magnetic field of 2500 G or more to the silicon melt 5 as a method of making the solid-liquid interface convex upward regardless of the pulling speed V (method (4)). .
[0117]
FIG. 9 shows the experimental results of examining the change in the shape of the solid-liquid interface under the pulling condition that the gap 20 is 57 mm, the crucible rotation speed C / R is 3 rpm, and a 3000 G horizontal magnetic field is applied to the silicon melt 5. The horizontal and vertical axes in FIG. 9 correspond to the horizontal and vertical axes in FIG. The growth rate V was changed in the range of 0.35 mm / min to 0.55 mm / min.
[0118]
As shown in FIG. 9, under the condition of applying a horizontal magnetic field, the solid-liquid interface can be convex upward regardless of the pulling speed V.
[0119]
Next, by cooling the silicon crystal 10 with the cooler 30, the method of making the solid-liquid interface convex upward with the pulling speed V maintained at a high speed without reducing the productivity was considered (Method (5)). ).
[0120]
FIG. 10 shows a diameter of 200 mm under a pulling condition in which the gap 20 is 30 mm, the crucible rotation speed C / R is 4 rpm, the silicon crystal rotation speed S / R is 13 rpm, and the cooler 30 is disposed above the silicon melt 5 by a distance of 80 mm. The experimental result which investigated the change of the shape of the solid-liquid interface when producing this silicon crystal 10 is shown. The horizontal and vertical axes in FIG. 10 correspond to the horizontal and vertical axes in FIG. The growth rate V was changed in the range of 0.78 mm / min to 1.48 mm / min.
[0121]
As shown in FIG. 10, under the condition that the silicon crystal 10 is cooled by the cooler 30, the solid-liquid interface shape becomes convex upward even if the pulling speed V is lowered to the critical value at which R-OSF is generated. The lower limit pulling speed V when V / G1 was lowered to the critical value was as high as 1.11 mm / min as can be seen from comparison with FIG.
[0122]
FIG. 11 shows the result of examining the pulling speed V when V / G1 is lowered to the vicinity of the critical value when the crucible rotation speed C / R, which is different from that in FIG. 10, is 1 rpm. The pulling speed V at which R-OSF is not generated was 1.15 mm / min or more. Compared to FIG. 10, it can be seen that the solid-liquid interface at the pulling speed that does not generate R-OSF is convex upward. It has been found that adjusting the crucible rotation speed in addition to installing the cooler in this way is effective for making the solid-liquid interface convex upward.
[0123]
Therefore, the influence of each parameter of the crucible rotation speed C / R and the silicon crystal rotation speed S / R on the shape of the solid-liquid interface was examined.
[0124]
FIG. 18 shows an experiment in which changes in the shape of the solid-liquid interface were examined when only the silicon crystal rotation speed S / R was changed under the same pulling conditions such as the crucible rotation speed C / R without applying a magnetic field. Results are shown. The horizontal and vertical axes in FIG. 18 correspond to the horizontal and vertical axes in FIG. The silicon crystal rotation speed S / R was changed to 4 rpm, 8 rpm, and 12 rpm, respectively.
[0125]
As shown in FIG. 18, it can be seen that the effect of making the solid-liquid interface convex upward increases as the silicon crystal rotation speed S / R increases.
[0126]
FIG. 19 shows an experiment in which the change in the shape of the solid-liquid interface when only the crucible rotation speed C / R is changed with the other pulling conditions such as the silicon crystal rotation speed S / R being the same without applying a magnetic field. Results are shown. The horizontal and vertical axes in FIG. 19 correspond to the horizontal and vertical axes in FIG. The crucible rotation speed C / R was changed to 6 rpm, 7 rpm, 8 rpm, and 10 rpm, respectively.
[0127]
As shown in FIG. 19, it can be seen that the effect of making the solid-liquid interface convex upward increases as the crucible rotation speed C / R increases.
[0128]
Therefore, in addition to installing the cooler 30, by adjusting the silicon crystal rotation speed S / R and the crucible rotation speed C / R, the solid liquid when the pulling speed V is reduced to the critical value at which R-OSF is generated. The interface shape can be convex upward.
[0129]
In this way, by adjusting the silicon crystal rotation speed S / R and the crucible rotation speed C / R in addition to the condition of the cooler installation or the cooler installation, the R-OSF can be reduced in the silicon wafer surface than the normal condition (FIG. 8). The pulling speed V that is not generated can be increased. This is because when the silicon crystal 10 is cooled by the cooler 30, G1 increases and the speed V when V / G1 decreases to a critical value can be increased.
[0130]
FIG. 12 shows the relationship between the pulling speed ratio V / Vmax and the void defect size at the center of the silicon crystal when the silicon crystal 10 is cooled by the cooler 30.
[0131]
The pulling speed ratio V / Vmax is a ratio of the pulling speed V to the limit speed Vmax when the silicon crystal 10 is deformed.
[0132]
As shown in FIG. 12, it can be seen that the defect size becomes smaller as the pulling speed V is lowered and the pulling speed ratio V / Vmax is lowered.
[0133]
A decrease in pulling speed V means a decrease in V · G2, and an increase in void defect size if limited to the parameters of V · G2, but a lower V / G1 effect than a negative effect due to this decrease in V · G2. It is thought that the defect size is reduced.
[0134]
From the above examination results, it is desirable to manufacture the silicon wafer 100D by the following manufacturing method.
[0135]
(Manufacturing method 1)
In this manufacturing method 1, the method (5) is applied, and the cooler 30 is installed in the CZ furnace 2. The cooler 30 is disposed so as to surround the silicon crystal 10 at a distance of 30 mm to 500 mm from the silicon melt 5. The diameter of the silicon crystal 10 was 200 mm.
[0136]
The gap 20 between the lower end of the heat shielding plate 8 and the silicon melt surface 5a is set to 20 mm to 100 mm.
[0137]
Then, the pulling speed V of the silicon crystal 10 by the pulling mechanism 4 is adjusted, and the cooling amount of the cooler 30 is adjusted to increase the axial temperature gradient G1 in the vicinity of the melting point of the silicon crystal 10, so that the growth speed V is 1. The growth condition V / G1 is lowered to near the critical value in a state where the solid-liquid interface is convex upward with respect to the melt surface in the range of 11 to 1.45 mm / min. At this time, the solid-liquid interface center height Xcen is preferably set to 0 to 20 mm. Further, the silicon crystal rotation speed S / R and the crucible rotation speed C / R are adjusted as necessary.
[0138]
According to this manufacturing method, as described with reference to FIG. 10, the silicon crystal 10 is cooled by the cooler 30 to increase G1, and the speed V when V / G1 is lowered to near the critical value is 1.11 mm / min. Higher than that can be maintained. However, as described with reference to FIG. 12, in order to obtain the effect of reducing the void defect size, it is desirable that the pulling speed V is a low speed in the vicinity of the lower limit speed of 1.11 mm / min that does not generate OSF. Even though the speed is low, the speed is sufficiently high compared with the lower limit pulling speed (0.76 mm) that does not generate OSF under normal pulling conditions, and productivity is not inferior.
[0139]
According to this manufacturing method, the growth condition V / G1 is lowered to the vicinity of the critical value in a state in which the solid-liquid interface is convex upward with respect to the melt surface. In addition, the radial distribution of V / G1 in the wafer surface becomes uniform to a certain level or more, so that OSF is not generated in the wafer surface, and the size and density of void defects are reduced by the low V / G1 effect. Can be reduced. Moreover, since the speed V is maintained higher than the normal condition, V · G2 increases, and the defect size can be further reduced by the high V · G2 effect (see FIG. 3). For this reason, the size and density of void defects over the entire surface of the silicon wafer 100D can be reduced to the level indicated by the oblique lines in FIG.
[0140]
In FIG. 2, the width of the silicon wafer 100D in the drawing is narrower than the widths of the silicon wafers 100A and 100B obtained under normal conditions. The V / G1 is made uniform in the wafer surface, and the void defect size and density are It is shown that the wafer is uniformly reduced in the wafer plane.
[0141]
Moreover, in this manufacturing method 1, since the solid-liquid interface is convex upward using the cooler 30 (method (5)), compared with the case where the same thing is achieved by applying a horizontal magnetic field (method (4)). Thus, the device cost can be kept low.
[0142]
Next, the effect of the manufacturing method 1 will be described with reference to FIG.
[0143]
FIG. 13 shows the relationship between the pulling rate and the defect size at the center of the crystal. FIG. 13 corresponds to FIG.
[0144]
Under normal conditions, as shown in FIG. 13 (a), when the pulling speed V is decreased, OSF is generated at the outer periphery of the crystal at a speed V1 before the low V / G1 effect is sufficiently obtained at the crystal center. End up. Therefore, although the low V / G1 effect cannot be obtained, the defect size is reduced by increasing the speed V to the pulling speed V2 at which the high V · G2 effect is obtained. However, the defect size reduction effect is limited only by the high V · G 2 effect.
[0145]
In method {circle around (2)}, as shown in FIG. 13 (b), by lowering the pulling speed V to V3, a low V / G1 effect can be sufficiently obtained at the crystal central portion and the defect size can be sufficiently reduced. . However, there is a possibility that OSF may be generated in the outer periphery of the crystal, and productivity is deteriorated due to a decrease in the pulling speed.
[0146]
On the other hand, in the case of the present invention using the cooler 30, as shown in FIG. 13C, the pulling speed V can be maintained at the high speed V5 and the low V / G1 effect can be obtained. It can be lowered sufficiently. On the other hand, in method (1), G2 is increased by the cooler and the limit speed Vmax is increased, so that the pulling speed V can be increased to an extremely high speed V4 near the limit speed Vmax. Thus, the effect of reducing the defect size is limited because the low V / G1 effect cannot be obtained.
[0147]
14A, 14B, 14C, and 14D show the pulling speeds of 1.45 mm / min (pulling speed ratio V / Vmax = 0.97) and 1.25 mm / min (raising speed ratio V / Vmax = 0.83), 1.15 mm / min (Pulling speed ratio V / Vmax = 0.77), 1.05 mm / min (Pulling speed ratio V / Vmax = 0.70) A histogram of the presence or absence of the R-OSF region and the number of LPDs per wafer is shown.
[0148]
The horizontal axis of the histogram indicates the number of particles having a size of 0.10 μm or more per wafer, and the vertical axis indicates the number of wafers corresponding to each count number.
[0149]
As shown in FIG. 14, it can be seen that the void defects having a large size per wafer decrease as the pulling speed V is decreased from 1.45 mm / min to 1.05 mm / min. Further, it can be seen that OSF is generated in the wafer surface at a pulling rate between 1.15 mm / min and 1.05 mm / min (1.11 mm / min is the lower limit from FIG. 10).
[0150]
Next, the effect of this embodiment compared with the prior art 1 and the prior art 2 (method {circle around (3)}) will be described.
[0151]
Since the prior art 1 does not take into consideration the shape of the solid-liquid interface and the radial distribution of V / G1, the shaded area shown in FIG. 4 is not necessarily an area where the void defect size and density can be reduced. It wasn't. However, according to this embodiment, by adjusting the cooling amount of the cooler 30, the solid-liquid interface is convex upward, and the radial distribution of V / G1 is made uniform. Can be reduced. For this reason, the yield of device defects is improved.
[0152]
Next, it compares with the prior art 2. FIG.
[0153]
Near the solid-liquid interface of the growing silicon crystal, the heat balance is balanced under the Stefan condition shown by the following equation.
[0154]
Ks / Gs = H / V + KL / GL
Ks: thermal conductivity of crystal
KL: Thermal conductivity of the melt
Gs: Temperature gradient of crystal
GL: Temperature gradient of melt
H: latent heat of solidification
V: Pulling speed
In prior art 2 (method (3)), the V / G1 distribution in the crystal diameter direction is made uniform, but in general, in order to make the V / G1 distribution uniform, it is necessary to suppress heat removal from the surface of the crystal. . For this reason, the effect of discharging the solidification latent heat is weakened, Ks · Gs is reduced in the above formula, and the pulling speed V cannot be increased. As a result, the cooling rate is lowered in the void defect generation temperature range, that is, V · G 2 is lowered. For this reason, void defect reduction and productivity are inhibited. On the other hand, in this embodiment, since the silicon crystal 10 is cooled by the cooler 30, G1 increases, and even if the pulling speed V is increased, V / G1 can be reduced and the interface shape is convex upward. The in-plane distribution of / G1 can be kept almost uniform. Further, since the pulling speed V is large, V · G2 can be increased. For this reason, compared with the prior art 2, void defect reduction and productivity can be improved.
[0155]
FIG. 17 compares the present invention with Method (1), Method (2), and Method (3) (Prior Art 2) in terms of reduction in the number of COPs with a size of 0.10 μm or more, productivity, and presence of R-OSF. Is. In FIG. 17, “◎” indicates an evaluation that is very excellent, “◯” indicates an evaluation that is excellent, and “Δ” indicates an evaluation that is slightly inferior. As shown in FIG. 17, the present invention was evaluated to be the best overall in comparison with other methods.
[0156]
(Manufacturing method 2)
The silicon wafer 100D may be manufactured in the same manner as the manufacturing method 1 by applying the method (4). In this case, the same control as in the manufacturing method 1 is performed except that a horizontal magnetic field of 2500 G or more is applied to the silicon melt 5 to make the solid-liquid interface convex upward. In the manufacturing method 2, since the solid-liquid interface can be convex upward regardless of the pulling speed V, the degree of freedom of the pulling speed V is improved.
[0157]
In the first embodiment described above, generation of OSF in the silicon wafer is avoided. However, even if the crystal structure is the OSF region, if the OSF nucleus does not appear in the OSF in the process of manufacturing the device, there may be no problem with the characteristics of the silicon wafer. That is, it is known that the nuclei of R-OSF are oxygen precipitates in the silicon crystal. Therefore, by reducing the oxygen concentration in the silicon crystal or by applying heat treatment that allows the OSF nuclei to disappear after the production of the silicon wafer. It is possible to make the OSF invisible. Therefore, the following manufacturing method may be adopted.
[0158]
(Second Embodiment)
100C shown in FIG. 2 shows the silicon wafer of the second embodiment. The silicon wafer 100C of the embodiment is manufactured so that OSF does not exist in a region from at least the center of the surface to 10 mm inside from the outer periphery in the surface.
[0159]
5 indicate the range of the average void defect density and the average void defect size in the inner region of the R-OSF of the silicon wafer 100C of the second embodiment. In the silicon wafer 100C of the second embodiment, the average void defect density in the inner region of the R-OSF is 5 × 10. ⁶ / cm ³ The average void defect size is 100 nm or less.
[0160]
The manufacturing method of the second embodiment is as follows.
[0161]
(Manufacturing method 3)
In the manufacturing method 3, the method (5) is applied, and the cooler 30 is installed in the CZ furnace 2. The diameter of the silicon crystal 10 was 200 mm.
[0162]
Then, while adjusting the pulling speed V of the silicon crystal 10 by the pulling mechanism 4 and adjusting the cooling amount of the cooler 30 to increase the axial temperature gradient G1 near the melting point of the silicon crystal, the growth condition V / Reduce G1 to near critical value.
[0163]
According to the present manufacturing method, as described with reference to FIG. 10, by cooling the silicon crystal 10 with the cooler 30, G1 increases, and the speed V when V / G1 is lowered to near the critical value can be maintained high. it can. However, since the OSF region is allowed to be generated in the outer peripheral portion of the silicon crystal 10, the solid-liquid interface has a slightly convex shape as compared with the manufacturing method 1 as shown in FIG. As shown, the pulling speed V is lower than that in the manufacturing method 1. For this reason, the effect of reducing the void defect size is further enhanced by further lowering the pulling speed V. Although it is low speed, it is at the same level as the lower limit pulling speed (0.76 mm / min) that does not generate OSF under normal pulling conditions, and productivity is not inferior.
[0164]
According to this manufacturing method, since V / G1 is lowered to the vicinity of the critical value, a low V / G1 effect can be obtained, and the size and density of void defects can be reduced. Moreover, since the speed V is kept high at the same level as the normal condition, V · G2 increases and the defect size can be further reduced by the high V · G2 effect (see FIG. 3). Therefore, in the silicon wafer 100C, the size and density of void defects can be reduced to the level indicated by the diagonal lines in FIG. 5 in at least the region from the center of the surface to the inner side 10 mm from the outer periphery.
[0165]
In FIG. 2, the width of the silicon wafer 100C in the drawing is narrower than the widths of the silicon wafers 100A and 100B obtained under normal conditions. The V / G1 is made uniform in the wafer surface, and the void defect size and density are It is shown that the wafer is uniformly reduced in the wafer plane.
[0166]
In this manufacturing method, the oxygen concentration in the silicon crystal 10 is controlled so that OSF nuclei do not appear in the OSF, and the silicon wafer 100C is subjected to heat treatment. Specifically, any one of the following steps or a combination of these steps is performed as appropriate.
[0167]
(Step 1) The oxygen concentration in the silicon crystal 10 is 12.5 × 10 ¹⁷ atoms / cm ³ Controlled to:
[0168]
(Step 2) A heat treatment of 1000 ° C. or higher is performed on the silicon wafer 100C.
(Step 3) The silicon wafer 100C is heat-treated at 1000 ° C. or higher in a non-oxidizing atmosphere.
[0169]
According to step 3, the effect of eliminating void defects on the surface layer of the silicon wafer can be obtained.
[0170]
Of course, (Step 1), (Step 2), and (Step 3) may be added as appropriate to the manufacturing methods 1 and 2 of the first embodiment. Further, in the manufacturing method 3 of the second embodiment, (Step 1), (Step 2), and (Step 3) may be omitted.
[0171]
The present invention can be applied not only when manufacturing a polished wafer but also when manufacturing an annealed wafer.
[Brief description of the drawings]
FIG. 1 is a diagram conceptually showing a defect formation mechanism.
FIG. 2 is a diagram showing the relationship between defect type and point defect (vacancy, interstitial silicon) concentration.
FIG. 3 is a diagram showing a relationship between a cooling rate, a void defect density, and a void defect size.
FIG. 4 is a diagram for explaining the prior art and showing the relationship between V / G1 and passage time.
FIG. 5 is a diagram showing a relationship between a void defect density and a void defect size.
FIG. 6 is a diagram showing the relationship between the cooling rate at 1100 ° C. and the void defect size.
FIGS. 7A, 7B, and 7C are views showing the relationship between each position in the radial direction of the silicon wafer and V / G1. FIG.
FIG. 8 is a diagram for explaining the relationship between the pulling rate under normal conditions, the solid-liquid interface shape, and the OSF generation rate.
FIG. 9 is a diagram for explaining the relationship between the pulling speed, the solid-liquid interface shape, and the OSF generation speed under the condition where a horizontal magnetic field is applied.
FIG. 10 is a diagram for explaining the relationship between the pulling speed, the solid-liquid interface shape, and the OSF generation speed under the condition in which the cooler is installed.
FIG. 11 is a diagram for explaining a lower limit speed at which no OSF is generated under the condition of installing a cooler.
FIG. 12 is a diagram showing the relationship between the pulling speed ratio under the condition of installing the cooler and the void defect size in the crystal central part.
FIGS. 13A, 13B, and 13C are views for explaining the effect of the embodiment, and showing the relationship between the pulling rate and the void defect size in the center of the crystal.
FIGS. 14A, 14B, 14C, and 14D show the correspondence between the pulling speed ratio under the cooler installation conditions, the presence / absence of an OSF region, and the histogram of the number of LPDs per wafer. FIG.
FIG. 15 is a diagram illustrating a manufacturing apparatus according to an embodiment.
FIG. 16 is a diagram illustrating a solid-liquid interface.
FIG. 17 is a diagram comparing a conventional COP reduction method and a method according to the present invention.
FIG. 18 is a diagram showing changes in the shape of the solid-liquid interface when the silicon crystal rotation speed is changed.
FIG. 19 is a diagram showing changes in the shape of the solid-liquid interface when the crucible rotation speed is changed.
FIG. 20 is a diagram for explaining the relationship between the pulling rate and the solid-liquid interface shape for a silicon crystal having a diameter different from that in FIG.
[Explanation of symbols]
4 Lifting mechanism
5 Melt
10 Silicon crystal
30 cooler
100C, 100D silicon wafer

Claims (13)

In a silicon wafer manufacturing method in which a silicon crystal is pulled and grown from a silicon melt, and a silicon wafer is obtained from the pulled and grown silicon crystal,
By cooling the silicon crystal by cooler, by increasing the axial temperature gradient G1 near the melting point of the silicon crystal, the solid-liquid interface is a boundary between the melt and the silicon crystal in the silicon crystal pulling on the melt surface On the other hand, while making the state of a convex shape upward ,
By setting the growth rate V to the lower limit rate of 1.11 mm / min or more,
The growth condition V / G1 (V: growth rate, G1: axial temperature gradient in the vicinity of the melting point of the silicon crystal) is lowered to near the critical value,
A method for producing a silicon wafer, comprising pulling and growing a silicon crystal. By cooling the silicon crystal with a cooler, the solid-liquid interface is raised with respect to the melt surface when the growth rate V is in the range of 97% to 75% of Vmax (the limit growth rate at which the silicon crystal can grow without deformation). With the convex shape, the growth condition V / G1 is lowered to near the critical value,
The method for producing a silicon wafer according to claim 1, wherein a silicon crystal having no OSF (oxidation induced stacking fault) region is pulled and grown on the entire surface of the silicon wafer. The method for producing a silicon wafer according to claim 1, wherein a magnetic field is applied to the silicon melt to make the solid-liquid interface convex upward with respect to the melt surface. The silicon crystal is cooled by a cooler, and the rotation speed of the silicon crystal or the rotation speed of the crucible containing the silicon melt is adjusted to make the solid-liquid interface convex upward with respect to the melt surface. The method for producing a silicon wafer according to claim 1. In a silicon wafer manufacturing method in which a silicon crystal is pulled and grown from a silicon melt, and a silicon wafer is obtained from the pulled and grown silicon crystal,
By cooling the silicon crystal with a cooler, the axial temperature gradient G1 in the vicinity of the melting point of the silicon crystal is increased, and the solid-liquid interface that is the boundary between the melt and the silicon crystal being pulled up is set to the melt surface. On the other hand, while making the state of a convex shape upward,
By setting the growth rate V to the lower limit rate of 1.11 mm / min or more,
The growth condition V / G1 (V: growth rate, G1: axial temperature gradient in the vicinity of the melting point of the silicon crystal) is lowered to near the critical value,
A silicon wafer manufacturing method characterized by pulling and growing a silicon crystal having no OSF (oxidation-induced stacking fault) region in at least a region from the center of the surface to 10 mm inside from the outer periphery of the surface of the silicon wafer. 6. The method for producing a silicon wafer according to claim 5, wherein the oxygen concentration in the silicon crystal is controlled to 12.5 × 10 ¹⁷ atoms / cm ³ (1979 ASTM) or less. 6. The method for producing a silicon wafer according to claim 5, wherein the silicon wafer is heat-treated at 1000 [deg.] C. or higher so that the OSF nucleus does not appear in the OSF. The silicon wafer is subjected to a heat treatment at 1000 ° C. or higher in a non-oxidizing atmosphere so that OSF nuclei do not appear in the OSF in the silicon wafer and void defects disappear in the surface layer of the silicon wafer. 5. A method for producing a silicon wafer according to 5. In a silicon wafer manufacturing apparatus in which a silicon crystal is pulled and grown by a pulling mechanism from a silicon melt and a silicon wafer is obtained from the silicon crystal that has been pulled and grown.
A cooler for cooling the silicon crystal is provided above the silicon melt,
By adjusting the silicon crystal pulling speed by the pulling mechanism and the cooling amount of the cooler,
The axial temperature gradient G1 in the vicinity of the melting point of the silicon crystal is increased so that the solid-liquid interface that is the boundary between the melt and the silicon crystal during pulling the silicon crystal has a convex shape upward with respect to the melt surface. And
By setting the growth rate V to the lower limit rate of 1.11 mm / min or more,
The growth condition V / G1 (V: growth rate, G1: axial temperature gradient in the vicinity of the melting point of the silicon crystal) is lowered to near the critical value,
A silicon wafer manufacturing apparatus characterized by pulling and growing a silicon crystal. By cooling the silicon crystal with a cooler, the solid-liquid interface is raised with respect to the melt surface when the growth rate V is in the range of 97% to 75% of Vmax (the limit growth rate at which the silicon crystal can grow without deformation). With the convex shape, the growth condition V / G1 is lowered to near the critical value,
The silicon wafer manufacturing apparatus according to claim 9, wherein a silicon crystal having no OSF (oxidation induced stacking fault) region is pulled and grown on the entire surface of the silicon wafer. In a silicon wafer manufacturing apparatus in which a silicon crystal is pulled and grown from a silicon melt and a silicon wafer is obtained from the silicon crystal that has been pulled and grown,
A cooler for cooling the silicon crystal is provided above the silicon melt,
By adjusting the silicon crystal pulling speed by the pulling mechanism and the cooling amount of the cooler,
A state in which the axial temperature gradient G1 in the vicinity of the melting point of the silicon crystal is increased, and the solid-liquid interface that is the boundary between the melt and the silicon crystal being pulled is convex upward with respect to the melt surface. And
By setting the growth rate V to the lower limit rate of 1.11 mm / min or more,
The growth condition V / G1 (V: growth rate, G1: axial temperature gradient in the vicinity of the melting point of the silicon crystal) is lowered to near the critical value,
A silicon wafer manufacturing apparatus characterized by pulling and growing a silicon crystal having no OSF (oxidation-induced stacking fault) region in at least a region from the center of the surface to 10 mm inside from the outer periphery of the surface of the silicon wafer. The apparatus for manufacturing a silicon wafer according to claim 9 or 11, wherein the cooler is disposed so as to surround the silicon crystal at a distance of 30 mm to 500 mm from the silicon melt. A heat shielding plate is provided above the silicon melt, and a gap between the lower end of the heat shielding plate and the silicon melt surface is set to 20 mm to 100 mm. 11. An apparatus for producing a silicon wafer according to 11.

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