JP4230869B2 - High voltage semiconductor device - Google Patents

High voltage semiconductor device Download PDF

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JP4230869B2
JP4230869B2 JP2003332819A JP2003332819A JP4230869B2 JP 4230869 B2 JP4230869 B2 JP 4230869B2 JP 2003332819 A JP2003332819 A JP 2003332819A JP 2003332819 A JP2003332819 A JP 2003332819A JP 4230869 B2 JP4230869 B2 JP 4230869B2
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silicon carbide
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聖支 今井
孝 四戸
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株式会社東芝
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  The present invention relates to a high voltage semiconductor device and a method for manufacturing the same, and more particularly to a high voltage semiconductor device such as an electrostatic induction transistor or a bipolar transistor for power control.

  Silicon carbide (SiC) is expected as a next-generation power semiconductor device material. Compared to Si, SiC has excellent physical properties such as a band gap of 3 times, a breakdown electric field strength of about 10 times, and a thermal conductivity of about 3 times. By utilizing these characteristics, ultra-low loss and high temperature operation are possible. Possible power semiconductor devices can be realized.

There are various high voltage semiconductor devices using such SiC characteristics. For example, an electrostatic induction transistor (hereinafter abbreviated as SIT) is known. SIT is an element having excellent characteristics, but the trench gate type is particularly excellent in switching characteristics. As a trench gate type SIT using SiC, there is one described in Patent Document 1.
JP-A-9-172187 (FIG. 1 etc.)

The trench gate type SIT described in Patent Document 1 has the following problems. That is, a large band discontinuity occurs between the trench gate electrode and the p-type SiC (gate region) provided at the bottom of the trench, resulting in a contact resistance of, for example, 10 −2 Ω · cm 2 or more at the gate electrode interface. Resulting in. Such a large contact resistance increases the charge / discharge time constant RC of the gate region, which hinders the speeding up of SIT switching.

  Here, when an inverter circuit, which is a typical application device of a power semiconductor device, is considered, generally about half of the power loss is occupied by the switching loss of the transistor. That is, unless a high-speed switching operation of the transistor can be realized, an inverter circuit or the like cannot sufficiently achieve a low loss utilizing the physical properties of SiC.

  The contact resistance described above is also present in other elements such as trench-based bipolar transistors and junction barrier Schottky diodes (JBS), and is a problem in realizing a high-speed switching operation.

  The present invention has been made in view of the above-described problems, and provides a high voltage semiconductor device capable of obtaining excellent performance of ultra-low on-resistance by utilizing the physical properties of SiC and greatly reducing switching loss. It aims at providing the manufacturing method.

(Constitution)
In order to solve the above problems, the present invention adopts the following configuration.

A first high breakdown voltage semiconductor device according to the present invention includes a high conductivity silicon carbide layer of a first conductivity type and a portion that is partially provided on one surface of the high resistance silicon carbide layer and is lower than the high resistance silicon carbide layer. A first silicon carbide layer of resistance first conductivity type, a trench provided in the high resistance silicon carbide layer across the first silicon carbide layer, and a second conductivity type provided in the bottom surface of the trench The first silicon carbide region, the insulating layer pattern provided on the side surface of the trench, and the second carbonization provided on the other surface of the high resistance silicon carbide layer and having a lower resistance than the high resistance silicon carbide layer. and silicon layer, the first source electrode having a layer mainly composed of Ni 2 Si and NiSi provided on the silicon carbide layer, the first Ni 2 Si and NiSi provided silicon carbide region And a gate electrode having a layer mainly composed of ; And a drain electrode provided on the layer, the ratio of the NiSi for Ni 2 Si and NiSi sum in each layer mainly containing Ni 2 Si and NiSi is characterized in that 3 to 10% by weight.

A second high breakdown voltage semiconductor device of the present invention includes a first conductivity type high resistance silicon carbide layer and a portion provided on one surface of the high resistance silicon carbide layer and lower than the high resistance silicon carbide layer. A first silicon carbide layer of resistance first conductivity type, a trench provided in the high resistance silicon carbide layer across the first silicon carbide layer, and a second conductivity type provided in the bottom surface of the trench The first silicon carbide region, the insulating layer pattern provided on the side surface of the trench, and the one side of the high resistance silicon carbide layer provided apart from the first silicon carbide layer and the high resistance. A source electrode having a second silicon carbide layer having a lower resistance than the silicon carbide layer, a layer mainly composed of Ni 2 Si and NiSi provided on the first silicon carbide layer, and the first carbonization have a layer mainly containing Ni 2 Si and NiSi provided on the silicon region That a gate electrode, the second; and a drain electrode provided on the silicon carbide layer, the Ni 2 Si and NiSi. 3 to the ratio of the NiSi for Ni 2 Si and NiSi sum in each layer consisting mainly of It is characterized by being 10% by weight .

  The first and second high voltage semiconductor devices of the present invention preferably have the following configuration.

  (1) The second silicon carbide layer is of a first conductivity type, and the high voltage semiconductor device is an electrostatic induction transistor.

(2) The second silicon carbide layer is of a second conductivity type, and the high breakdown voltage semiconductor device is an electrostatic induction thyristor.
(3) The first conductivity type is an N type, the second conductivity type is a P type, and the low resistance first conductivity type first silicon carbide layer has an N type impurity concentration of 5 × 10 19 cm −3 or more. Having

A third high breakdown voltage semiconductor device of the present invention includes a first conductivity type high resistance silicon carbide layer and a second conductivity type first silicon carbide layer provided on one surface of the high resistance silicon carbide layer. Sandwiching the second silicon carbide layer between the first conductivity type second silicon carbide layer partially provided on the first silicon carbide layer and having a lower resistance than the high resistance silicon carbide layer; A trench provided to reach the first silicon carbide layer; an insulating layer pattern provided on a side surface of the trench; and a second resistance lower than that of the first silicon carbide layer provided on a bottom surface of the trench. A first conductivity type silicon carbide region; a third conductivity type first silicon carbide layer provided on the other surface of the high resistance silicon carbide layer and having a lower resistance than the high resistance silicon carbide layer; emitter having a layer mainly composed of Ni 2 Si and NiSi provided on the second silicon carbide layer Comprising the electrode, a base electrode having a layer mainly composed of Ni 2 Si and NiSi provided on the first silicon carbide region, and a collector electrode provided on the third silicon carbide layer, wherein the ratio of NiSi to the sum of Ni 2 Si and NiSi is 3-10% by weight in each layer mainly containing Ni 2 Si and NiSi.
Such a third high voltage semiconductor device of the present invention preferably comprises the following configuration.
The first conductivity type is N-type, the second conductivity type is P-type, and the low-resistance first conductivity-type second silicon carbide layer has an N-type impurity concentration of 5 × 10 19 cm −3 or more. .

A fourth high voltage semiconductor device of the present invention includes a high resistance silicon carbide layer, a first conductivity type source region and a first conductivity type made of silicon carbide provided in a first surface region of the high resistance silicon carbide layer. A drain region; a first channel region made of silicon carbide provided between the first conductivity type source region and the first conductivity type drain region; and a first gate insulating film on the first channel region. A first gate electrode provided between the first conductive type source region and a first conductive type drain region, respectively, and a layer mainly composed of Ni 2 Si and NiSi provided on the first conductive type source region and the first conductive type drain region, respectively. A first transistor having a source electrode and a drain electrode; a second conductivity type source region and a second conductivity type drain region made of silicon carbide provided in a second surface region of the high resistance silicon carbide layer; The first A second channel region made of silicon carbide provided between the conductivity type source region and the second conductivity type drain region, and a second channel region provided on the second channel region via a second gate insulating film A second source electrode and a drain electrode each having a layer mainly composed of Ni 2 Si and NiSi provided on the second conductivity type source region and the second conductivity type drain region, respectively, anda second transistor having a ratio of NiSi for Ni 2 Si and NiSi sum in each layer mainly containing Ni 2 Si and NiSi is characterized in that 3 to 10 wt% .
The fourth high voltage semiconductor device of the present invention preferably has the following configuration.
The first conductivity type is N-type, the second conductivity type is P-type, and the first conductivity-type source region and the first conductivity-type drain region have an N-type impurity concentration of 5 × 10 19 cm −3 or more.

(1) the proportion of NiSi for Ni 2 Si and NiSi sum in each layer mainly containing Ni 2 Si and NiSi is 3-10 wt%.

(1) The main surface of the high-resistance silicon carbide layer is a [0001] plane, and the side wall surface of the trench is any one of [11-20] plane and [1-100].

(2) The trench has a stripe shape, and the longitudinal direction thereof is either the <1-100> direction axis or the <11-20> direction axis.

(Function)
According to the present invention, electrodes mainly composed of Ni 2 Si and NiSi are used as a source electrode and a gate electrode in a trench static induction transistor, a trench static induction thyristor, and the like, and in a trench bipolar transistor, an emitter. It is used as an electrode and a base electrode, respectively. Therefore, the contact resistance of each electrode can be sufficiently reduced in both the P and N type electrodes, and charging / discharging using a trench gate or the like can be performed smoothly and at high speed. Therefore, in each of the above-described elements, it is possible to obtain excellent performance of ultra-low on-resistance by utilizing the physical properties of SiC, greatly reduce the switching loss, and improve the switching characteristics.

In addition, an insulating layer pattern is formed on the side surface of the trench, and an electrode mainly composed of Ni 2 Si and NiSi is selectively (self-aligned) formed on one conductivity type silicon carbide region of the bottom surface of the trench. Therefore, a gate potential can be selectively applied to the silicon carbide region. On the other hand, the gate potential is not directly applied to the side surface of the trench because the insulating film pattern exists. For this reason, the gate voltage can be preferentially applied to the silicon carbide region portion located adjacent to the corner portion of the bottom surface of the trench, and the depletion layer in the high resistance silicon carbide layer adjacent to the portion extends. Therefore, switching characteristics can be improved.

Also in the complementary MOSFET, the contact resistance of each electrode can be sufficiently reduced in both the P and N type electrodes, and charging and discharging through each electrode can be performed smoothly and at high speed. It is possible to obtain excellent performance of ultra-low on-resistance by utilizing physical properties, and to greatly reduce switching loss and improve switching characteristics.

  According to the present invention, it is possible to obtain excellent performance of ultra-low on-resistance by utilizing the physical properties of SiC, greatly reduce switching loss, and improve switching characteristics.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing the configuration of a trench gate type static induction transistor (hereinafter abbreviated as SIT) according to the first embodiment of the present invention. 2 to 4 are process cross-sectional views illustrating a method of manufacturing the element shown in FIG. In the present embodiment, the N type is used as the first conductivity type, and the P type is used as the second conductivity type.

As shown in FIG. 1, the trench gate type SIT according to the present embodiment includes an N-type high-resistance SiC layer 102 and low-resistance N-type source regions 105a and 105b provided on one surface of the N-type high-resistance SiC layer 102. 105c, trenches 104a and 104b, P-type diffusion regions 106a and 106b provided on the bottom surfaces of the trenches 104a and 104b, a silicon oxide film 115 provided on the side surfaces of the trenches 104a and 104b, and an N-type high-resistance SiC And a low-resistance N-type drain region 101 provided on the other surface of the layer 102. Further, the layer 116b mainly composed of Ni 2 Si and NiSi and the Al layer provided thereon constitute source electrodes 109a, 109b and 109c, and the layer 116a mainly composed of Ni 2 Si and NiSi The polysilicon layer 117 provided in the gate electrode constitutes gate electrodes 107 a and 107 b, and the drain electrode 108 is provided in the drain region 101.

  Next, a manufacturing method of the trench gate type SIT shown in FIG. 1 will be described.

First, as shown in FIG. 2A, on an N-type low resistance hexagonal silicon carbide (SiC) substrate (or layer) 101 (later drain region) having an impurity concentration of 1 × 10 19 cm −3 and a thickness of 300 μm. In addition, an N-type high resistance SiC layer 102 having an impurity concentration of 5 × 10 15 cm −3 and a thickness of 8 μm, an impurity concentration of 5 × 10 18 cm −3 to 1 × 10 20 cm −3 , and a thickness of 0. An N-type low resistance SiC layer 103 having a thickness of 3 to 1 μm is sequentially formed. However, although nitrogen is used as the N-type impurity here, another impurity such as phosphorus may be used. Moreover, you may use both impurities simultaneously. Further, instead of forming the N-type low resistance layer, phosphorus or nitrogen is applied to the surface of the N-type high resistance layer 102 at an acceleration energy of 10 to 200 keV and a total dose of 5 × 10 15 cm −2 at a substrate temperature of about 500 ° C. Then, the multi-stage ion implantation is selectively performed under the conditions described above, and then an N-type low resistance region having an impurity concentration of 1 × 10 20 cm −3 is formed in a region about 0.3 μm deep from the surface by activation heat treatment at about 1600 ° C. May be.

Next, a silicon oxide film 111 is formed on the surface of the N-type low resistance layer 103. Thereafter, a resist 112 is spin-coated on the surface of the oxide film 111, and the resist 112 is patterned by a photolithography technique as shown in FIG. Using the patterned resist 112 as an etching mask, as shown in FIG. 2B, the N-type low resistance layer 103 is penetrated by anisotropic etching such as RIE and subsequent smoothing treatment in the trench by CDE or the like. Then, trenches 104a and 104b whose bottoms reach the N-type high resistance layer 102 are formed. Although only two trenches are shown in the drawing, there are more trenches. Due to the formation of the trenches 104a and 104b, the N-type low resistance layer 103 is formed into a striped source region 10.
Patterned to 5a, 105b, 105c. Here, for example, the width of the mesa between the trenches is 2 μm, and the width of the trench is 0.6 μm.

  Then, after removing the resist 112, a silicon oxide film 113 is formed inside the trenches 104a and 104b, as shown in FIG. Thereafter, the oxide film 113 at the bottom of the trenches 104a and 104b is removed by anisotropic etching such as RIE. At the same time, the oxide film 113 on the mesa between the trenches is also removed, but the underlying oxide film 111 and the oxide film on the side walls of the trench remain. Thereby, the ion implantation mask 113A in the following process is formed.

Next, as shown in FIG. 3A, selective ion implantation of 27 Al + is performed on the N-type high resistance layer 102 exposed at the bottom through the ion implantation mask 113A. 27 Al + is implanted in multiple stages under the conditions of substrate temperature Tsub = room temperature to 700 ° C., here about 500 ° C., acceleration energy Eacc = 10 to 150 keV, and total dose Φ = 2 × 10 13 cm −2 . As a result, a 27 Al + implantation layer 114 having an impurity concentration of 1 × 10 18 cm −3 is formed in a region having a depth of 0.3 μm from the surface.

  Thereafter, the oxide film 113A is removed, and P-type diffusion regions 106a and 106b are selectively formed by an activation heat treatment at a substrate temperature Tsub = 1600 ° C. as shown in FIG. The p-type SiC diffusion regions 106a and 106b are gate regions of a trench gate type SIT.

  Next, a silicon oxide film 115 is formed on the substrate surface and in the trenches 104a and 104b. Thereafter, the entire substrate surface is covered with a resist (not shown), and a thin oxide film (natural oxide film or the like) existing on the back surface of the low-resistance SiC substrate 101 is diluted with hydrofluoric acid (HF) or buffered HF or the like. Etch away. Further, a Ni film is deposited on the back surface of the n-type low-resistance SiC substrate 101 to a thickness of about 1 μm to form the drain electrode 108 (FIG. 4A).

  Next, after removing the resist on the substrate surface, a sinter treatment is performed at a substrate temperature Tsub = 800 to 1100 ° C., for example, 950 ° C. for about 5 minutes, so that the ohmic contact of the drain electrode 108 is improved. Thereafter, the silicon oxide film 115 above the source regions 105a, 105b, and 105c and the silicon oxide film 115 at the bottom of the trenches 104a and 104b are simultaneously removed by anisotropic etching such as RIE. As a result, the silicon oxide film 115 is selectively left on the side surfaces of the trenches 104a and 104b.

Next, a Ni film is formed to a thickness of about 5 to 80 nm, preferably about 10 to 50 nm on the entire surface of the substrate by sputtering or the like. Thereafter, the Ni film and the source regions 105a, 105b, and 105c, and the Ni film and the P-type diffusion regions 106a and 106b are heated by heat treatment at a substrate temperature Tsub = 850 to 950 ° C., preferably about 900 ° C. React. Next, by washing the substrate with a mixed solution of sulfuric acid and hydrogen peroxide solution, only the unreacted Ni film on the oxide film 115 is removed. As described above, as a result of the so-called Ni salicide process, the layers 116a (part of the gate electrode) and 116b (part of the source electrode) mainly composed of Ni 2 Si and NiSi are selectively formed.

In this embodiment, in order to obtain a practical low contact resistance for both N-type and P-type, an N-type ohmic interface (corresponding to the interface between the source regions 105a, 105b, 105c and the layer 116b in this embodiment) and P are used. Ni 2 Si and NiSi are the main components of the electrode at the type ohmic interface (corresponding to the interface between the P-type diffusion regions 106a and 106b and the layer 116a in this embodiment). In particular, it is desirable to adjust the ratio of NiSi to the sum of Ni 2 Si and NiSi to be 3 to 10% by weight near the electrode interface by heat treatment at 850 to 950 ° C. Here, as the heat treatment temperature increases from 850 ° C. to 950 ° C., the ratio of NiSi to the sum of Ni 2 Si and NiSi decreases from 10 wt% to 3 wt%.

Here, characteristic diagrams showing the relationship between the ratio of NiSi to the sum of Ni 2 Si and NiSi, the contact resistance of P-type and N-type ohmic, and the impurity concentration of the N-type contact layer are shown in FIGS. Show. 10 to 12, the horizontal axis indicates the ratio of NiSi to the sum of Ni 2 Si and NiSi, the vertical axis indicates the contact resistance of P-type and N-type ohmic, and FIG. 10 shows the N-type contact layer (source region 105a, 105b, 105c) when the impurity concentration is 5 × 10 19 cm −3 , FIG. 11 is a diagram when the impurity concentration of the N-type contact layer is 1 × 10 20 cm −3 , and FIG. 12 is the impurity concentration of the N-type contact layer. Each figure shows a case where the concentration is 4 × 10 19 cm −3 .

Although the Schottky barrier at the N-type ohmic interface is slightly increased to about 0.5 eV by configuring the electrode as described above, the N-type impurity layer has a shallow and high carrier concentration contact layer of about 40 to 60 meV. Therefore, the contact resistance can be kept as low as 1 × 10 −5 Ωcm 2 or less by carrier tunneling. Here, in order to sufficiently cause carrier tunneling to the Schottky barrier, it is important to set the impurity concentration of the N-type contact layer (source regions 105a, 105b, 105c) to 5 × 10 19 cm −3 or more. It is. On the other hand, at the P-type ohmic interface, the Schottky barrier can be set low, contrary to the N-type. That is, since the Schottky barrier can be set relatively low by about 0.1 eV compared to the case where Ni 2 Si is dominant (NiSi ratio is less than 3% by weight), the contact resistance is 1 × 10 −4 Ωcm 2. The following can be reduced.

When the ratio of NiSi to the sum of Ni 2 Si and NiSi is outside the range of 3 to 10% by weight in the vicinity of the electrode interface, it is difficult to reduce the contact resistance of both the N-type and P-type electrodes. The reason is as follows. That is, when the substrate temperature during heat treatment is higher than 950 ° C., the ratio of NiSi to the sum of Ni 2 Si and NiSi is less than 3% by weight, and the main component of the electrode is mainly Ni 2 Si. In contrast, the Schottky barrier at the N-type ohmic interface is as low as about 0.4 eV, but at the P-type ohmic interface made of the same electrode component (Ni 2 Si), the Schottky barrier is relatively opposite to the N-type ohmic interface. It becomes expensive. As a result, the contact resistance of the N-type ohmic is reduced to 5 × 10 −6 Ωcm 2 or less, but the P-type ohmic is remarkably increased to 1 × 10 −2 Ωcm 2 or more. In particular, in SiC, the P-type impurity level is as deep as about 200 to 300 meV, and a high activation rate cannot be obtained. Therefore, it is impossible to obtain a contact layer having a low resistance (high carrier concentration). That is, the width of the Schottky barrier generated at the P-type ohmic interface is narrowed by utilizing a contact layer having a high carrier concentration, and it is difficult to easily cause carrier tunneling. The impact of is enormous. Here, in order to reduce the contact resistance of the P-type ohmic, excessive doping of the P-type impurity induces SiC crystal lattice defects and should be avoided. As a result, it is difficult to obtain a practical low contact resistance with a P-type ohmic electrode made of the same electrode component (Ni 2 Si) as the N-type ohmic electrode.

On the other hand, in the heat treatment at a temperature lower than 850 ° C., the ratio of NiSi to the sum of Ni 2 Si and NiSi is greater than 10% by weight, and in this case, the Schottky barrier at the P-type ohmic interface is 0.4 eV. However, the Schottky barrier at the N-type ohmic interface is higher than 0.5 eV. As a result, the P-type contact resistance is relatively about 1 × 10 −4 Ωcm 2 , but the N-type ohmic contact resistance is larger than 1 × 10 −4 Ωcm 2 . When the Schottky barrier at the N-type ohmic interface is as high as 0.5 eV or more, it becomes difficult to sufficiently cause carrier tunneling to the Schottky barrier by increasing the impurity concentration of the N-type contact layer. It is difficult to reduce the contact resistance of the N-type ohmic to a practical level. Again, excessive doping of N-type impurities to reduce N-type ohmic contact resistance induces SiC crystal lattice defects and must be avoided.

  Next, as shown in FIG. 4A, a polysilicon film is deposited on the entire surface, and this film is etched back to leave the polysilicon layer 117 inside the trenches 104a and 104b. The layers 116a and the polysilicon layer 117 inside the trenches 104a and 104b constitute gate electrodes 107a and 107b. Further, as shown in FIG. 4B, an Al film is formed and patterned to form an Al layer on the layer 116b. The Al layer and the layer 116b constitute source electrodes 109a, 109b, and 109c. Note that by using the MOCVD method, for example, an Al layer having a thickness of about 0.5 to 1 μm is selectively deposited on the layer 116a and the layer 116b, respectively, and the layer 116a and the Al layer thereon are formed as a gate electrode, The layer 116b and the Al layer thereon may be used as the source electrode. Instead of the above-described polysilicon layer or Al layer, a metal such as W or Cu, a metal silicide such as W silicide, or a combination thereof may be formed. Thus, the outline process of the trench gate type SIT is completed.

In the present embodiment, as described above, by using a silicide layer mainly composed of Ni 2 Si and NiSi as a part of the gate electrodes 107a and 107b, the sum of Ni 2 Si and NiSi in the silicide layer in particular. By setting the ratio of NiSi to 3 to 10% by weight, the barrier height is about 0.1 eV with respect to the underlying p-type SiC (P-type diffusion regions 106a and 106b) as compared with the case where Ni 2 Si is dominant. We found it to be lower. As a result, the contact resistance at the interface between the gate electrodes 107a and 107b and the P-type diffusion regions 106a and 106b is greatly reduced, and either the N-type ohmic interface (source electrode interface) or the P-type ohmic interface (gate electrode interface). It is possible to reduce the contact resistance. As a result, the gate potential can be effectively applied to the P-type diffusion regions 106a and 106b, so that the switching characteristics can be remarkably improved.

  Further, in the manufacturing process of the buried gate electrodes 107a and 107b, a Ni salicide process and a subsequent MOCVD method such as an Al film are used to form a gate electrode at the bottom of the fine trench having a width of 0.6 μm. It is possible to form the film more accurately and uniformly with the film thickness.

  Further, it is desirable to consider the setting of the main surface of the hexagonal silicon carbide (SiC) substrate, the trench gate side wall surface, and the longitudinal direction of the gate from the viewpoint of selective formation of the Al film. For example, when the [0001] plane is set as the main surface of the substrate, either the [11-20] plane or the [1-100] plane is used as the trench gate side wall, and the side wall is used as the gate longitudinal direction. Correspondingly, it is desirable to select either the <1-100> direction axis (in the case of [11-20] plane) or the <11-20> direction axis (in the case of [1-100] plane). .

  The reason is that the flatness of the trench gate sidewall formed by RIE and subsequent CDE process strongly depends on the plane orientation. In the case of the {11-20} plane or [1-100] plane, the root mean square Rms of the surface roughness is about 0.3 nm under the optimized CDE condition, and the insulation formed on this plane The root mean square Rms of the surface roughness of the film is also very high at around 0.5 nm reflecting the flatness of the base. When such a highly flat insulating film is formed on the trench side wall, the probability of the formation of Al nuclei on the side wall insulating film can be kept low in the formation of the Al film by the MOCVD method. As a result, an Al film can be formed with good selectivity only on the bottom of the trench. Needless to say, the planes and direction axes mentioned here include equivalent planes and equivalent direction axes.

The results of evaluating the electrical characteristics of the trench gate type SIT manufactured as described above are as follows. In a trench gate type SIT with a withstand voltage of 800 V, the leakage current when applying a gate voltage of −40 V and a drain voltage of 600 V was 1 × 10 −6 A / cm 2 , and the on-resistance was 3 mΩcm 2 . Further, the turn-off time was 10 nanoseconds under the conditions of a power supply voltage of 300 V and a main current density of 150 A / cm 2 , and a very high speed switching operation could be obtained. As a result, the switching loss that occupies about half of the power loss in the inverter circuit can be significantly reduced, and the switching characteristics can be remarkably improved.

On the other hand, as a comparative example, in the SIT having the same configuration as that of this embodiment except that (Ni 2 Si) is used as the silicide layer of each of the gate electrode and the source electrode, the on-resistance is about 3 mΩcm 2 when compared with the same breakdown voltage of 800V. It was equivalent. However, the turn-off time under the same condition is very slow, about 300 nsec, due to the influence of a large contact resistance parasitic on the gate electrode interface. As a result, in an inverter circuit using this, it is difficult to reduce the transistor switching loss that accounts for about half of the power loss, so that the excellent physical properties of silicon carbide cannot be fully utilized after all.

  Here, the reason why the turn-off time can be greatly shortened to 10 nsec according to the present embodiment is that the contact resistance between the P-type diffusion regions 106a and 106b and the buried gate electrodes 107a and 107b is greatly reduced, and the charging using the trench gate is performed. This is because the discharge can be performed smoothly and at high speed. Therefore, by adopting the configuration as described above, it is possible to obtain excellent performance of ultra-low on-resistance by utilizing the physical properties of SiC in the trench gate type SIT, and to greatly reduce switching loss and improve switching characteristics. It can be done.

Another feature of the element structure of this embodiment is that an oxide film 115 is formed as an insulating layer on the side surfaces of the trenches 104a and 104b, and a P-type diffusion region (gate) is selectively formed on the bottom surfaces of the trenches 104a and 104b. (Regions) 106a and 106b are exposed, and gate electrode layers 116a mainly composed of Ni 2 Si and NiSi are selectively formed in the gate regions 106a and 106b. In such a structure, the buried gate electrodes 107a and 107b formed of the gate electrode layer 116a / Al layer 117 do not directly contact the side surfaces of the trenches 104a and 104b, but directly to the gate regions 106a and 106b on the bottom surfaces of the trenches 104a and 104b. I'm in contact. That is, since the buried gate electrodes 107a and 107b are formed in a self-aligned manner with respect to the oxide film 115, the buried gate electrodes 107a and 107b are accurately positioned in the center region of the bottom surfaces of the trenches 104a and 104b. Therefore, the gate potential can be selectively applied to the gate regions 106a and 106b on the bottom surfaces of the trenches 104a and 104b, and the gate potential is not directly applied to the side surfaces of the trenches 104a and 104b. For this reason, the gate voltage can be preferentially applied to the portions of the gate regions 106a and 106b located adjacent to the corners of the bottom surfaces of the trenches 104a and 104b, and the N-type high resistance layer adjacent to the portions. Since the extension of the depletion layer in 102 can be made dominant, the switching characteristics can be improved.

  The present invention can also be applied to electrostatic induction thyristors. In the case of an electrostatic induction thyristor, the conductivity type of the N-type low-resistance hexagonal silicon carbide (SiC) substrate 101 in FIG. 1 may be changed to P-type, and the same effect as in the above embodiment can be obtained.

(Second Embodiment)
FIG. 5 is a cross-sectional view showing the configuration of a trench-based bipolar transistor (hereinafter abbreviated as BJT) according to the second embodiment of the present invention. In the present embodiment, the N type is used as the first conductivity type, and the P type is used as the second conductivity type.

As shown in FIG. 5, the trench base type BJT of this embodiment includes an N-type high-resistance SiC layer 202, a P-type SiC layer 203 provided on one surface of the N-type high-resistance SiC layer 202, and a P-type SiC layer. Low-resistance N-type emitter regions 206a, 206b, 20 partially provided on 203
6c, trenches 205a and 205b, silicon oxide film 215 provided on the side surfaces of trenches 205a and 205b, low-resistance P-type diffusion regions 207a and 207b provided on the bottom surfaces of trenches 205a and 205b, N-type high And a low-resistance N-type collector region 201 provided on the other surface of the resistive SiC layer 202. Further, the layer 216b mainly composed of Ni 2 Si and NiSi and the Al layer provided thereon constitute emitter electrodes 210a, 210b and 210c, and the layer 216a mainly composed of Ni 2 Si and NiSi The polysilicon layer 217 provided on the substrate constitutes base electrodes 208a and 208b, and a collector electrode 209 is provided in the collector region 201.

  Next, a manufacturing method of the trench base type BJT shown in FIG. 5 will be described.

First, an impurity concentration of 5 × 10 5 is formed by epitaxial growth on an N-type low resistance hexagonal silicon carbide (SiC) substrate (or layer) 201 (later collector region) having an impurity concentration of 1 × 10 19 cm −3 and a thickness of 300 μm. 15 cm −3 , 10 μm thick N-type high-resistance SiC layer 202, impurity concentration 3 × 10 17 cm −3 , 1 μm thick P-type SiC layer 203, and impurity concentration 1 × 10 19 cm −3 , thickness A 1 μm N-type low resistance SiC layer 204 is sequentially formed. However, although nitrogen is used as the N-type impurity here, another impurity such as phosphorus may be used. Further, although boron is used as the P-type impurity, another impurity such as aluminum may be used. Moreover, you may use both impurities simultaneously. Further, instead of forming the N-type low resistance SiC layer 204, phosphorus or nitrogen is applied to the surface of the N-type high resistance SiC layer 203, the acceleration energy is 10 to 400 keV at a substrate temperature of about 500 ° C., and the total dose is 2 × 10 15 cm. -2 ion implantation is selectively performed under the condition of -2 , and then an N type low resistance region having an impurity concentration of 1 × 10 19 cm -3 is formed in a region about 0.7 μm deep from the surface by activation heat treatment at about 1600 ° C. It may be formed. Similarly, the P-type SiC layer 203 may be formed by ion implantation using aluminum, boron, or the like.

  Next, a silicon oxide film (not shown) is formed on the surface of the N-type low resistance layer 204 as in the first embodiment. Thereafter, a resist (not shown) is spin-coated on the surface of the oxide film, and the resist is patterned by a photolithography technique. Then, using the patterned resist as an etching mask, the N-type low-resistance layer 204 is penetrated by anisotropic etching such as RIE and subsequent smoothing treatment in the trench by CDE or the like, and the bottom is the P-type layer 203. Trenches 205a and 205b are formed. Although only two trenches are shown in the drawing, there are more trenches. By forming the trenches 205a and 205b, the N-type low resistance layer 204 is patterned into the stripe-shaped emitter regions 206a, 206b and 206c.

  Next, after removing the resist, an oxide film (not shown) is formed in the trenches 205a and 205b as in the first embodiment. The oxide film at the bottom of the trenches 205a and 205b is removed by anisotropic etching such as RIE. Thereby, an ion implantation mask for the following process is formed.

Then, selective ion implantation of 27 Al + is performed on the P-type layer 203 exposed at the bottoms of the trenches 205a and 205b through this ion implantation mask, as in the first embodiment. 27 Al + is implanted in multiple stages under the conditions of a substrate temperature Tsub = room temperature to 700 ° C., here about 500 ° C., acceleration energy Eacc = 10 to 150 keV, and total dose Φ = 2 × 10 15 cm −2 . As a result, a 27 Al + implantation layer having an impurity concentration of 1 × 10 20 cm −3 is formed in a region having a depth of 0.3 μm from the surface.

Thereafter, as in the first embodiment, all the oxide films on the substrate are removed, and P-type diffusion regions 207a and 207b are selectively formed by activation heat treatment at a substrate temperature Tsub = 1600 ° C. The P type diffusion regions 207a and 207b are base contact regions of a trench base type BJT.

  Next, an oxide film is formed in the same manner as in the first embodiment on the substrate surface and in the trenches 205a and 205b. Thereafter, the entire substrate surface is covered with a resist, and a thin oxide film (natural oxide film or the like) existing on the back surface of the low-resistance SiC substrate 201 is etched with diluted hydrofluoric acid (HF) or buffered HF. On the back surface of the n-type low-resistance SiC substrate 201, a Ni film is deposited to a thickness of about 1 μm to form a collector electrode 209 (FIG. 4B).

  Next, after removing the resist on the substrate surface, a sinter treatment is performed at a substrate temperature Tsub = 800 to 1100 ° C., for example, 950 ° C. for about 5 minutes to improve the ohmic contact of the collector electrode 209. Thereafter, the oxide film above the emitter regions 206a, 206b, and 206c and the oxide film at the bottom of the trenches 205a and 205b are simultaneously removed by anisotropic etching such as RIE. As a result, the silicon oxide film 215 is selectively left on the side surfaces of the trenches 205a and 205b.

Next, a Ni film is formed to a thickness of about 5 to 80 nm, preferably about 10 to 50 nm on the entire surface of the substrate by sputtering or the like. Thereafter, the Ni film and the emitter regions 206a, 206b, and 206c, and the Ni film and the P-type diffusion regions 206a and 206b are heated by heat treatment at a substrate temperature Tsub = 850 to 950 ° C., preferably about 900 ° C. React. Next, by washing the substrate with a mixed solution of sulfuric acid and hydrogen peroxide solution, only the unreacted Ni film on the oxide film 215 is removed. As described above, as a result of the so-called Ni salicide process, layers 216a (part of the base electrode) and 216b (part of the emitter electrode) mainly composed of Ni 2 Si and NiSi are selectively formed.

  Next, a polysilicon film is deposited on the entire surface, and this film is etched back to leave the polysilicon layer 217 inside the trenches 205a and 205b. The layers 216a and the polysilicon layer 217 inside the trenches 205a and 205b constitute base electrodes 208a and 208b. Furthermore, an Al layer is formed on the layer 216b by forming an Al film and patterning it. The Al layer and layer 216b constitute emitter electrodes 210a, 210b, and 210c. Note that, by using the MOCVD method, for example, an Al layer having a thickness of about 0.5 to 1 μm is selectively deposited on the layer 216a and the layer 216b, respectively, and the layer 216a and the Al layer thereon are formed as a base electrode, The layer 216b and the Al layer thereon may be used as the emitter electrode. Instead of the above-described polysilicon layer or Al layer, a metal such as W or Cu, a metal silicide such as W silicide, or a combination thereof may be formed. Thus, the outline process of the trench base type BJT is completed.

In this embodiment, as in the first embodiment, the base electrode 208a, by using a silicide layer mainly composed of Ni 2 Si and NiSi as part of 208b, Ni 2 Si, especially in the silicide layer When the ratio of NiSi to the sum of NiSi is 3 to 10% by weight, the barrier height is lower than the underlying p-type SiC (P-type diffusion regions 207a and 207b) compared to the case where Ni 2 Si is dominant. It is about 0.1 eV lower. As a result, the contact resistance at the interface between the base electrodes 208a and 208b and the P-type diffusion regions 207a and 207b is greatly reduced, and either the N-type ohmic interface (emitter electrode interface) or the P-type ohmic interface (base electrode interface). It is possible to reduce the contact resistance. Thereby, the base potential can be effectively applied to the P-type diffusion regions 207a and 207b, so that the switching characteristics can be remarkably improved.

In addition, in the manufacturing process of the embedded base electrodes 208a and 208b, a base electrode is formed at the bottom of the fine trench having a width of 0.6 μm by using a Ni salicide process and a subsequent MOCVD method such as an Al film. It is possible to form the film more accurately and uniformly with the film thickness.

  In addition, it is desirable to sufficiently consider the setting of the main surface of the hexagonal silicon carbide (SiC) substrate, the trench base side wall surface, and the longitudinal direction of the base from the viewpoint of selective formation of the Al film. Since this is the same as in the case of the first embodiment, a description thereof is omitted here.

The results of evaluating the electrical characteristics of the trench-based BJT manufactured as described above are as follows. With a trench gate type BJT having a withstand voltage of 1600 V, the leakage current when applying a base current of 100 mA and a collector voltage of 1200 V was 1 × 10 −6 A / cm 2 , and the on-resistance was 7 mΩcm 2 . In addition, under the conditions of a power supply voltage of 500 V and a main current density of 150 A / cm 2, a very fast switching operation with a turn-off time of 30 nanoseconds could be obtained. As a result, the switching loss that accounts for about half of the power loss in the inverter circuit can be greatly reduced, and the switching characteristics can be improved.

On the other hand, as a comparative example, in the BJT having the same configuration as that of the present embodiment except that (Ni 2 Si) is used as the silicide layer of each of the base electrode and the emitter electrode, the on-resistance is about 8 mΩcm 2 when compared at the same breakdown voltage of 1600V. It was equivalent. However, the turn-off time under the same condition is very slow as about 300 nsec because the base current is not discharged smoothly and at high speed due to the influence of a large contact resistance parasitic on the base electrode interface. As a result, in an inverter circuit using this, it is difficult to reduce the transistor switching loss corresponding to about half of the power loss, so that the excellent physical properties of silicon carbide cannot be fully utilized.

  Here, the reason why the turn-off time can be greatly shortened to 30 nsec by the present invention is that the contact resistance between the P-type diffusion regions 207a and 207b and the buried base electrodes 208a and 208b is greatly reduced, and the injection and discharge of the base current are reduced. This is because it has been achieved smoothly and at high speed. Therefore, by adopting the configuration as described above, it is possible to obtain excellent performance of ultra-low on-resistance by utilizing the physical properties of SiC in the trench base type BJT, and greatly reduce switching loss and improve switching characteristics. It can be done.

(Third embodiment)
FIG. 6 is a cross-sectional view showing the configuration of a trench gate type lateral static induction transistor (hereinafter abbreviated as lateral SIT) according to the third embodiment of the present invention. The difference between the lateral SIT of this embodiment and the SIT of the first embodiment is that the drain electrode is formed not on the back surface of the substrate but on the surface of the N-type high resistance layer formed by epitaxial growth or the like. In the present embodiment, the N type is used as the first conductivity type, and the P type is used as the second conductivity type.

  That is, in this embodiment, unlike the first embodiment in which the N-type low resistance layer 103 is formed on the N-type high resistance layer 102 by an epitaxial method or the like, an N-type low resistance hexagonal silicon carbide (SiC) substrate ( Alternatively, phosphorus or nitrogen or both are selectively ion-implanted into a predetermined region on the surface of the N-type high-resistance SiC layer 302 on the layer 301 to form an N-type region, and stripes are formed from the N-type region. N-type source regions 305a, 305b, and 305c are formed. As a method of forming the N-type source regions 305a, 305b, and 305c, the method described in the first embodiment can be applied. P-type SiC diffusion regions (gate regions) 306a and 306b and a silicon oxide film 315 The gate electrodes 309a and 309b made of the Al film 316a / polycrystalline silicon 317 and the source electrodes 310a, 310b, and 310c made of the Al film 316b / Al layer are also formed by the same method as in the first embodiment.

Further, the N-type drain region 308 is located on the surface of the N-type high-resistance SiC layer 302 on the same side as the side where the N-type source regions 305a, 305b, and 305c are formed, at a position spaced apart from the gate regions 306a and 306b. Form. Between the N-type source regions 305a, 305b, and 305c and the N-type drain region 308, one or more P-type electric field relaxation regions 307a and 307b are provided in parallel with the gate regions 306a and 306b. . The P-type electric field relaxation regions 307a and 307b alleviate the electric field concentration at the ends of the gate regions 306a and 306b.

In this embodiment, after forming the trench, an oxide film 315 is formed on the entire surface including the inner surface of the trench, a resist mask is formed thereon, and a source contact hole and a drain contact hole are opened. The source contact holes are opened so as to include the gate regions 306a and 306b, and the silicon oxide film 115 above the source regions 305a, 305b and 305c and the drain region 308 and the silicon oxide at the bottom of the trench are formed by anisotropic etching such as RIE. The film 315 is removed at the same time. In this removal step, the silicon oxide film 315 is selectively left on the side surface of the trench. Thereafter, using a salicide process similar to that of the first embodiment, a layer 316b mainly composed of Ni 2 Si and NiSi is formed on the N-type source regions 305a, 305b, and 305c, and an Ni-type drain region 308 is formed on the Ni-type drain region 308. the layer 316c composed mainly of 2 Si and NiSi, P-type SiC diffusion region (gate region) 306a, a layer 316a composed mainly of Ni 2 Si and NiSi on 306 b, is formed. The compositions of the layers 316a, 316b, 316c are the same. Further, the source electrodes 310a, 310b, 310c, the drain electrode 311, and the gate electrodes 309a, 309b are formed by a normal electrode forming process. Here, the drain electrode 311 is preferably formed in parallel to the gate electrodes 309a and 309b at a predetermined distance from the gate electrodes 309a and 309b. Configurations and processes other than those described above are basically the same as the SIT of the first embodiment shown in FIG. This completes the horizontal SIT.

  In the lateral SIT, since the source electrode and the drain electrode are provided on the same surface, the monolithic IC can be easily integrated on the same semiconductor chip. In addition, wiring work is also simplified when incorporated in a hybrid IC or the like. Further, since the drain electrode is provided in each semiconductor device, the degree of freedom of surface wiring and connection is increased, and the design is facilitated. In such a lateral SIT as well, it is possible to obtain excellent performance of ultra-low on-resistance by utilizing the physical properties of SiC as in the first embodiment, and to greatly reduce switching loss and improve switching characteristics.

  The present invention can also be applied to electrostatic induction thyristors. In the case of an electrostatic induction thyristor, the conductivity type of the N-type drain region 308 in FIG. 6 may be changed to P-type, and the same effect as in the above embodiment can be obtained.

(Fourth embodiment)
FIG. 7 is a sectional view showing the configuration of a complementary MOSFET (hereinafter abbreviated as CMOS) according to the fourth embodiment of the present invention. 8 and 9 are process sectional views showing a method of manufacturing the element shown in FIG. In the present embodiment, the N type is used as the first conductivity type, and the P type is used as the second conductivity type.

First, as shown in FIG. 8A, an N well 402 and a P well 403 are respectively formed on the surface of a high resistance silicon carbide substrate 401 by a well formation method using an ion implantation method. Here, nitrogen is used as the N-type impurity, but another impurity such as phosphorus may be used. Further, although boron is used as the P-type impurity, another impurity such as aluminum may be used. Moreover, you may use both impurities simultaneously. Specifically, with respect to nitrogen, multistage ion implantation is selectively performed under conditions of an acceleration energy of 10 to 400 keV and a total dose of 1 × 10 12 cm −2 at a substrate temperature of about room temperature. On the other hand, boron is also selectively implanted in multiple stages under the conditions that the substrate temperature is about room temperature, the acceleration energy is 10 to 400 keV, and the total dose is 2 × 10 12 . The electrical activation of impurities after ion implantation is performed by heat treatment at about 1600 ° C.

Next, as shown in FIG. 8B, impurity ions are implanted to form source / drain regions 405a, 405b, 404a, and 404b in the respective regions of the nMOS transistor and the pMOS transistor. Phosphorus is implanted into the nMOS transistor region (P well 403) and aluminum is implanted into the pMOS transistor region (N well 402). Specifically, with respect to phosphorus, multistage ion implantation is selectively performed under conditions of an acceleration energy of 10 to 200 keV and a total dose of 5 × 10 15 cm −2 at a substrate temperature of about 500 ° C. On the other hand, aluminum is also selectively subjected to multistage implantation under the conditions of a substrate temperature of about 500 ° C., acceleration energy of 10 to 150 keV, and total dose of 2 × 10 15 cm −2 . The electrical activation of impurities after ion implantation is performed by heat treatment at about 1600 ° C. Although phosphorus is used as the N-type impurity, other impurities such as nitrogen may be used. Further, although aluminum is used as the P-type impurity, another impurity such as boron may be used. Moreover, you may use both impurities simultaneously.

Next, as shown in FIG. 8C, an element isolation insulating film 406 is formed on the surface of the silicon carbide substrate 401 by a known element isolation method (for example, short trench isolation), and then a gate insulating film (for example, silicon oxide). Film) 407 is formed. Next, as shown in FIG. 8D, an undoped polycrystalline silicon film 408 having a thickness of about 40 nm is formed on the entire surface by CVD. Next, As is selectively implanted into the nMOS transistor region and boron is selectively ion-implanted into the pMOS transistor region in the regions of the polycrystalline silicon film 408 that will be the gate electrodes of the nMOS transistor and the pMOS transistor. These ion implantations are for reducing the resistance of the gate electrode. Ion implantation conditions are, for As, 30keV, 4 × 10 15 cm -2, with respect to boron and 3keV, 4 × 10 15 cm -2 . The electrical activation of the impurities after ion implantation is performed by RTA (Rapid Thermal Annealing) at 950 ° C. for 10 seconds.

  Next, as shown in FIG. 9A, after the polycrystalline silicon film 408 and the gate insulating film 407 are processed into the shape of the gate electrode, side wall insulating films 409a and 409b are formed on the side walls of the gate electrodes 408a and 408b, respectively. To do. The sidewall insulating films 409a and 409b are formed, for example, by depositing a silicon oxide film having a thickness of 5 nm and a silicon nitride film having a thickness of 40 nm sequentially on the entire surface, and then subjecting these insulating films to anisotropic etching. Here, a laminated insulating film is used as the sidewall insulating film, but a single-layer insulating film may be used.

Next, as shown in FIG. 9B, a Ni film 410 is formed to a thickness of about 5 to 80 nm, preferably about 10 to 50 nm on the entire surface of the substrate by sputtering. Thereafter, by heat treatment at a substrate temperature of 850 to 950 ° C., preferably about 900 ° C., the surface of the Ni film 410 and the N-type source / drain regions 405a and 405b, the surfaces of the P-type source / drain regions 404a and 404b, and polycrystalline silicon The surface of each of the gate electrodes 408a and 408b made of is subjected to thermal reaction. Next, by washing the substrate with a mixed solution of sulfuric acid and hydrogen peroxide solution, only the unreacted Ni film on the insulating films (sidewall insulating films 409a and 409b and element isolation insulating film 406) is removed. The As described above, as a result of the so-called Ni salicide process, the layers 411a, 411b, 411d, 411e, 411c, and 411f mainly containing Ni 2 Si and NiSi are selectively formed. Layers 411a and 411b are part of the source / drain electrodes of the pMOS transistor, layer 411c is part of the gate electrode of the pMOS transistor, layers 411d and 411e are part of the source / drain electrode of the nMOS transistor, and 411f is the nMOS It becomes part of the gate electrode of the transistor. Thereafter, an interlayer insulating film and metal wiring (not shown) are formed according to a known method to complete the CMOS.

Also in this embodiment, as in the first embodiment, Ni 2 is used as at least part of the source / drain electrodes and the gate electrode of each of the nMOS transistor and the pMOS transistor.
By using a silicide layer mainly composed of Si and NiSi, Ni 2 Si is dominant by making the ratio of NiSi to the sum of Ni 2 Si and NiSi in the silicide layer 3 to 10% by weight. Compared to the case, the barrier height is about 0.1 eV lower than the underlying p-type SiC (P-type source / drain regions 404a and 404b). As a result, the contact resistance can be greatly reduced at each of the interfaces between the P-type source / drain regions 404a and 404b and the electrode layers 411a and 411b, and an N-type ohmic interface (source / drain and gate of an nMOS transistor). In addition, it is possible to reduce the contact resistance at both the P-type ohmic interface (source / drain and gate of the pMOS transistor). As a result, a potential can be effectively applied not only to the N-type source / drain regions 405a and 405b but also to the P-type source / drain regions 404a and 404b, thereby reducing power consumption with an ultra-low on-resistance. At the same time, the switching characteristics can be remarkably improved. Further, since the Ni salicide process is adopted, the manufacturing process can be simplified.

  Therefore, by adopting the configuration as described above, in the CMOS as well as in the first embodiment, the physical properties of SiC are utilized to obtain excellent performance of ultra-low on-resistance, and the switching loss is greatly reduced. Switching characteristics can be improved.

(Other embodiments)
As described above, the present invention has been disclosed by the first to fourth embodiments, but the present invention is not limited to these embodiments.

For example, in the description of the first to fourth embodiments already described, the silicon oxide film is used as the insulating film formed on the trench or the surface, but in addition to this, tantalum oxide (Ta 2 O 5 ), silicon nitride ( Other insulating films such as Si 3 N 4 ) and aluminum nitride (AlN) may be used.
Further, although the first conductivity type is N-type and the second conductivity type is P-type, both may be interchanged.

Further, the present invention is not limited to a trench gate type electrostatic induction transistor, an electrostatic induction thyristor, a trench base type bipolar transistor, or a complementary MOSFET, and other carbonizations having both a P type ohmic interface and an N type ohmic interface. The present invention can also be applied to a semiconductor element made of silicon. For example, for an N-type source region of a high voltage MOSFET and a P-type contact region provided on or adjacent to the surface of the source region, an electrode layer provided in contact with both regions simultaneously. The present invention can be applied. For example, a P-type contact region is provided on the surface of the N-type source region (405a or 405b) in FIG. 7 or adjacent to the N-type source region, and contacts are made simultaneously so as to straddle the source region and the P-type contact region. The electrode layer may be a layer mainly composed of Ni 2 Si and NiSi described above. Such a high breakdown voltage MOSFET may be a horizontal type or a vertical type. In this case as well, it is possible to obtain excellent performance of ultra-low on-resistance by utilizing the physical properties of SiC as in the first embodiment, and to greatly reduce the switching loss and improve the switching characteristics.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 is a cross-sectional view showing a configuration of a trench gate type static induction transistor according to a first embodiment of the present invention. Process sectional drawing which shows the manufacturing method of the electrostatic induction transistor shown in FIG. Process sectional drawing following FIG. Process sectional drawing following FIG. Sectional drawing which shows the structure of the trench base type bipolar transistor which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the structure of the horizontal static induction transistor of a trench gate type | mold which concerns on the 3rd Embodiment of this invention. Sectional drawing which shows the structure of the CMOS transistor which concerns on the 4th Embodiment of this invention. FIG. 8 is a process cross-sectional view illustrating a method for manufacturing the CMOS transistor illustrated in FIG. 7. Process sectional drawing following FIG. Characteristic diagram showing the relationship between the contact resistance of NiSi ratio and P-type ohmic and N-type ohmic to the sum of the Ni 2 Si and NiSi in the layer mainly composed of Ni 2 Si and NiSi. Characteristic diagram showing the relationship between the contact resistance of NiSi ratio and P-type ohmic and N-type ohmic to the sum of the Ni 2 Si and NiSi in the layer mainly composed of Ni 2 Si and NiSi. Characteristic diagram showing the relationship between the contact resistance of NiSi ratio and P-type ohmic and N-type ohmic to the sum of the Ni 2 Si and NiSi in the layer mainly composed of Ni 2 Si and NiSi.

Explanation of symbols

101 N-type low resistance hexagonal silicon carbide (SiC) substrate (drain region)
102 N-type high resistance SiC layer 103 N-type low resistance SiC layer 104a, 104b Trench 105a, 105b, 105c Source region 106a, 106b p-type SiC diffusion region (gate region)
107a, 107b Gate electrode 108 Drain electrode 109a, 109b, 109c Source electrode 111, 113 Silicon oxide film 112 Resist 113A Ion implantation mask 114 27 Al + implantation layer 115 Silicon oxide film 116a, 116b Ni 2 Si and NiSi are the main components. Layer 117 polysilicon layer

Claims (9)

  1. A first conductivity type high-resistance silicon carbide layer and a first conductivity-type first silicon carbide partially provided on one surface of the high-resistance silicon carbide layer and having a lower resistance than the high-resistance silicon carbide layer A layer, a trench provided in the high resistance silicon carbide layer with the first silicon carbide layer interposed therebetween, a first conductivity type first silicon carbide region provided on a bottom surface of the trench, and the trench An insulating layer pattern provided on a side surface, a second silicon carbide layer having a lower resistance than the high resistance silicon carbide layer provided on the other surface of the high resistance silicon carbide layer, and the first silicon carbide layer A source electrode having a layer mainly composed of Ni 2 Si and NiSi provided on the gate electrode, and a gate electrode having a layer mainly composed of Ni 2 Si and NiSi provided on the first silicon carbide region; A drain electrode provided on the second silicon carbide layer; Bei, and high breakdown voltage semiconductor device percentage of NiSi for Ni 2 Si and NiSi sum in each layer mainly containing Ni 2 Si and NiSi is characterized in that 3 to 10% by weight.
  2. A first conductivity type high-resistance silicon carbide layer and a first conductivity-type first silicon carbide partially provided on one surface of the high-resistance silicon carbide layer and having a lower resistance than the high-resistance silicon carbide layer A layer, a trench provided in the high resistance silicon carbide layer with the first silicon carbide layer interposed therebetween, a first conductivity type first silicon carbide region provided on a bottom surface of the trench, and the trench An insulating layer pattern provided on a side surface and a second carbonized carbon which is provided on the one surface of the high resistance silicon carbide layer and spaced apart from the first silicon carbide layer and has a lower resistance than the high resistance silicon carbide layer. and silicon layer, the first source electrode having a layer mainly composed of Ni 2 Si and NiSi provided on the silicon carbide layer, the first Ni 2 Si and NiSi provided silicon carbide region A gate electrode having a layer mainly composed of ; And a drain electrode provided on the silicon layer, the ratio of the NiSi for Ni 2 Si and NiSi sum in each layer mainly containing Ni 2 Si and NiSi is characterized in that 3 to 10 wt% High voltage semiconductor device.
  3. 3. The high breakdown voltage semiconductor device according to claim 1, wherein the second silicon carbide layer is of a first conductivity type, and the high breakdown voltage semiconductor device is an electrostatic induction transistor.
  4. 3. The high breakdown voltage semiconductor device according to claim 1, wherein the second silicon carbide layer is of a second conductivity type, and the high breakdown voltage semiconductor device is an electrostatic induction thyristor.
  5. A first conductivity type high resistance silicon carbide layer, a second conductivity type first silicon carbide layer provided on one surface of the high resistance silicon carbide layer, and a portion on the first silicon carbide layer The first conductivity type second silicon carbide layer having a lower resistance than the high resistance silicon carbide layer and the second silicon carbide layer sandwiched between and reaching the first silicon carbide layer. A trench, an insulating layer pattern provided on a side surface of the trench, a first silicon carbide region of a second conductivity type provided on a bottom surface of the trench and having a lower resistance than the first silicon carbide layer, A third silicon carbide layer of the first conductivity type provided on the other surface of the high resistance silicon carbide layer and having a lower resistance than the high resistance silicon carbide layer, and Ni 2 provided on the second silicon carbide layer. An emitter electrode having a layer mainly composed of Si and NiSi, and the first silicon carbide region; Each layer a base electrode having a layer mainly composed of Ni 2 Si and NiSi provided, comprising a collector electrode provided on the third silicon carbide layer, composed mainly of the Ni 2 Si and NiSi A high breakdown voltage semiconductor device, wherein the ratio of NiSi to the sum of Ni 2 Si and NiSi is 3 to 10% by weight.
  6. A high resistance silicon carbide layer, a first conductivity type source region and a first conductivity type drain region made of silicon carbide provided in a first surface region of the high resistance silicon carbide layer, and the first conductivity type source region; A first channel region made of silicon carbide provided between the first conductivity type drain regions, and a first gate electrode provided on the first channel region via a first gate insulating film; A first source electrode and a drain electrode each having a layer mainly composed of Ni 2 Si and NiSi provided on the first conductivity type source region and the first conductivity type drain region, respectively. A second conductivity type source region and a second conductivity type drain region made of silicon carbide provided in a second surface region of the high resistance silicon carbide layer, the second conductivity type source region and the second conductivity Type A second channel region made of silicon carbide provided between the in regions, a second gate electrode provided on the second channel region via a second gate insulating film, and the second conductivity A second transistor comprising: a second source electrode and a drain electrode each having a layer mainly composed of Ni 2 Si and NiSi provided on the type source region and the second conductivity type drain region; comprising a high breakdown voltage semiconductor device percentage of NiSi for Ni 2 Si and NiSi sum in each layer mainly containing Ni 2 Si and NiSi is characterized in that 3 to 10% by weight.
  7. The first conductivity type is N-type, the second conductivity type is P-type, and the low-resistance first conductivity-type first silicon carbide layer has an N-type impurity concentration of 5 × 10 19 cm −3 or more. The high withstand voltage semiconductor device according to claim 1, wherein the high withstand voltage semiconductor device is provided.
  8. The first conductivity type is N-type, the second conductivity type is P-type, and the low-resistance first conductivity-type second silicon carbide layer has an N-type impurity concentration of 5 × 10 19 cm −3 or more. The high breakdown voltage semiconductor device according to claim 5, wherein the high breakdown voltage semiconductor device is provided.
  9. The first conductivity type is N type, the second conductivity type is P type, and the first conductivity type source region and the first conductivity type drain region have an N type impurity concentration of 5 × 10 19 cm −3 or more. The high breakdown voltage semiconductor device according to claim 6.
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