JP4206574B2 - Voltage detection circuit of the battery pack - Google Patents

Voltage detection circuit of the battery pack Download PDF

Info

Publication number
JP4206574B2
JP4206574B2 JP23078699A JP23078699A JP4206574B2 JP 4206574 B2 JP4206574 B2 JP 4206574B2 JP 23078699 A JP23078699 A JP 23078699A JP 23078699 A JP23078699 A JP 23078699A JP 4206574 B2 JP4206574 B2 JP 4206574B2
Authority
JP
Grant status
Grant
Patent type
Prior art keywords
voltage
capacitor
unit
connected
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP23078699A
Other languages
Japanese (ja)
Other versions
JP2001056350A (en )
Inventor
大助 小西
Original Assignee
株式会社ジーエス・ユアサコーポレーション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/005Testing of electric installations on transport means
    • G01R31/006Testing of electric installations on transport means on road vehicles, e.g. automobiles or trucks
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36Apparatus for testing electrical condition of accumulators or electric batteries, e.g. capacity or charge condition
    • G01R31/3606Monitoring, i.e. measuring or determining some variables continuously or repeatedly over time, e.g. current, voltage, temperature, state-of-charge [SoC] or state-of-health [SoH]
    • G01R31/362Monitoring, i.e. measuring or determining some variables continuously or repeatedly over time, e.g. current, voltage, temperature, state-of-charge [SoC] or state-of-health [SoH] based on measuring voltage only

Description

【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、複数の単位電池を直列接続して構成された組電池において、各単位電池の電圧を検出する回路に関する。 The present invention provides a battery pack configured by serially connecting a plurality of unit batteries, a circuit for detecting the voltage of each unit cell.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
例えば、電気自動車の動力用バッテリーは多数の単位電池を直列接続して所要の高電圧を確保した組電池により構成されている。 For example, the power battery of the electric vehicle is constituted by an assembled battery which ensures the required high voltage multiple unit cells connected in series. このような電池システムでは、各単位電池の電圧にばらつきが生ずると、電池システムの信頼性が低下するおそれがあるため、各単位電池の電圧を検出して、各単位電池が所定の状態にあるか否かを監視するようにしている。 In such a cell system, when the variation occurs in the voltage of each unit cell, since the reliability of the battery system may be reduced, by detecting the voltage of each unit cell, the unit cell is in a predetermined state and so as to monitor whether.
【0003】 [0003]
各単位電池の電圧を検出するためには、一般に、図5に示すような構成が利用される。 To detect the voltage of each unit cell is generally configured as shown in FIG. 5 is utilized. ここでは、単位電池は図面の簡略化のために4個のみ図示してあり、各単位電池E1〜E4の例えば正極側の出力端子と、グランドラインGNDとの間に抵抗RA,RBを直列接続してなる分圧回路P1〜P4が接続されると共に、各分圧回路P1〜P4における抵抗RA,RB間の共通接続点は、電圧検出用のCPU1に接続されている。 Here, the unit batteries Yes illustrates only four for simplification of the drawing, the resistor RA, and RB connected in series between the output terminal of the example, a positive electrode side of the unit batteries E1 to E4, and a ground line GND with dividing circuit P1 to P4 which was formed by is connected, the common connection point between the resistors RA, RB in each voltage dividing circuit P1 to P4, is connected to the CPU1 for voltage detection. このCPU1では、単位電池E1の電圧V1と、単位電池E1とE2とを合わせた電圧V2と、単位電池E1〜E3を合わせた電圧V3と、単位電池E1〜E4を合わせた電圧V4とを、順次にサンプリングして検出すると共に、これらV1〜V をCPU1に備えたA/D変換器にてデジタル信号化し、次式に従って各単位電池E1〜E4の電圧VE1〜VE4を求める。 In the CPU 1, the voltage V1 of the unit battery E1, the unit battery E1 and the voltage V2 the combined E2, the voltage V3 of the combined unit cells E1 to E3, and a voltage V4 obtained by combining the unit cells E1 to E4, sequentially and detects by sampling, it V1~V 4 were digital signal by the a / D converter provided in the CPU 1, obtaining the voltage VE1~VE4 of the unit batteries E1~E4 according to the following equation. なお、下式においてkは分圧比で決まる比例常数である。 Incidentally, k in the formula is a proportionality constant determined by the voltage division ratio.
VE1=k・V1 VE1 = k · V1
VE2=k・(V2−V1) VE2 = k · (V2-V1)
VE3=k・(V3−V2) VE3 = k · (V3-V2)
VE4=k・(V4−V3) VE4 = k · (V4-V3)
【0004】 [0004]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
ところで、上述のシステムでは、最終的に検出したいものは、各単位電池E1〜E4の個々の電圧であるが、そのために複数の単位電池が直列した大電圧(V2〜V4)を検出し、それらの大電圧同士の差に基づいて単位電池の個々の電圧を算出している。 Incidentally, in the above system, ultimately those to be detected is the individual voltages of the unit batteries E1 to E4, and detecting the atmospheric voltage (V2 to V4) in which a plurality of unit cells in series in order that they and it calculates the individual voltages of the unit batteries on the basis of the difference between the large voltage between. このため、CPU1の分解能が十分に発揮されず、検出精度が低下するという問題が生じる。 Therefore, the resolution of CPU1 is not sufficiently exerted, is a problem that the detection accuracy decreases occurs. 即ち、CPU1におけるA/D変換器の分解能を例えば10ビットとした場合に、1つの単位電池の電圧を直にA/D変換器に取り込むときと、単位電池を4つ直列した大電圧をA/D変換器に取り込むときとを比較すると、前者では、1つの単位電池の電圧に2 10の分解能を割り当てることができるが、後者では、1つの単位電池の電圧に2 10 /4の分解能しか割り当てることができず、前者に比べて後者は分解能が低下し、従って、単位電池の個々の電圧の検出精度が低くなる。 That is, when the resolution, for example, 10-bit A / D converter in the CPU 1, and when incorporated into directly A / D converter the voltage of one unit cell, a large voltage four series unit cells A comparing the time to take in / D converter, in the former, but may be assigned a resolution of 2 10 to the voltage of one unit cell, the latter two to the voltage of one unit cell 10/4 only resolution can not be assigned, the latter resolution is lowered, therefore, the detection accuracy of the individual voltages of the unit cells is lower than the former.
【0005】 [0005]
また、上述のシステムでは、上記電圧V1〜V4を順次にサンプリングして検出しているので、例えば、最初に検出した単位電池の検出電圧に対し、最後に検出した単位電池の検出電圧には、検出タイミングのずれに伴う電圧変動分が含まれることとなり、単位電池同士の正確な電圧差を求められない。 Further, in the system described above, since the detection by sequentially sampling the voltage V1-V4, for example, to detect the voltage of the detected first unit cells, the detection voltage of the last detected unit cell, It will be included voltage change caused by the deviation of the detection timing, not required to correct the voltage difference between the unit cells. 一方、上記電圧V1〜V4を、一度に検出すべく、同時に複数の電圧検出を行うことが可能なCPU(A/Dコンバータ)を設けると、コストがかかってしまう。 On the other hand, the voltage V1-V4, to detect at once, simultaneously providing a plurality of voltage detection capable of performing CPU (A / D converter), it takes cost.
【0006】 [0006]
さらに、上述したシステムでは、各分圧回路P1〜P4に流れる放電電流i1〜i4により、各単位電池E1〜E4の容量にばらつきが発生する。 Furthermore, in the system described above, the discharge current i1~i4 flowing through voltage dividing circuits P1 to P4, variation occurs in the capacity of each unit battery E1 to E4. すなわち、図5に示すように、放電電流i1は単位電池E1にのみ流れるが、放電電流i2は単位電池E1,E2の双方に流れ、放電電流i3は単位電池E1,E2,E3に流れる…、という関係になっているため、グランドラインGNDにより近い単位電池E1,E2…には、より多くの電流が常時流れることになる。 That is, as shown in FIG. 5, but the discharge current i1 flows only in the unit cell E1, the discharge current i2 flows in both unit cell E1, E2, the discharge current i3 flows in the unit cell E1, E2, E3 ..., since that is a relationship that unit batteries E1, E2 ... the closer the ground line GND, will flow more current at all times. このため、グランドラインに近い単位電池ほど容量を低下させてしまうのである。 Therefore, it is the result so as to reduce the capacity as unit cells close to the ground line.
【0007】 [0007]
本発明は上記事情に鑑みてなされたもので、その目的は、組電池を構成する各単位電池の電圧を高い精度で検出することが可能な組電池の電圧検出回路を提供することにある。 The present invention has been made in view of the above circumstances, an object thereof is to provide a voltage detection circuit of the battery pack capable of detecting the voltage of each unit cell constituting the battery pack with high accuracy.
【0008】 [0008]
【課題を解決するための手段】 In order to solve the problems]
請求項1の発明に係る組電池の電圧検出回路は、複数の単位電池を直列接続してなる組電池に対応させて、複数のコンデンサを直列接続したコンデンサ群を設け、前記組電池と前記コンデンサ群との間で、互いに同じ順位に配置された各単位電池の両極と各コンデンサの両極とを複数の並列ラインで接続しかつそれら並列ラインにサンプルホールド用スイッチを設けることにより、前記各コンデンサの両極間に前記各単位電池の電圧をホールド可能な複数のサンプルホールド回路を構成し、 かつ前記各コンデンサの両極から引き出された複数の計測ラインを選択スイッチに接続し、前記選択スイッチを介して前記各コンデンサの両極間の電圧を電圧検出回路に印加されるように構成し、前記サンプルホールド用スイッチをオン状態から一斉に Voltage detection circuit of an assembled battery according to a first aspect of the invention, corresponding to the plurality of unit cells in the assembled battery formed by serially connected, provided the capacitor group connected in series a plurality of capacitors, the said battery pack capacitor between the groups, by providing the sample-hold switch to each other and both electrodes of each unit cell arranged in the same order as both poles of each capacitor were connected by a plurality of parallel lines and their parallel lines, wherein each capacitor the voltage of each unit cell constitutes a hold can be a plurality of sample-and-hold circuits between the two electrodes, and connect the to the selection switch a plurality of measurement lines drawn from both poles of the capacitors, the through the selection switch the voltage between both electrodes of each capacitor configured to be applied to the voltage detection circuit, all at once the sample-hold switch from the on state フさせることによって前記各単位電池の電圧を各コンデンサにホールドさせ、前記ホールドさせた電圧が前記コンデンサ群の所定部間の電圧として前記電圧検出回路に印加されるように前記選択スイッチのオン・オフを制御するスイッチ制御手段段とを備えたところに特徴を有する。 To hold a voltage of the respective unit batteries to each capacitor by off, on and off of the selection switch so that the voltage obtained by the hold is applied to the voltage detection circuit as the voltage between the predetermined portion of the capacitor group characterized in place and a switch control unit stage for controlling.
【0011】 [0011]
【発明の作用及び効果】 [Operation and effect of the invention]
<請求項1の発明> <Invention of claim 1>
請求項1の構成によれば、サンプルホールド用スイッチがオンすると、各単位電池の電圧が、各コンデンサの両極間の電圧と同じになる。 According to the first aspect, the sample-hold switch is turned on, the voltage of each unit cell is equal to the voltage between both electrodes of each capacitor. そして、全部のサンプルホールド用スイッチが一斉にオフして、各コンデンサの両極間に、各単位電池の同時刻における電圧がホールドされる。 Then, all of the sample-hold switch is turned off simultaneously, between the electrodes of the capacitors, the voltage at the time of each unit cell is held. この状態で、 前記コンデンサ群の所定部間の電圧が前記計測ラインを介して前記電圧検出手段に順次印加されるように切り換えられるため、コンデンサ群の所定部間の電圧が順次に電圧検出手段に取り込まれ、同時にホールドされた各単位電池の電圧が順次に検出される。 In this state, since the voltage between the predetermined portion of the capacitor group is switched to be sequentially applied to the voltage detection means via the measurement line, the voltage is sequentially voltage detection means between a predetermined portion of the capacitor group incorporated, the voltage of each unit cell, which is held at the same time are sequentially detected.
このようにして、本発明によれば、単位電池の同時刻の電圧を検出することが可能となり、従来問題となっていた、検出タイミングのずれに伴う電圧変動分が検出結果に含まれなくなり、高精度の電圧検出が可能となる。 In this way, according to the present invention, it is possible to detect a voltage at the same time the unit cell, has conventionally been a problem, a voltage variation due to the shift of the detection timing is not included in the detection result, highly accurate voltage detection is possible. しかも、本発明によれば、各単位電池に分圧回路を接続しなくて済むから、従来のように、分圧回路に流れる放電電流によって、各単位電池の容量にばらつきが発生することもない。 Moreover, according to the present invention, since it is not necessary to connect the voltage dividing circuit in the unit cell, as in the prior art, the discharge current flowing through the voltage divider circuit, is not generated variations in the capacity of each unit battery .
【0014】 [0014]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
以下、本発明を例えば電気自動車の動力用バッテリーシステムに適用した一実施形態について図1〜3を参照しつつ説明する。 Hereinafter, an embodiment of applying the present invention to a battery system for example of an electric vehicle power will be described with reference to FIGS.
【0015】 [0015]
本発明の組電池に相当するバッテリーBは、図1に示すように、例えば4つのの単位電池E1〜E4を直列接続してなる。 Battery B corresponds to the assembled battery of the present invention, as shown in FIG. 1, for example, the 4 horn unit cells E1~E4 connected in series. 本実施形態の電圧検出回路には、上記4つの単位電池E1〜E4に対応させて、4つのコンデンサC1〜C4を直列接続したコンデンサ群10が備えられ、このコンデンサ群10とバッテリーBとの間では、互いに同じ順位に配置された各コンデンサC1〜C4の両極と各単位電池E1〜E4の両極とが、並列ラインL1〜L5で接続されている。 The voltage detection circuit of this embodiment, corresponding to the four unit cells E1 to E4, provided four capacitors C1~C4 capacitor group 10 connected in series, between the capacitor group 10 and the battery B in the bipolar and both poles of each unit battery E1~E4 of the capacitors C1~C4 arranged in the same order with each other are connected in parallel lines L1 to L5.
【0016】 [0016]
具体的には、バッテリーBの正極は、並列ラインL4によって、コンデンサ群10の一端に接続されており、また、バッテリーBの負極は、並列ラインL5によってコンデンサ群10の他端に接続されている。 Specifically, the positive electrode of the battery B is by a parallel line L4, is connected to one end of the capacitor group 10, also, the negative electrode of the battery B is connected to the other end of the capacitor group 10 by a parallel line L5 . さらに、バッテリーBのうち隣り合った単位電池同士の共通接続点とコンデンサ群10のうち隣り合ったコンデンサ同士の共通接続点とが並列ラインL1〜L3で接続されている。 Further, a common connection point of the capacitor between the adjacent of the common connection point and the capacitor group 10 of the unit cells with each other adjacent one of the battery B is connected in parallel lines L1 to L3.
【0017】 [0017]
上記並列ラインL1〜L4には、それぞれサンプルホールド用スイッチSW1〜SW4が設けられている。 The aforementioned parallel lines L1 to L4, respectively sample-hold switch SW1~SW4 are provided. ここで、図1で簡略記号で示した各サンプルホールド用スイッチSW1〜SW4は、図2に具体的な構成が示されており、いずれもNチャンネルの接合型FET1で構成されている。 Wherein each sample-hold switch SW1~SW4 indicated by the mnemonic in FIG. 1 is a specific configuration is shown in Figure 2, both configured in junction type FET1 N-channel. また、隣り合った並列ラインの間には、それぞれトランジスタT1のエミッタ・コレクタが接続されており、これら各トランジスタT1のコレクタに各FET1のゲートが接続されている。 Between the parallel lines adjacent each is connected to the emitter and the collector of the transistor T1, the gate of each FET1 to the collector of each transistor T1 is connected. さらに、各トランジスタT1のバイアス回路は、ひとまとめにされて1つのトランジスタT2に接続され、このトランジスタT2が次述するCPU30(スイッチ制御手段に相当する)から2値信号を受けてオンオフされることで、全部のトランジスタT1が一斉にオンオフする。 Further, the bias circuit of each transistor T1 is taken together are connected to one transistor T2, that this transistor T2 is turned on and off by receiving a binary signal from the CPU30 will be described next (corresponding to the switch control means) , all of the transistor T1 is turned on and off in unison. これにより、後の動作説明で詳説するように全部のFET1が一斉にオンオフされる。 Accordingly, FET1 all as detailed in the description of the operation of the later is turned on and off simultaneously.
【0018】 [0018]
本実施形態の電圧検出回路には、電圧検出手段として、A/Dコンバータを内蔵したCPU30が備えられている。 The voltage detection circuit of this embodiment, as the voltage detecting means, CPU 30 with built-in A / D converter is provided. このCPU30には、4つのA/D変換用の入力端子A/D1〜A/D4と、1つのGND端子とが備えられ、これら各端子に各コンデンサC1〜C4の両極から引き出された計測ラインが接続されている。 The CPU 30, 4 one input terminal A / D1~A / D4 of the A / D conversion, one GND terminal and is provided, the measurement line drawn from both poles of the capacitors C1~C4 to respective terminals There has been connected.
【0019】 [0019]
具体的には、図1に示すように、前記した並列ラインL5を延長した計測ラインL15がCPU30のGND端子に接続され、前記した並列ラインL1〜L4を延長した計測ラインL11〜L14が、CPU30の入力端子A/D1〜A/D4にそれぞれ接続されている。 Specifically, as shown in FIG. 1, the measurement line L15 that extends parallel line L5 described above are connected to the GND terminal of the CPU 30, the measurement line L11~L14 that extend parallel lines L1~L4 described above, CPU 30 They are respectively connected to the input terminal a / D1~A / D4 of.
【0020】 [0020]
上記計測ラインのうちL12〜L14には、それぞれ選択スイッチSW12〜SW14が設けられている。 The L12~L14 of the measurement line, respectively selection switch SW12~SW14 is provided. ここで、選択スイッチSW12〜SW14は、図2に具体的な構成が示されており、いずれもPチャンネルのMOS型FET2で構成され、これらFET2のバイアス回路の途中に設けた各トランジスタT3が、前記CPU30から2値信号を受けてオンオフされ、もって各FET2が別々にオンオフされる。 The selection switch SW12~SW14 has been shown the specific configuration in FIG. 2, both formed of a MOS type FET2 of P-channel, each transistor T3 provided in the middle of the bias circuit of FET2, is off by receiving the binary signal from the CPU 30, the FET2 is turned on and off separately with.
【0021】 [0021]
図1に示すように、計測ラインのうちL11〜13は、L15に対して、計測ラインL16〜L18によって接続されており、これら計測ラインL16〜L18には、選択スイッチSW21〜SW23が設けられている。 As shown in FIG. 1, L11~13 of measurement lines for L15, it is connected by measuring lines L16~L18, These measurement line L16~L18, the selection switch SW21~SW23 provided there. ここで、選択スイッチSW21〜SW23は、図2に具体的な構成が示されており、いずれもNチャンネルのMOS型FET3で構成され、これらFET3のゲートが、図示しないバイアス回路に接続され、このバイアス回路に備えた例えばトランジスタがCPU30から2値信号を受けてオンオフされ、もってFET3が別々にオンオフされる。 The selection switch SW21~SW23 is specific configuration is shown in Figure 2, both formed of a MOS-type FET3 the N channel gate of FET3 is connected to a bias circuit (not shown), this for example a transistor provided in the bias circuit is turned on and off by receiving the binary signals from the CPU 30, it has been FET3 is turned on and off separately.
【0022】 [0022]
CPU30は、図3のタイムチャートに示すように、所定周期で上記した各サンプルホールド用スイッチ及び選択スイッチをオンオフ制御しており、以下、この図3を参照しつつ本実施形態の電圧検出回路の動作について説明する。 CPU30, as shown in the time chart of FIG. 3, and on-off controlling each sample-hold switch and the selection switch as described above at a predetermined period, or less, of the voltage detection circuit of the present embodiment with reference to FIG. 3 the operation will be described.
【0023】 [0023]
まず、電圧検出回路を起動すると、全てのスイッチがオフされた状態となる。 First, when starting the voltage detection circuit, a state where all switches are turned off. この状態から、まず最初に、並列ラインL1〜L4に設けたSW1〜SW4が一斉にオンして、各単位電池E1〜E4及び各コンデンサC1〜C4の両極同士が導通接続される。 From this state, first, SW1 to SW4 provided in parallel lines L1~L4 is turned on simultaneously, both electrodes of the respective unit cells E1~E4 and capacitors C1~C4 are electrically connected. 具体的には、CPU30によってトランジスタT2(図2参照)がオンされて、単位電池E1〜E4毎に配した全部のトランジスタT1にバイアス電流が流れ、それらトランジスタT1がオンする。 Specifically, CPU 30 by the transistor T2 (see FIG. 2) is turned on, the bias current flows through the transistor T1 of all that arranged in each unit cell E1 to E4, which transistor T1 is turned on. すると、各FET1のゲートの電位が抵抗R1によってソースの電位まで持ち上げられて、ゲート・ソース電圧VGSが0Vとなり、全部のFET1がオンして、並列ラインL1〜L4が導通状態となり、もって上記したように、各単位電池E1〜E4及び各コンデンサC1〜C4の両極同士が導通接続される。 Then, the FET1 lifted to the potential of the source by the potential resistors R1 of the gate of the gate-source voltage VGS is 0V and all of FET1 is turned on, a parallel line L1~L4 becomes conductive, have been described above as such, both electrodes of the respective unit cells E1~E4 and capacitors C1~C4 are electrically connected.
【0024】 [0024]
すると、コンデンサC1〜C4に電荷が流れ込み、対応した単位電池と同じ電圧が各コンデンサの両極間に発生する。 Then, electric charge in the capacitor C1~C4 flows, the same voltage as the corresponding unit cell is generated between both electrodes of the capacitors. また、このとき、コンデンサ群10とCPU30とを繋ぐ計測ラインL12〜L14上の選択スイッチSW12〜SW14はオフしているから、単位電池を2つ以上繋げた大電圧が、CPU30の入力端子(A/D2〜A/D4)に印加されることはない。 At this time, the selection switch SW12~SW14 on measurement line L12~L14 for connecting the capacitor group 10 and the CPU 30 is turned off, a large voltage obtained by connecting the unit cells of two or more, CPU 30 of the input terminal (A / D2~A / D4) will not be applied to.
【0025】 [0025]
なお、本実施形態の電圧検出回路には、図2に示すように、計測ラインL11〜L14の途中に安全を期して、リミッタ回路H1が設けられており、何らかの原因で、選択スイッチSW12〜SW14がオンしていても、CPU30には一定以上の電圧がかからない。 Incidentally, the voltage detection circuit of the present embodiment, as shown in FIG. 2, for the sake of safety in the middle of the measurement line L11 to L14, the limiter circuit H1 is provided, for some reason, the selection switch SW12~SW14 but even if turned on, not to apply certain level of voltage in the CPU30.
【0026】 [0026]
次いで、SW1〜SW4が一斉にオフされる(ホールド期間)。 Then, SW1 to SW4 are simultaneously turned off (hold period). 具体的には、CPU30からの2値信号が例えばLレベルになり、トランジスタT2がオフして、全トランジスタT1がオフする。 More specifically, it becomes a binary signal is, for example L level from CPU 30, the transistor T2 is turned off, all the transistors T1 are turned off. すると、各FET1のゲートとソース間に、単位電池の電圧が印加された状態となり、FET1が一斉にオフする。 Then, between each FET1 gate and the source of a state in which the voltage of the unit cells is applied, FET1 is turned off in unison.
【0027】 [0027]
これにより、各単位電池E1〜E4と各コンデンサC1〜C4とが一斉に非導通状態となり、コンデンサC1〜C4に流れ込んだ電荷は、どこにも逃げる経路がなくなり、同時刻(SW1〜SW4をオフした瞬間の時刻。図3の時刻t1参照)の各単位電池E1〜E4の電圧が、各コンデンサC1〜C4にホールドされる。 Accordingly, it is the unit batteries E1~E4 each capacitor C1~C4 and is non-conducting state simultaneously, the charge flowing into the capacitor C1~C4 Where the eliminated even escape routes, turns off the same time (SW1 to SW4 moment of time. voltage of each unit cell E1~E4 reference time t1 in FIG. 3) is held in each capacitor C1 -C4.
【0028】 [0028]
次いで、コンデンサ群10のうち低電位側のコンデンサC1から、順次に、その両極間の電位をCPU30に取り込む動作に移行する。 Then, from the low potential side of the capacitor C1 of the capacitor group 10 sequentially shifts the operation to fetch a potential between the two electrodes to CPU 30. 具体的には、まず最初に、CPU30のGND端子と入力端子A/D1との間の電圧が取り込まれる。 More specifically, first, the voltage between the input terminal A / D1 and the GND terminal of the CPU30 captured. ここで、GND端子と入力端子A/D1とに両極を接続されたコンデンサC1には、単位電池E1の電圧がホールドされているから、その単位電池E1の電圧がCPU30に取り込まれることとなり、これがデジタルデータ化されかつ所定のソフト処理を経て電圧値として検出される。 Here, the capacitor C1 connected to both electrodes to the GND terminal and the input terminal A / D1, since the voltage of the unit battery E1 is held, becomes the voltage of the unit cell E1 is incorporated in CPU 30, which is digital data and through a predetermined software processing is detected as a voltage value.
【0029】 [0029]
このデータの取り込みが終了すると(図3の時刻t2参照)、スイッチSW21(図2のFET3)がオンして、計測ラインL11とL15とが導通接続される。 When this data capture is completed (see time t2 in FIG. 3), the switch SW21 (FET 3 in Fig. 2) is turned on, the measurement line L11 and L15 are electrically connected. これにより、コンデンサC1に蓄えられた電荷が放電されると共に、コンデンサC2の負極がCPU30のGND端子に導通接続される。 Thus, the charge stored in the capacitor C1 is discharged, the negative electrode of the capacitor C2 is electrically connected to the GND terminal of the CPU 30.
次いで、スイッチSW12(図2のFET2)がオンして、コンデンサC2の正極が入力端子A/D2に導通接続される。 Then, the switch SW12 (FET2 in Figure 2) is turned on, the positive electrode of the capacitor C2 is electrically connected to the input terminal A / D2. そして、この状態で、GND端子と入力端子A/D2との間の電圧が、CPU30に取り込まれてデジタルデータ化される。 In this state, the voltage between the GND terminal and the input terminal A / D2 is digital data is taken into the CPU 30. これにより、コンデンサC2の両極間にホールドされた単位電池E2の電圧が検出される。 Accordingly, the voltage of the unit cell E2, which is held between both electrodes of the capacitor C2 is detected.
【0030】 [0030]
このデータの取り込みが終了すると(図3の時刻t3参照)、スイッチSW21、SW12がオフすると共に、SW22(図2のFET3)がオンする。 When the import of the data is completed (see time t3 in FIG. 3), the switches SW21, SW12 are turned off, SW22 (FET 3 in Fig. 2) is turned on. これにより、コンデンサC2の正極がGNDに導通接続されて、コンデンサC1に蓄えられた電荷が放電されると共に、コンデンサC3の負極がGND端子に導通接続される。 Thus, the positive electrode of the capacitor C2 is electrically connected to the GND, together with the charge stored in the capacitor C1 is discharged, the negative electrode of the capacitor C3 is electrically connected to the GND terminal. 次いで、スイッチSW13(図2のFET2)がオンして、コンデンサC の正極が入力端子A/D3に導通接続され、この状態で、GND端子と入力端子A/D3との間に印加された電圧が、CPU30に取り込まれる。 Then, the switch SW13 (FET2 in Figure 2) is turned on, the positive electrode of the capacitor C 3 is electrically connected to the input terminal A / D3, in this state, is applied between the GND terminal and the input terminal A / D3 voltage is incorporated into the CPU30. これにより、コンデンサC3の両極間にホールドされた単位電池E3の電圧が検出される。 Accordingly, the voltage of the unit cell E3, which is held between both electrodes of the capacitor C3 is detected.
【0031】 [0031]
以下、同様にして、コンデンサC4の両極間の電圧がCPU30に取り込まれ、もって、コンデンサC4の両極間にホールドされた単位電池E4の電圧が検出される。 In the same manner, the voltage between both electrodes of the capacitor C4 is fetched into the CPU 30, with it, the voltage of the unit cell E4 which is held between both electrodes of the capacitor C4 is detected.
このようにして、各コンデンサC1〜C4の両極間にホールドされた各単位電池E1〜E4の同時刻における電圧が、順次にCPU30に取り込まれて検出され、例えば、各単位電池の電圧の差が所定の電圧差に収まっているか否かが監視される。 In this way, the voltage at the time of each unit cell E1~E4 which is held between the two electrodes of each capacitor C1~C4 is detected is sequentially taken into the CPU 30, for example, the difference between the voltage of each unit cell whether within a predetermined voltage difference it is monitored.
【0032】 [0032]
このように本実施形態によれば、複数の単位電池E1〜E4の同時刻の電圧を検出することが可能となり、従来問題となっていた、検出タイミングのずれに伴う電圧変動分が検出結果に含まれなくなり、高精度の電圧検出が可能となる。 According to this embodiment, it is possible to detect a voltage at the same time a plurality of unit batteries E1 to E4, has conventionally been a problem, the voltage change caused by the deviation of the detection timing detection result including longer, it is possible to highly accurate voltage detection. しかも、同時に複数の電圧検出を行えるCPUを備えて同じ課題を解決した電圧検出回路に比べて、低コストで製造することができる。 Moreover, it is possible to include a CPU capable of performing multiple simultaneous voltage detection than the voltage detecting circuit which can solve the same problem, produced at low cost.
【0033】 [0033]
また、CPU30に、各単位電池E1〜E4の一つ当たりの電圧を取り込む構成としたから、CPU30の分解能(例えば、10ビット)を、単位電池1つの電圧に割り当てることができ、従来のように、複数の単位電池が直列した大電圧に分解能の全てを割り当てたものに比べて、検出精度が向上する。 Further, the CPU 30, from the configured to capture voltage per one of the unit batteries E1 to E4, the resolution of the CPU 30 (e.g., 10 bits), can be assigned to the unit cell one voltage, as in the prior art , as compared with a plurality of unit cells assigned to all resolution large voltage in series, the detection accuracy is improved.
【0034】 [0034]
さらに、本発明によれば、各単位電池E1〜E4に分圧回路を接続しなくて済むから、従来のように、分圧回路に流れる放電電流によって、各単位電池の容量にばらつきが発生することもない。 Furthermore, according to the present invention, since it is not necessary to connect the unit batteries E1~E4 binary pressure circuit, as in the prior art, the discharge current flowing through the voltage divider circuit, variation occurs in the capacity of each unit battery nor. その上、コンデンサは、分圧回路に必要な抵抗に比べて温度の影響を受けにくく、この点においても、検出精度の向上が図られる。 Moreover, the capacitor less susceptible to temperature as compared with the resistance required to the voltage divider circuit, also in this respect, improvement of detection accuracy can be achieved.
【0035】 [0035]
<他の実施形態> <Other embodiments>
本発明は、前記実施形態に限定されるものではなく、例えば、以下に説明するような実施形態も本発明の技術的範囲に含まれ、さらに、下記以外にも要旨を逸脱しない範囲内で種々変更して実施することができる。 The present invention, the present invention is not limited to the embodiments, for example, embodiments as described below also lie within the technical range of the present invention, further, various ways within a scope not departing from the gist other than below it can be practiced with modification.
【0036】 [0036]
(1)前記実施形態では、CPU30に備えた複数の入力端子A/D1〜A/D4に、計測ラインL11〜L14が予め接続されていて、これら計測ラインL11〜L14を選択スイッチSW12〜SW14で導通状態と非導通状態とに切り換える構成であったが、例えば、図4に示すように、各コンデンサC1〜C4の正極から引き出した計測ラインL42を、CPU30に備えた1つの入力端子A/D1に選択スイッチSW24にて選択的に導通接続すると共に、各コンデンサの負極から引き出した計測ラインL43を、1つのGND端子に選択スイッチSW25にて選択的に導通接続する構成としてもよい。 (1) In the above embodiment, a plurality of input terminals A / D1~A / D4 with the CPU 30, be pre-connected to the measurement line L11 to L14, these measurement lines L11 to L14 in the selection switch SW12~SW14 conducting state and there is constructed a constitution for switching to the non-conducting state, for example, as shown in FIG. 4, the measurement line L42 drawn out from the positive electrode of the capacitors C1 -C4, 1 an input terminal a / D1 with the CPU30 to thereby selectively conductively connected at the selection switch SW24, the measurement line L43 drawn out from the negative electrode of each capacitor may be selectively turned connecting structure at selected switch SW25 to one GND terminal.
【0037】 [0037]
(2)前記実施形態のMOS型FET2,3を、例えば、フォトFETに替えた構成としてもよい。 (2) a MOS FET2,3 of the embodiment, for example, may be configured to place the photo FET. ここでフォトFETは、ゲート部に発光及び受光の両ダイオードを配してパッケージ化したものである。 Here the photo FET is obtained by packaging by disposing both diodes of the light emitting and light receiving gate portion. 従って、フォトFETを用いれば、そのゲートは、ソース、ドレインと絶縁状態をなすから、ゲート電流による影響を受けずに、より正確な電圧検出を行うことができる。 Therefore, the use of the photo FET, its gate, since forms source, drain and insulated, without being affected by the gate current, it is possible to perform a more accurate voltage detection.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】本発明の一実施形態に係るバッテリーの電圧検出回路の簡略回路図【図2】その電圧検出回路のスイッチの構成を示した詳細回路図【図3】CPUによるスイッチにオンオフタイミングを示したタイムチャート【図4】変形例を示す回路図【図5】従来の電圧検出回路の回路図【符号の説明】 The on-off timing switch according detailed circuit diagram Figure 3 CPU shown a simplified circuit diagram Figure 2 switches the voltage detection circuitry of the voltage detection circuit of a battery according to an embodiment of the invention; FIG circuit diagram of the time chart Figure 4 is a circuit diagram showing a modification [5] conventional voltage detection circuit shown eXPLANATION oF REFERENCE nUMERALS
10…コンデンサ群30…CPU(電圧検出手段、スイッチ制御手段) 10 ... capacitor group 30 ... CPU (voltage detection means, switch control means)
B…バッテリー(組電池) B ... battery (battery pack)
C1〜C4…コンデンサE1〜E4…単位電池L1〜L5…並列ラインL11〜18、L42,L43…計測ラインSW1〜SW4…サンプルホールド用スイッチSW12〜SW14,SW21〜SW25…選択スイッチ C1~C4 ... capacitor E1~E4 ... unit cell L1~L5 ... parallel line L11~18, L42, L43 ... measurement line SW1~SW4 ... sample-hold switch SW12~SW14, SW21~SW25 ... selection switch

Claims (1)

  1. 複数の単位電池を直列接続してなる組電池に対応させて、複数のコンデンサを直列接続したコンデンサ群を設け、 A plurality of unit cells so as to correspond to the assembled battery formed by serially connected, provided the capacitor group connected in series a plurality of capacitors,
    前記組電池と前記コンデンサ群との間で、互いに同じ順位に配置された各単位電池の両極と各コンデンサの両極とを複数の並列ラインで接続しかつそれら並列ラインにサンプルホールド用スイッチを設けることにより、前記各コンデンサの両極間に前記各単位電池の電圧をホールド可能な複数のサンプルホールド回路を構成し、 Between the capacitor unit and the battery pack, by providing the sample-hold switch to be and their parallel lines connecting the two poles and each capacitor poles of the unit batteries which are located in the same rank from each other by a plurality of parallel lines Accordingly, the voltage of each unit cell constitutes a hold can be a plurality of sample-and-hold circuits between the two electrodes of each capacitor,
    かつ前記各コンデンサの両極から引き出された複数の計測ラインを選択スイッチに接続し、前記選択スイッチを介して前記各コンデンサの両極間の電圧を電圧検出回路に印加されるように構成し、 And wherein connected to a plurality of selected measurement line switch drawn from both poles of the capacitors, configured to be applied a voltage between both electrodes of each capacitor through the selection switch to the voltage detection circuit,
    前記サンプルホールド用スイッチをオン状態から一斉にオフさせることによって前記各単位電池の電圧を各コンデンサにホールドさせ、前記ホールドさせた電圧が前記コンデンサ群の所定部間の電圧として前記電圧検出回路に印加されるように前記選択スイッチのオン・オフを制御するスイッチ制御手段を備えたことを特徴とする組電池の電圧検出回路。 Applied to the voltage of the unit cell is held in the capacitor, the voltage detection circuit voltage obtained by the hold as the voltage between the predetermined portion of the capacitor group by turning off all at once the sample-hold switch from the on state voltage detection circuit of an assembled battery characterized by comprising a switch control means for controlling the on-off of the selection switch to be.
JP23078699A 1999-08-17 1999-08-17 Voltage detection circuit of the battery pack Active JP4206574B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23078699A JP4206574B2 (en) 1999-08-17 1999-08-17 Voltage detection circuit of the battery pack

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23078699A JP4206574B2 (en) 1999-08-17 1999-08-17 Voltage detection circuit of the battery pack

Publications (2)

Publication Number Publication Date
JP2001056350A true JP2001056350A (en) 2001-02-27
JP4206574B2 true JP4206574B2 (en) 2009-01-14

Family

ID=16913257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23078699A Active JP4206574B2 (en) 1999-08-17 1999-08-17 Voltage detection circuit of the battery pack

Country Status (1)

Country Link
JP (1) JP4206574B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102540087A (en) * 2010-11-25 2012-07-04 株式会社电装 Voltage measurement apparatus
CN102539881A (en) * 2010-12-03 2012-07-04 株式会社电装 Voltage detection device for assembled battery

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4540029B2 (en) * 2001-03-23 2010-09-08 株式会社Gsユアサ Voltage detecting method and the voltage detection device
JP3696124B2 (en) 2001-05-17 2005-09-14 三洋電機株式会社 Voltage detection circuit of the battery pack
JP4509852B2 (en) * 2005-05-17 2010-07-21 株式会社東芝 Battery assembly and its voltage detector
JP2008175597A (en) * 2007-01-16 2008-07-31 Gs Yuasa Corporation:Kk Voltage detection device for battery pack
JP5169491B2 (en) 2008-05-28 2013-03-27 株式会社Gsユアサ Breaking detection method of the assembled battery monitoring device and a battery pack wire
CN102216795B (en) * 2008-09-18 2015-07-15 株式会社Lg化学 Apparatus and method for monitoring voltages of cells of battery pack
JP6229248B2 (en) 2011-06-03 2017-11-15 株式会社Gsユアサ Cell monitoring device of the power storage module, and a disconnection detection method
JP5991299B2 (en) 2012-12-26 2016-09-14 株式会社デンソー Voltage detection device of the battery pack

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102540087A (en) * 2010-11-25 2012-07-04 株式会社电装 Voltage measurement apparatus
CN102539881A (en) * 2010-12-03 2012-07-04 株式会社电装 Voltage detection device for assembled battery
CN102539881B (en) * 2010-12-03 2014-11-19 株式会社电装 Voltage detection device for assembled battery

Also Published As

Publication number Publication date Type
JP2001056350A (en) 2001-02-27 application

Similar Documents

Publication Publication Date Title
US7102378B2 (en) Testing apparatus and method for thin film transistor display array
US6639409B2 (en) Battery voltage measurement device
US6639408B2 (en) Battery voltage measurement device
US20060012336A1 (en) Battery-pack voltage detection apparatus
US20030189419A1 (en) Multiplex voltage measurement apparatus
US20030006749A1 (en) Current sensing and measurement in a pulse width modulated power amplifier
US6362627B1 (en) Voltage measuring instrument with flying capacitor
US20080309317A1 (en) Integrated Battery Voltage Sensor with High Voltage Isolation, a Battery Voltage Sensing System and Methods Therefor
JPH07128414A (en) Battery test device, and electric power device having the test device built in
US20080054907A1 (en) Assembled battery total voltage detection and leak detection apparatus
US6437538B1 (en) Battery voltage measurement apparatus
JPH11248755A (en) Stacked voltage measuring apparatus
US5612696A (en) Digital-to-analog converter of current segmentation
US20050189949A1 (en) Flying capacitor type battery voltage detector
US6646442B2 (en) Voltage detection device for a battery package
US20130300371A1 (en) Cell balance configuration for pin count reduction
US4017687A (en) Device for minimizing interchannel crosstalk in high rate commutator multiplexers
US20040096061A1 (en) Electrostatic capacitance sensor and fingerprint collator comprising it
US20050194931A1 (en) Circuit system for a battery electronic control unit
US7088394B2 (en) Charge mode active pixel sensor read-out circuit
US20010003356A1 (en) Electromagnetic radiation detection device
JP2002286766A (en) Voltage detection method and voltage detection device
US20050083015A1 (en) Voltage detector of battery assembly
JP2002184470A (en) Charge/discharge current measuring apparatus
US20070024270A1 (en) Method of voltage measurement and apparatus for same

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20051213

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20060112

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060602

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20070110

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080710

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080715

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080904

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080924

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20081007

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111031

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111031

Year of fee payment: 3

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111031

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111031

Year of fee payment: 3

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111031

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111031

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121031

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121031

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131031

Year of fee payment: 5