JP4161913B2 - 正弦波乗算回路及び正弦波乗算方法 - Google Patents
正弦波乗算回路及び正弦波乗算方法 Download PDFInfo
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- JP4161913B2 JP4161913B2 JP2004038066A JP2004038066A JP4161913B2 JP 4161913 B2 JP4161913 B2 JP 4161913B2 JP 2004038066 A JP2004038066 A JP 2004038066A JP 2004038066 A JP2004038066 A JP 2004038066A JP 4161913 B2 JP4161913 B2 JP 4161913B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1466—Passive mixer arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1483—Balanced arrangements with transistors comprising components for selecting a particular frequency component of the output
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0041—Functional aspects of demodulators
- H03D2200/0086—Reduction or prevention of harmonic frequencies
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- General Physics & Mathematics (AREA)
- Analogue/Digital Conversion (AREA)
Description
次に、加重回路10及び極性切換回路13の具体的な回路例について説明する。図14は、2つの加算係数を有し、k=4、即ち8倍のサンプリングで動作する回路例(回路例1)を示す回路図である。
図16に、k=8、即ち16倍サンプリングの加重回路10及び極性切換回路13の具体的な回路例(回路例2)を示す。図17は、回路例2の場合におけるスイッチの制御及び加重係数を示す図である。極性を切り換えるスイッチSWpとSWpxは回路例1と同じである。本回路例では、加重係数を4種類切り換えるために、3種類のスイッチSWma,SWmb,SWmcxを使っている。
図18に、等価的に入力スイッチ機能を有するバッファ回路により実現した回路例(回路例3)を示す。
図20は、加重回路10及び極性切換回路13として回路例2(図16)を用いて、非常に振幅精度の良い正弦波信号を発生する正弦波発生回路を実現した構成例を示す回路図である。本構成例に係る正弦波発生回路では、回路例2に係る正弦波乗算回路において、入力in+,in−として振幅制御電圧Vcを与えるようにし、当該振幅制御電圧Vcにより出力の振幅を制御することで、出力の振幅を高精度で設定することが出来る。パルス制御回路14には、乗算する正弦波信号の周波数fの8倍のクロックが入力される。パルス制御回路14は、周波数fの8倍のクロックに基づいて、図17に示すスイッチの制御パルスを生成する。振幅制御電圧Vcに任意の信号を加えると、極めて精度の良い振幅変調をすることも出来る。
図21は、入力の複素信号に周波数fの複素信号を乗算する応用例2に係る正弦波乗算回路の構成例を示すブロック図である。
Claims (3)
- 印加される差動入力信号に対して、固有値を持つn個(nは2以上の整数)の加重係数を乗じて差動信号を出力する加重手段と、
前記加重手段の差動出力端子に接続され、その2つの信号線を入れ替えることにより、差動の同相出力と差動の逆相出力を得る極性切換手段と、
前記n個の加重係数及び前記極性を、1周期の1/2k(kは整数で、2kが8以上、4n以下)のサンプリング周期毎に切り換える制御手段とを備え、
前記加重手段および前記極性切換手段は、前記加重係数を決める抵抗網と、前記抵抗網の入出力間における伝達利得を切り替えることによって前記加重係数とするスイッチ回路とを有し、
前記加重手段は、前記n個の加重係数の内、少なくとも1個の加重係数を半周期の前半に2回、後半に2回の計4回使用し、残りの加重係数を半周期の前半に1回、後半に1回の計2回使用し、
前記極性切換手段は、半周期の前半に同相出力を出力し、後半に反転出力を出力する
ことを特徴とする正弦波乗算回路。 - 前記加重係数と前記極性の積は、正弦波のサンプリング周期の瞬時値に比例するように設定されている
ことを特徴とする請求項1記載の正弦波乗算回路。 - 印加される差動入力信号に対して、固有値を持つn個(nは2以上の整数)の加重係数を乗じて差動信号を出力する第1ステップと、
前記第1ステップでの差動出力の2つの信号線を入れ替えることにより、差動の同相出力と差動の逆相出力を得る第2ステップと、
前記n個の加重係数及び前記極性を、1周期の1/2k(kは整数で、2kが8以上、4n以下)のサンプリング周期毎に切り換える第3ステップとを有し、
前記第1ステップ及び前記2ステップでは、前記加重係数を抵抗網によって決めるとともに、前記抵抗網の入出力間における伝達利得をスイッチ回路により切り替えることによって前記加重係数とし、
前記第1ステップでは、前記n個の加重係数の内、少なくとも1個の加重係数を半周期の前半に2回、後半に2回の計4回使用し、残りの加重係数を半周期の前半に1回、後半に1回の計2回使用し、
前記第2ステップでは、半周期の前半に同相出力を出力し、後半に反転出力を出力する
ことを特徴とする正弦波乗算方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004038066A JP4161913B2 (ja) | 2004-02-16 | 2004-02-16 | 正弦波乗算回路及び正弦波乗算方法 |
US11/049,784 US7631030B2 (en) | 2004-02-16 | 2005-02-03 | Sine wave multiplication circuit and sine wave multiplication method |
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JP2004038066A JP4161913B2 (ja) | 2004-02-16 | 2004-02-16 | 正弦波乗算回路及び正弦波乗算方法 |
Publications (2)
Publication Number | Publication Date |
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JP2005228207A JP2005228207A (ja) | 2005-08-25 |
JP4161913B2 true JP4161913B2 (ja) | 2008-10-08 |
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JP2004038066A Expired - Fee Related JP4161913B2 (ja) | 2004-02-16 | 2004-02-16 | 正弦波乗算回路及び正弦波乗算方法 |
Country Status (2)
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US (1) | US7631030B2 (ja) |
JP (1) | JP4161913B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004336152A (ja) * | 2003-04-30 | 2004-11-25 | Sony Corp | 正弦波発生回路 |
US8442470B1 (en) * | 2009-05-14 | 2013-05-14 | Marvell International Ltd. | Harmonic-reject FTI filter |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US3935439A (en) * | 1974-07-12 | 1976-01-27 | Texas Instruments Incorporated | Variable tap weight convolution filter |
US4084256A (en) * | 1976-12-16 | 1978-04-11 | General Electric Company | Sampled data analog multiplier apparatus |
US4156284A (en) * | 1977-11-21 | 1979-05-22 | General Electric Company | Signal processing apparatus |
IT1115581B (it) * | 1978-08-25 | 1986-02-03 | Cselt Centro Studi Lab Telecom | Circuito di comando e di controllo dei coefficienti di un equalizzatore adattativo di tipo analogico |
US4727333A (en) * | 1986-06-30 | 1988-02-23 | Rca Corporation | Circuitry for multiplying a PCM signal by a sinusoid |
JPH0814829B2 (ja) | 1986-12-27 | 1996-02-14 | ソニー株式会社 | 乗算回路 |
JPH01204510A (ja) | 1988-02-10 | 1989-08-17 | Fujitsu Ten Ltd | 振幅変調回路 |
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2004
- 2004-02-16 JP JP2004038066A patent/JP4161913B2/ja not_active Expired - Fee Related
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2005
- 2005-02-03 US US11/049,784 patent/US7631030B2/en not_active Expired - Fee Related
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US7631030B2 (en) | 2009-12-08 |
US20050195014A1 (en) | 2005-09-08 |
JP2005228207A (ja) | 2005-08-25 |
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