JP4150373B2 - Power switch IC and power switch control method - Google Patents

Power switch IC and power switch control method Download PDF

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JP4150373B2
JP4150373B2 JP2004371520A JP2004371520A JP4150373B2 JP 4150373 B2 JP4150373 B2 JP 4150373B2 JP 2004371520 A JP2004371520 A JP 2004371520A JP 2004371520 A JP2004371520 A JP 2004371520A JP 4150373 B2 JP4150373 B2 JP 4150373B2
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power
power source
inverter circuit
output
power supply
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JP2006180226A5 (en
JP2006180226A (en
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慶二 福村
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株式会社リコー
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Description

The present invention relates to a power switch IC and a power switch control method , and more particularly to a power switch IC and a power switch control method for detecting an abnormality in a power source of a device to which multiple power supplies are supplied.

The current notebook personal computer is generally equipped with a PC card slot. A desktop PC can also handle PC cards by adding an expansion board. “Express Card (registered trademark)” has been established by an industry group as a next-generation card to replace this PC card, and a personal computer equipped with this Express Card will be shipped from the end of 2004.
Three card power supplies of 3.3V, 3.3VAUX (auxiliary power input), and 1.5V are supplied to the card slot for the Express Card. As seen from the card slot, a power switch IC is arranged immediately upstream of the three power sources. A function required for the power switch IC for the Express Card is to set the reset output to the L level when any one of the 3.3V, 3.3VAUX, and 1.5V power input is turned off.

In addition, when the power input of 3.3VAUX is turned off, all power outputs are turned off. When the power input of 3.3V is turned off, power outputs of 3.3V and 1.5V are turned off. Even when the power input of 1.5V is turned off, the power output of 3.3V and 1.5V is turned off as a necessary function.
In order to realize these functions, a power source for operating the power switch IC is provided in addition to the power input of 3.3V, 3.3VAUX, and 1.5V.

FIG. 4 is a block diagram of a conventional power switch IC.
SW1, SW2, and SW3 are Nch power MOS transistors, and have a function of a switch that connects IN1, IN2, and IN3 to OUT1, OUT2, and OUT3, respectively.
The gates of SW1, SW2, and SW3 are connected to a gate control circuit, and the drains of SW1, SW2, and SW3 are connected to an abnormality detection circuit. The output VDET of the abnormality detection circuit is connected to the gate control circuit and to the timing control circuit. A VDET signal and a reset signal are input to the timing control circuit, and an output of the timing control circuit is input to the inverter circuit INV0.
The number of enable inputs in the figure is one, but a plurality of enable inputs may be used to make a combination of whether or not to output OUT1, OUT2, and OUT3.
The gate control circuit controls which Nch power MOS transistor is turned on in response to the enable input and the output (VDET) of the abnormality detection circuit.
The gate potential of the Nch power MOS transistor is controlled in order to set the rise time and fall time of OUT1, 2, 3 to desired specifications.
The abnormality detection circuit monitors whether OUT1, 2, and 3 are at a potential within the standard.
The timing control circuit changes the reset output according to the change in the reset input, and changes the reset output according to the change in VDET.
The gate control circuit, timing control circuit, abnormality detection circuit, and INV0 operate by receiving power supply from a Vcc terminal (also referred to as a pin). For the operation of each of these circuits, IN1, IN2, and IN3 do not need to be supplied (see, for example, Non-Patent Document 1).

Further, there is provided a semiconductor integrated circuit which is a power supply control IC having a power supply disconnecting function and an output short circuit detecting function while suppressing an increase in chip area and capable of reducing the size and cost of a power supply circuit. Has been developed.
This circuit is composed of a comparator to which the power supply potential is inputted to minus and a reference potential to be inputted to plus, an output short circuit detection circuit, an output signal of the comparator, and an OR circuit to which an output signal of the output short circuit detection circuit is inputted. By incorporating these circuits in the power supply control IC, the power cut-off function and the output short-circuit detection function are provided, the number of parts constituting the power supply circuit is reduced, and the power supply circuit is reduced in size and cost. (For example, refer to Patent Document 1).
Japanese Patent Application Laid-Open No. 2001-244412 ROHM product specifications

By the way, the techniques described in Non-Patent Document 1 and Patent Document 1 described above require a power supply dedicated to the internal circuit of the IC, but mounting the power supply dedicated to the internal circuit causes a cost increase for the host system. In addition, the number of pins increases by the number of power supply pins for internal circuits, and this increases the cost of the IC itself.
SUMMARY OF THE INVENTION An object of the present invention is to provide an inexpensive power switch IC and a power switch control method that can be turned off when an abnormality occurs in a desired power source input among multiple power sources.

In order to solve the above problems, the invention according to claim 1 is an Nch power MOS that turns on and off lines connected to power sources A, B, and C (potential of power source A ≧ potential of power source B> potential of power source C). When the transistor and the power source A are power sources, and any one of the power sources A, B, and C is turned off, the reset output of the reset output terminal is set to the L level, and the power source input of the power source A is turned off. Turns off all power outputs, and when the power input of the power source B or C is turned off, control means for turning off the power outputs of the power sources B and C, and the power source A as a power source, An abnormality detection circuit for inputting an output potential VDET to the control means when the output potential of the Nch power MOS transistor falls below a threshold value, and a reset signal from the control means using the power supply A as a power supply. In a power switch IC including a first inverter circuit that inverts and outputs to a reset output terminal, a second inverter circuit that uses the power source A as a gate input and the power source B as a power source, and the power source A as a gate A third inverter circuit having the power source C as a power source, a source and a drain connected between the reset output terminal and GND, and an output of the second inverter circuit being gate-input; A reset output side NchMOS transistor; a second reset output side NchMOS transistor whose source and drain are connected between the reset output terminal and GND; and the output of the third inverter circuit is gate-input; The output of the inverter circuit and the output of the third inverter circuit are gate inputs, and the power source A is the power source. A NOR gate having an output from the NOR gate as a gate input and the power source A as a power source, and an Nch power for turning on and off the power source A by using the output from the fourth inverter circuit as a gate input. A first power supply-side NchMOS transistor having a source and drain connected between the gate of the MOS transistor and GND, and the control means having a capability greater than the capability of driving the Nch power MOS transistor; and the second inverter circuit The source and drain are connected between the gate of the Nch power MOS transistor that turns on and off the power supply B and GND, and the control means has a capability greater than the ability to drive the Nch power MOS transistor. Second power supply side NchMOS transistor and front The output of the third inverter circuit is used as a gate input, and the source and drain are connected between the gate of the Nch power MOS transistor for turning on and off the power supply C and GND, and the control means drives the Nch power MOS transistor. A third power supply side NchMOS transistor having a capacity greater than the capacity, the potential of the power supply A drops to 0V, the input potential of the first inverter circuit becomes indefinite, and the L level of the potential of the reset output terminal When an abnormality that cannot be maintained by the first inverter circuit occurs, when the potential of the power source A drops to the threshold value of the second inverter circuit, the output of the second inverter circuit becomes H level, and the second When the NchMOS transistor on the power supply side is turned on, the NchMOS on the second power supply side The transistor overcomes the driving force of each Nch power MOS transistor by the control means to turn off the Nch power MOS transistor on the power supply B side, and the potential of the power supply A is lower than the threshold value of the second inverter circuit. When the threshold voltage of the third inverter circuit is lowered, the output of the third inverter circuit becomes H level, the potential of the reset output terminal is maintained at L level, and the NchMOS transistor on the third power supply side is turned on. the NchMOS transistor of the third power supply side is the oFF state Nch power MOS transistors of the power supply C side overcomes the driving force of each Nch power MOS transistor according to said control means, NchMOS transistors of the first power source side Is turned on, Nc on the first power supply side MOS transistor is characterized in that said turns off the Nch power MOS transistors of the power supply A side by overcoming the driving force of each Nch power MOS transistor according to the control means.

The invention according to claim 2 is a Pch power MOS transistor for turning on and off lines connected to power sources A, B and C (potential of power source A ≧ potential of power source B> potential of power source C), and power source A When any one of the power sources A, B, and C is turned off, the reset output of the reset output terminal is set to L level, and when the power source input of the power source A is turned off, all power source outputs are turned off. When the power supply input of the power supply B or the power supply C is turned off, the control means for turning off the power supply output of the power supply B and the power supply C, the power supply A as a power supply, and the output potential of the Pch power MOS transistor is An abnormality detection circuit for inputting an output potential VDET to the control means when the threshold value is below, and a power supply A as a power supply, and a reset signal from the control means is inverted to a reset output terminal In a power switch IC including a first inverter circuit for outputting, the power source A is a gate input, the second inverter circuit having the power source B as a power source, the power source A is a gate input, and the power source C is A third inverter circuit serving as a power source; a first reset output side NchMOS transistor having a source and a drain connected between the reset output terminal and GND; and an output of the second inverter circuit being gated; A source and drain are connected between the reset output terminal and GND, a second reset output side NchMOS transistor to which the output of the third inverter circuit is gated, an output of the second inverter circuit, and the A NOR gate using the output of the third inverter circuit as a gate input and the power supply A as a power supply; The output of the R gate is the gate input, the source and drain are connected between the power source A and the gate of the Pch power MOS transistor that turns the power source A on and off, and the ability of the control means to drive the Pch power MOS transistor A first power supply side PchMOS transistor, a fifth inverter circuit having the power supply B as a power supply and an output of the second inverter circuit as a gate input, the power supply C as a power supply, and the third inverter A sixth inverter circuit having the output of the circuit as a gate input and a source and a drain between the power source B and the gate of a Pch power MOS transistor that turns on and off the power source B with the output of the fifth inverter circuit as an input And the control means is capable of driving the Pch power MOS transistor. A source and drain between the second power supply side PchMOS transistor having a greater capacity and the power supply C and the gate of the Pch power MOS transistor that turns on and off the power supply C with the output of the sixth inverter circuit as a gate input. And the control circuit has a third power supply side PchMOS transistor having a capacity larger than that for driving the Pch power MOS transistor, and the potential of the power supply A is lowered to 0 V so that the first inverter circuit When the input potential of the power supply A drops to the threshold value of the second inverter circuit, the input potential of the power source A decreases to the threshold value of the second inverter circuit. The output of the second inverter circuit becomes H level, and the fifth inverter circuit The power becomes L level, the PchMOS transistor on the second power supply side is turned on, and the PchMOS transistor on the second power supply side overcomes the driving force of each Pch power MOS transistor by the control means to When the B-side Pch power MOS transistor is turned off and the potential of the power source A drops to the threshold value of the third inverter circuit which is lower than the threshold value of the second inverter circuit, the output of the third inverter circuit becomes H level. The output of the sixth inverter circuit becomes L level, the potential of the reset output terminal is maintained at L level, the PchMOS transistor on the third power supply side is turned on, and the third power supply side PchMOS transistors of each Pch power MOS transistor by the control means Overcoming the power to the Pch power MOS transistors of the power supply C side to the OFF state, the PchMOS transistor of the first power source side is turned on, the PchMOS transistor of the first power source side by the control means each characterized in that it turns off the Pch power MOS transistors of the power supply a side by overcoming the driving force of the Pch power MOS transistor.

  According to the present invention, since only the power input to the power MOS transistor is used and no power input for the control circuit is required other than the power input, the number of power pins of the power switch IC does not increase and the IC is inexpensive. The desired power input can be turned off.

  The power switch IC of this embodiment is a power switch IC in which a plurality of Nch power MOS transistors are integrated, and different power sources are input to the sources of the Nch power MOS transistors. In a power switch IC that operates a control circuit for controlling an Nch power MOS transistor, the control circuit uses a power source A as a gate input and a plurality of inverter circuits using a power source other than the power source A, and between a reset output terminal and GND. An inverter circuit is provided between a plurality of reset output side NchMOS transistors whose sources and drains are connected in parallel and whose output terminal is connected to each gate terminal, and between the gate and GND of each Nch power MOS transistor. Output is connected to the gate, except power supply A Power is input, characterized in that it comprises a power supply side NchMOS transistor to turn off the Nch power MOS transistor when the abnormality occurs.

  In addition to the above configuration, the power switch IC of this embodiment includes a NOR gate in which the output of the inverter circuit is input to the gate, a NOR side inverter circuit in which the output of the NOR gate is input to the gate, and the power source A is input to the source Other NchMOS transistors which are provided between the gate of the power supply A side Nch power MOS transistor and the GND and the output of the NOR side inverter is input to the gate and turn off the power supply A side Nch power MOS transistor when an abnormality occurs Are preferably included.

  Further, the power switch IC of the present embodiment is a power switch IC in which a plurality of Pch power MOS transistors are integrated, and different power sources are input to the sources of the Pch power MOS transistors. In a power switch IC that operates a control circuit that controls all Pch power MOS transistors, the control circuit includes a plurality of first-stage inverter circuits that use a power supply A as a gate input and use a power supply other than the power supply A, and a first-stage inverter circuit. The source and drain are connected in parallel between the reset output terminal and GND, and the output of the first-stage inverter circuit is connected to each gate terminal. Connected reset output NchMOS transistor and each power Pch A power-side PchMOS transistor provided between the gate and source of the OS transistor, connected to the output of the second-stage inverter circuit, and powered by a power source other than the power source A, and turns off the Pch power MOS transistor when an abnormality occurs; It is characterized by including.

  In addition to the above configuration, the power switch IC of the present embodiment includes a NOR gate in which the output of the inverter circuit is input to the gate, an output of the NOR gate is input to the gate, the power source A is connected to the source, and the drain is the power source A. It is preferable to include another PchMOS transistor that is connected to the gate of the side Pch power MOS transistor and turns off the power supply A side Pch power MOS transistor when an abnormality occurs.

[Example 1]
An embodiment of a power switch IC according to the present invention will be described. FIG. 1 is a block diagram showing an embodiment of a power switch IC according to the present invention. In addition, the same code | symbol was used for the element similar to the prior art example shown in FIG.
Input terminals IN 1, IN 2 to which potentials (for example, 3.3 V, 3.3 VAUX, 1.5 V) of different power sources A, B, C (potential of power source A ≧ potential of power source B> potential of power source C ) are input. The sources of Nch power MOS transistors SW1, SW2, and SW3 are connected to IN3, respectively. The drains of the Nch power MOS transistors SW1, SW2, and SW3 are connected to output terminals OUT1, OUT2, and OUT3, respectively.

The output terminals of the gate control circuits are connected to the gates of the Nch power MOS transistors SW1, SW2 and SW3, respectively. Each output terminal OUT1, OUT2, OUT3 is connected to an input terminal of the abnormality detection circuit. The output terminal of the abnormality detection circuit is connected to the input terminal of the gate control circuit and the input terminal of the timing control circuit, and the output potential VDET is the gate control circuit and the timing control circuit (two constitute one control means). Is input. An enable signal is input from the enable input terminal to the gate control circuit, and a reset signal is input from the reset input terminal to the timing control circuit. The output terminal of the timing control circuit is connected to the input terminal of the first inverter circuit INV0, and the output terminal of the inverter circuit INV0 is connected to the reset output terminal.
An input terminal IN1 to which a 3.3V power supply as a desired power supply A is input includes a gate control circuit, a timing control circuit, an abnormality detection circuit, an inverter circuit INV0, a two-input NOR gate circuit NOR1, which will be described later, and a fourth inverter circuit INV3. In addition to being connected to the power supply terminal, the gate input of the second inverter circuit INV1 and the third inverter circuit INV2. That is, the gate control circuit, the timing control circuit, the abnormality detection circuit, and the inverter circuit INV3 operate by receiving power supply from the IN1 terminal.

The output terminal of one inverter circuit INV1 is connected to the NchMOS transistor M1 as the first reset output side NchMOS transistor, the gate of M3 as the second power supply side NchMOS transistor, and the gate of the 2-input NOR gate circuit NOR1. Output terminal of the other inverter circuit INV2 is connected to the gate of the NchMOS transistors M2, the third gate of M4 and as the power source side NchMOS transistors of the two-input NOR gate NOR1 of the second reset output side NchMOS transistor.
The source of the Nch MOS transistor M3 is grounded, and the drain is connected to the gate of the Nch power MOS transistor SW2. The source of the Nch MOS transistor M4 is grounded, and the drain is connected to the gate of the Nch power MOS transistor SW3.

The sources of the Nch MOS transistors M1 and M2 are both grounded, and the drains are both connected to the reset output terminal.
The output terminal of the 2-input NOR gate circuit NOR1 is connected to the input terminal of the inverter circuit INV3, and the output terminal of the inverter circuit INV3 is connected to the gate of the NchMOS transistor M5 as the first reset output side NchMOS transistor . The source of the Nch MOS transistor M5 is grounded, and the drain is connected to the gate of the Nch power MOS transistor SW1.
These inverter circuits INV1, INV2, INV3, NchMOS transistors M1 to M5, and a two-input NOR gate circuit NOR1 constitute a control circuit.

Next, the operation of the power switch IC shown in FIG. 1 will be described.
Here, if the power supply potential is input to each of the input terminals IN1 (AUXIN), IN2 (3.3VIN), and IN3 (1.5VIN) and the output of the Nch power MOS transistor is normal, the reset output is at the “H” level. Is output. A case where IN1 is removed in such an “H” level state will be described.
First, regarding the reset output, when the input of the power supply potential to the input terminal IN1 is removed, the electric charge remaining at the node (node or connection point in the electric circuit theory) of the input terminal IN1 is discharged by the consumption current of the power switch IC. The potential gradually decreases (see FIG. 2).
FIG. 2 is a timing chart for explaining the operation of the power switch IC shown in FIG. In FIG. 2, the horizontal axis indicates the time axis, and the potential axes of the input terminals IN3, IN2, IN1, nodes N1, N2, and the reset terminal are shown from the top. The horizontal wavy line indicates the GND potential. Note that the potential of the input terminal IN2> the potential of the input terminal IN3.
When the potential of the output terminal OUT decreases as the potential of the input terminal IN1 (AUXIN) decreases, and the potential of the output terminal OUT1 falls below the threshold value of the abnormality detection circuit, the potential of the reset terminal becomes “L” level. When the potential of the input terminal IN1 is reduced to 0V, the input potential of the inverter circuit INV0 becomes unstable, so that the “L” level of the potential of the reset terminal cannot be maintained at INV0.

However, since the nodes N1 and N2 are at the “H” level, the NchMOS transistors M1 and M2 can maintain the “L” level of the potential of the reset terminal.
The node N1 becomes “H” level at t2. At t2, the potential of the input terminal IN1 drops to V2 (the potential V2 is a threshold value of the inverter circuit INV1). The node 2 becomes “H” level at t3. At t3, the input terminal IN1 drops to the potential V3 (the potential V3 is a threshold value of the inverter circuit INV2).
Next, the output of the Nch power MOS transistor will be described.
When the potential of the node N1 becomes “H” level, the Nch MOS transistor M3 is turned on, the gate potential of the power MOS transistor SW2 becomes 0V, and the Nch power MOS transistor SW2 is turned off. Similarly, the potential of the node N2 becomes “H” level, and the Nch power MOS transistor SW3 is turned off. Further, when the potential of the node N1 or the node N2 becomes “H” level, the Nch power MOS transistor SW1 is turned off.

  Here, it is preferable that the capability of the Nch MOS transistors M3, M4, and M5 is sufficiently larger than the capability of the gate control circuit to drive the Nch power MOS transistors SW1, SW2, and SW3. This is because the NchMOS transistors M3 and M4 are turned on at times t2 and t3. At this time, the level of the input terminal IN1 is still high, and the level of the input terminal IN1 is high enough to operate the gate control circuit. The NchMOS transistors SW1, SW2, and SW3 can be driven from the gate control circuit. This is to overcome the driving force and turn off the Nch power MOS transistors SW1, SW2, and SW3.

[Example 2]
FIG. 3 is a block diagram showing another embodiment of the power switch IC according to the present invention.
The difference between the power switch IC shown in FIG. 3 and the power switch IC shown in FIG. 1 is that a PchMOS transistor is used. Since the PchMOS transistor and the NchMOS transistor have opposite characteristics with respect to the gate input , the inverter circuit INV4 as the fifth inverter circuit and the INV5 as the sixth inverter circuit are connected to the subsequent stage of the inverter circuits INV1 and INV2, respectively . The gate of the PchMOS transistor M5 as the first power supply side PchMOS transistor is directly connected to the subsequent stage of the 2-input NOR gate NOR1 without using the inverter circuit, and the PchMOS transistor M3 as the second power supply side PchMOS transistor , the third PchMOS transistor as a power source side PchMOS transistor M4, the source is the Pch power without being grounded MO of PchMOS transistor M5 as a first power source side PchMOS transistor It is connected to the source of the transistor SW1, SW2, SW3.
The gate inputs of the inverter circuits INV1 and INV2 are power supplies input to the input terminal IN1, and the power input to the input terminal IN1 is a power supply for the gate control circuit, the abnormality detection circuit, the timing control circuit, and the inverter circuit INV0. And connected to the drain of the PchMOS transistor M5. The source of the Pch MOS transistor M5 is connected to the source of the Pch power MOS transistor SW1. The sources of the Pch MOS transistors M3 and M4 are not grounded but are connected to the gates of the Pch power MOS transistors SW2 and SW3, respectively. The output of the 2-input NOR gate circuit NOR1 is connected to the gate of the PchMOS transistor M5.
The power switch IC shown in FIG. 3 can achieve the same effect as the power switch IC shown in FIG.

〔effect〕
Since only the power supply input to the power MOS transistor is used and no power supply input for the control circuit is required other than the power supply input, the number of power supply pins of the power switch IC is not increased, and the IC can be manufactured at low cost. . In addition, when any power input of the power MOS transistor is turned off, the reset output can function or a desired power input can be turned off. In addition, since it is not necessary to prepare a new power source for the control circuit of the power switch on the substrate of the host system (for example, a personal computer motherboard), the host system can be manufactured at low cost. Further, since the power supply of the IC itself can be taken from the power supply input of the power MOS, the space can be reduced by reducing the cost and reducing the IC package for the IC and the host system.

  The present invention can be used for a personal computer on which an Express Card can be mounted.

It is a block diagram which shows one Example of the power switch IC which concerns on this invention. 3 is a timing chart for explaining the operation of the power switch IC shown in FIG. 1. It is a block diagram which shows the other Example of the power switch IC which concerns on this invention. It is a block diagram of the conventional power IC switch.

Explanation of symbols

IN1 to IN3 input terminals INV0 to INV Inverter circuit M1 to M5 NchMOS transistor (PchMOS transistor)
N1, N2, N4 Node NOR1 2-input NOR gate OUT1-OUT3 Output terminal SW1-SW3 Nch power MOS transistor (Pch power MOS transistor)

Claims (2)

  1. Nch power MOS transistors for turning on and off lines connected to power sources A, B, and C (potential of power source A ≧ potential of power source B> potential of power source C);
    When the power source A is a power source, when any one of the power sources A, B, C is turned off, the reset output of the reset output terminal is set to L level, and when the power source input of the power source A is turned off, all Control means for turning off the power supply output and turning off the power supply output of the power supply B and the power supply C when the power supply input of the power supply B or the power supply C is turned off;
    An abnormality detection circuit that uses the power source A as a power source and inputs an output potential VDET to the control means when the output potential of the Nch power MOS transistor falls below a threshold value;
    In a power switch IC comprising: a power source A as a power source; and a first inverter circuit that inverts a reset signal from the control means and outputs the inverted signal to a reset output terminal.
    A second inverter circuit having the power source A as a gate input and the power source B as a power source;
    A third inverter circuit having the power source A as a gate input and the power source C as a power source;
    A first reset output NchMOS transistor having a source and a drain connected between the reset output terminal and GND, and an output of the second inverter circuit being gated;
    A second reset output side NchMOS transistor having a source and a drain connected between the reset output terminal and GND, and an output of the third inverter circuit being gated;
    A NOR gate having the output of the second inverter circuit and the output of the third inverter circuit as gate inputs and the power source A as a power source;
    A fourth inverter circuit having the output of the NOR gate as a gate input and the power source A as a power source;
    The output of the fourth inverter circuit is used as a gate input, the source and drain are connected between the gate and GND of an Nch power MOS transistor that turns on and off the power supply A, and the control means drives the Nch power MOS transistor. A first power supply side NchMOS transistor having a capacity greater than the capacity;
    The output of the second inverter circuit is used as a gate input, and the source and drain are connected between the gate and GND of an Nch power MOS transistor that turns on and off the power supply B, and the control means drives the Nch power MOS transistor. A second power supply side NchMOS transistor having a capacity greater than the capacity;
    An output of the third inverter circuit is used as a gate input, and a source and a drain are connected between a gate and a GND of an Nch power MOS transistor that turns on and off the power supply C, and the control means drives the Nch power MOS transistor. A third power supply side NchMOS transistor having a capacity larger than the capacity,
    When the potential of the power source A drops to 0 V, the input potential of the first inverter circuit becomes indefinite, and an abnormality occurs that makes it impossible to maintain the L level of the potential of the reset output terminal in the first inverter circuit. When the potential of the power supply A drops to the threshold value of the second inverter circuit, the output of the second inverter circuit becomes H level, the NchMOS transistor on the second power supply side is turned on, and the second power supply The Nch MOS transistor on the side overcomes the driving force of each Nch power MOS transistor by the control means to turn off the Nch power MOS transistor on the power supply B side,
    When the potential of the power source A drops to the threshold value of the third inverter circuit, which is lower than the threshold value of the second inverter circuit, the output of the third inverter circuit becomes H level, and the potential of the reset output terminal becomes L level. And the third power supply side NchMOS transistor is turned on, and the third power supply side NchMOS transistor overcomes the driving force of each Nch power MOS transistor by the control means, and the power supply C side Turn off the Nch power MOS transistor,
    The NchMOS transistor of the first power source side is turned on, the first power source side of Nch power of the power supply A side by overcoming the driving force of the respective Nch power MOS transistor NchMOS transistors by the control means MOS power switch IC, characterized in that the transistor in the oFF state.
  2. Pch power MOS transistors for turning on and off lines connected to power sources A, B, and C (potential of power source A ≧ potential of power source B> potential of power source C);
    When the power source A is a power source, when any one of the power sources A, B, C is turned off, the reset output of the reset output terminal is set to L level, and when the power source input of the power source A is turned off, all Control means for turning off the power supply output and turning off the power supply output of the power supply B and the power supply C when the power supply input of the power supply B or the power supply C is turned off;
    An abnormality detection circuit that uses the power source A as a power source and inputs an output potential VDET to the control means when the output potential of the Pch power MOS transistor falls below a threshold value;
    In a power switch IC comprising: a power source A as a power source; and a first inverter circuit that inverts a reset signal from the control means and outputs the inverted signal to a reset output terminal.
    A second inverter circuit having the power source A as a gate input and the power source B as a power source;
    A third inverter circuit having the power source A as a gate input and the power source C as a power source;
    A first reset output NchMOS transistor having a source and a drain connected between the reset output terminal and GND, and an output of the second inverter circuit being gated;
    A second reset output side NchMOS transistor having a source and a drain connected between the reset output terminal and GND, and an output of the third inverter circuit being gated;
    A NOR gate having the output of the second inverter circuit and the output of the third inverter circuit as gate inputs and the power source A as a power source;
    The output of the NOR gate is the gate input, and the source and drain are connected between the power source A and the gate of the Pch power MOS transistor that turns on and off the power source A, and the control means is larger than the ability to drive the Pch power MOS transistor. A first power-side PchMOS transistor having the capability;
    A fifth inverter circuit having the power source B as a power source and the output of the second inverter circuit as a gate input;
    A sixth inverter circuit having the power source C as a power source and the output of the third inverter circuit as a gate input;
    The output of the fifth inverter circuit is used as an input, and the source and drain are connected between the power source B and the gate of the Pch power MOS transistor that turns on and off the power source B, and the control means drives the Pch power MOS transistor. A second power-side PchMOS transistor having a capacity greater than the capacity to
    An output of the sixth inverter circuit is used as a gate input, and a source and a drain are connected between the power source C and a gate of a Pch power MOS transistor that turns on and off the power source C, and the control circuit uses the Pch power MOS transistor. A third power supply side PchMOS transistor having a capacity larger than that for driving,
    When the potential of the power source A drops to 0 V, the input potential of the first inverter circuit becomes indefinite, and an abnormality occurs that makes it impossible to maintain the L level of the potential of the reset output terminal in the first inverter circuit. When the potential of the power source A drops to the threshold value of the second inverter circuit, the output of the second inverter circuit becomes H level, the output of the fifth inverter circuit becomes L level, and the PchMOS on the second power source side When the transistor is turned on, the Pch MOS transistor on the second power supply side overcomes the driving force of each Pch power MOS transistor by the control means to turn off the Pch power MOS transistor on the power supply B side,
    When the potential of the power source A drops to the threshold value of the third inverter circuit which is lower than the threshold value of the second inverter circuit, the output of the third inverter circuit becomes H level, and the output of the sixth inverter circuit becomes L level. The third power source PchMOS transistor is turned on, and the third power source PchMOS transistor is turned on by the control means. Overcoming the driving power of the MOS transistor and turning off the Pch power MOS transistor on the power source C side,
    The PchMOS transistor of the first power source side is turned on, the first power source side of the PchMOS transistor Pch power of the power supply A side by overcoming the driving force of each Pch power MOS transistor according to the control means MOS A power switch IC characterized in that a transistor is turned off.
JP2004371520A 2004-12-22 2004-12-22 Power switch IC and power switch control method Expired - Fee Related JP4150373B2 (en)

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