JP4129219B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4129219B2
JP4129219B2 JP2003346725A JP2003346725A JP4129219B2 JP 4129219 B2 JP4129219 B2 JP 4129219B2 JP 2003346725 A JP2003346725 A JP 2003346725A JP 2003346725 A JP2003346725 A JP 2003346725A JP 4129219 B2 JP4129219 B2 JP 4129219B2
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external connection
connection terminal
circuit pattern
semiconductor device
case
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JP2005116662A (en
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伸二 奈須
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Description

本発明は、半導体装置に係る発明であって、特に、半導体装置に用いられるケースの構造に関するものである。   The present invention relates to a semiconductor device, and particularly relates to a structure of a case used in the semiconductor device.

従来の半導体パワーモジュールでは、絶縁基板上に回路パターンが形成され、その上に半導体素子が実装されている。さらに、絶縁基板を取り囲むようにケースが形成され、このケースには、外部から半導体素子への入力又は半導体素子から外部への出力のための外部接続用端子が設けられている。外部接続用端子と回路パターンとの間には、アルミワイヤで接合することで電気的に接続している。なお、ケースには樹脂が注入され、ケース内の各構成が封止されている。   In a conventional semiconductor power module, a circuit pattern is formed on an insulating substrate, and a semiconductor element is mounted thereon. Further, a case is formed so as to surround the insulating substrate, and this case is provided with an external connection terminal for input to the semiconductor element from the outside or output from the semiconductor element to the outside. The external connection terminal and the circuit pattern are electrically connected by bonding with an aluminum wire. In addition, resin is inject | poured into the case and each structure in a case is sealed.

特許文献1に示されている従来の半導体パワーモジュールでは、アルミワイヤを介さず外部接続用端子と回路パターンとを直接接続している。ケースにインサート成形された外部接続用端子は、ケース内部の絶縁基板上に形成された回路パターンに接合材を介して接合している。そのため、特許文献1の半導体パワーモジュールは、多数のアルミワイヤをボンディングする必要なしに、大きな電流を流すことができる。   In the conventional semiconductor power module disclosed in Patent Document 1, an external connection terminal and a circuit pattern are directly connected without using an aluminum wire. The external connection terminal insert-molded in the case is joined to a circuit pattern formed on an insulating substrate inside the case via a joining material. Therefore, the semiconductor power module of Patent Document 1 can pass a large current without the need to bond a large number of aluminum wires.

特開2002−299552号公報JP 2002-299552 A

従来の半導体パワーモジュールでは、外部接続用端子と回路パターンとの間をアルミワイヤで接合するので、ワイヤボンディング作業に多くの時間を要するなど組立性に問題があった。また、外部接続用端子に傷や割れなどの不具合がある場合、絶縁基板上の回路パターンと外部接続用端子とを接続するアルミワイヤの接合強度が劣化する問題があった。   In the conventional semiconductor power module, since the external connection terminal and the circuit pattern are joined by the aluminum wire, there is a problem in assemblability because a long time is required for the wire bonding work. Further, when the external connection terminal has a defect such as a scratch or a crack, there is a problem that the bonding strength of the aluminum wire connecting the circuit pattern on the insulating substrate and the external connection terminal deteriorates.

さらに、特許文献1に示されている従来の半導体パワーモジュールでは、接合材を介して外部接続用端子と回路パターンとを接合している。そのため、外部接続用端子と回路パターンとを接合する作業が必要となり、組立作業に多くの時間必要となる問題があった。また、外部接続用端子と回路パターンとの間に接合部分を有することは、この部分で接合不良を生じる可能性があった。   Further, in the conventional semiconductor power module disclosed in Patent Document 1, the external connection terminal and the circuit pattern are bonded via a bonding material. Therefore, there is a problem that an operation for joining the external connection terminal and the circuit pattern is required, and a long time is required for the assembly operation. Further, having a joint portion between the external connection terminal and the circuit pattern may cause a joint failure at this portion.

そこで、本発明は、組立が簡単で生産性が向上し、接合不良による信頼性低下が生じない半導体装置を提供することを目的とする。   In view of the above, an object of the present invention is to provide a semiconductor device that is easy to assemble, improves productivity, and does not cause a decrease in reliability due to poor bonding.

本発明に係る解決手段は、絶縁基板と、絶縁基板の表面に形成される回路パターンと、回路パターン上に実装される半導体素子と、絶縁基板及び半導体素子を取り囲む側壁を有するケースと、半導体素子に対して入出力を行い、回路パターンの一部を延在して形成される外部接続用端子とを備え、外部接続用端子は、延在する回路パターンの一部を折り返して形成された2層構造で、且つ外部接続用端子の一部は、ケースの側壁内に配設され、絶縁基板を支持することを特徴とする。 The solution according to the present invention includes an insulating substrate, a circuit pattern formed on the surface of the insulating substrate, a semiconductor element mounted on the circuit pattern, a case having a sidewall surrounding the insulating substrate and the semiconductor element, and a semiconductor element The external connection terminal is formed by extending a part of the circuit pattern , and the external connection terminal is formed by folding back a part of the extended circuit pattern. in the layer structure, and a portion of the external connection terminal is disposed within the side wall of the case, characterized by supporting the insulating substrate.

本発明に記載の半導体装置は、絶縁基板と、絶縁基板の表面に形成される回路パターンと、回路パターン上に実装される半導体素子と、絶縁基板及び半導体素子を取り囲む側壁を有するケースと、半導体素子に対して入出力を行い、回路パターンの一部を延在して形成される外部接続用端子とを備え、外部接続用端子は、延在する回路パターンの一部を折り返して形成された2層構造で、且つ外部接続用端子の一部は、ケースの前記側壁内に配設され、絶縁基板を支持するので、回路パターンと外部接続用端子との間に接合部が存在しないため、組立が簡単で生産性が向上し、接合不良による信頼性低下が生じない効果がある。また、本発明に記載の半導体装置は、回路パターンが形成される面と平行な方向に移動することを規制しているため、絶縁基板をケースに強固に固定することができる効果がある。さらに、本発明に記載の半導体装置は、外部接続用端子の折り曲げ部分が自由に変更できるため、半導体装置のパッケージを容易に縮小化することが可能である効果がある。

A semiconductor device according to the present invention includes an insulating substrate, a circuit pattern formed on the surface of the insulating substrate, a semiconductor element mounted on the circuit pattern, a case having a sidewall surrounding the insulating substrate and the semiconductor element, and a semiconductor And an external connection terminal formed by extending a part of the circuit pattern and performing input / output with respect to the element, and the external connection terminal is formed by folding a part of the extended circuit pattern Since the two-layer structure and a part of the external connection terminal are disposed in the side wall of the case and support the insulating substrate, there is no junction between the circuit pattern and the external connection terminal. Assembling is simple and productivity is improved, and there is an effect that reliability is not lowered due to poor bonding. In addition, since the semiconductor device described in the present invention restricts movement in a direction parallel to the surface on which the circuit pattern is formed, there is an effect that the insulating substrate can be firmly fixed to the case. Further, the semiconductor device according to the present invention has an effect that the package of the semiconductor device can be easily reduced because the bent portion of the external connection terminal can be freely changed.

(実施の形態1)
図1に、本実施の形態に係る半導体装置の一部の断面図を示す。図1では、銅ベース板1上に絶縁基板であるセラミック基板2を半田3で固定している。このセラミック基板2の表面には、銅の回路パターン5が形成されている。図1では、セラミック基板2の上下の表面に回路パターン5が形成されている。この回路パターン5は、半導体装置の種類により様々なパターンが形成される。さらに、回路パターン5上には半導体素子6が実装される。半導体素子6と回路パターン5とは、半田7により接合されている。半導体素子6と回路パターン5との間には、必要に応じてアルミワイヤ8が設けられ、半導体素子6と回路パターン5とを電気的に接続している。
(Embodiment 1)
FIG. 1 is a cross-sectional view of a part of the semiconductor device according to this embodiment. In FIG. 1, a ceramic substrate 2, which is an insulating substrate, is fixed on a copper base plate 1 with solder 3. A copper circuit pattern 5 is formed on the surface of the ceramic substrate 2. In FIG. 1, circuit patterns 5 are formed on the upper and lower surfaces of the ceramic substrate 2. As the circuit pattern 5, various patterns are formed depending on the type of the semiconductor device. Further, a semiconductor element 6 is mounted on the circuit pattern 5. The semiconductor element 6 and the circuit pattern 5 are joined by solder 7. An aluminum wire 8 is provided between the semiconductor element 6 and the circuit pattern 5 as necessary to electrically connect the semiconductor element 6 and the circuit pattern 5.

本実施の形態に係る半導体装置では、回路パターン5の一部を延在して外部接続用端子9を形成する。図1では、セラミック基板2の上側表面に形成された回路パターン5の一部が、左右方向に延在している。この延在する回路パターン5が、外部接続用端子9として用いられる。ここで、延在する回路パターン5とは、セラミック基板2の端部から外側へ延びた回路パターン5の一部をいう。なお、図1では、半導体素子6が実装される側を半導体装置の内側、その反対側を外側とする。   In the semiconductor device according to the present embodiment, a part of the circuit pattern 5 is extended to form the external connection terminal 9. In FIG. 1, a part of the circuit pattern 5 formed on the upper surface of the ceramic substrate 2 extends in the left-right direction. The extending circuit pattern 5 is used as the external connection terminal 9. Here, the extending circuit pattern 5 refers to a part of the circuit pattern 5 extending outward from the end of the ceramic substrate 2. In FIG. 1, the side on which the semiconductor element 6 is mounted is the inside of the semiconductor device, and the opposite side is the outside.

図2に、外部接続用端子9の一部が折り曲げられた半導体装置の断面図を示す。図2では、外部接続用端子9の一部が、回路パターン5の形成される面に対し略直角に折り曲げられる。なお、外部接続用端子9が折り曲げられる部分は、セラミック基板2の端部から少し外側である。また、折り曲げられた外部接続用端子9は、銅ベース板1の端よりも内側に存在する。   FIG. 2 is a cross-sectional view of a semiconductor device in which a part of the external connection terminal 9 is bent. In FIG. 2, a part of the external connection terminal 9 is bent at a substantially right angle with respect to the surface on which the circuit pattern 5 is formed. The portion where the external connection terminal 9 is bent is slightly outside the end portion of the ceramic substrate 2. Further, the bent external connection terminal 9 exists inside the end of the copper base plate 1.

図3に、本実施の形態に係る半導体装置の断面図を示す。図3では、銅ベース板1を底面として、セラミック基板2及び半導体素子6を取り囲むように側壁を有する例えば樹脂製のケース10が形成されている。このケース10の側壁内には、外部接続用端子9の一部が埋め込まれている。埋め込む方法は、インサート成形であってもアウトサート形成であっても良い。外部接続用端子9の一部をケース10の側壁内に埋め込む(配設する)ことにより、回路パターン5が形成される面と平行な方向に対して、外部接続用端子9がセラミック基板2及び半導体素子6を支持することになる。そのため、セラミック基板2及び半導体素子6は、回路パターン5が形成される面と平行な方向への移動が規制される。図3では、直角に折り曲げられた外部接続用端子9が、セラミック基板2及び半導体素子6を支持し、移動を規制している。   FIG. 3 is a cross-sectional view of the semiconductor device according to the present embodiment. In FIG. 3, for example, a resin case 10 having a side wall so as to surround the ceramic substrate 2 and the semiconductor element 6 is formed with the copper base plate 1 as a bottom surface. A part of the external connection terminal 9 is embedded in the side wall of the case 10. The embedding method may be insert molding or outsert formation. By embedding (arranging) a part of the external connection terminals 9 in the side wall of the case 10, the external connection terminals 9 are connected to the ceramic substrate 2 and the direction parallel to the surface on which the circuit pattern 5 is formed. The semiconductor element 6 is supported. For this reason, the ceramic substrate 2 and the semiconductor element 6 are restricted from moving in a direction parallel to the surface on which the circuit pattern 5 is formed. In FIG. 3, the external connection terminals 9 bent at a right angle support the ceramic substrate 2 and the semiconductor element 6 and restrict the movement.

直角に折り曲げられた外部接続用端子9は、ケース10の上面でさらに折り曲げられ回路パターン5が形成される面と平行になっている。このケース10の上面でさらに折り曲げられた外部接続用端子9の部分が、ケース10から露出し、外部との間で入出力を行う。本実施の形態では、延在する回路パターン5が外部接続用端子9を形成しているので、回路パターン5と外部接続用端子9との間でアルミワイヤ8をボンディングする必要も、接合材で接合する必要もない。なお、本実施の形態では、絶縁特性を向上させるために、ケース9内のセラミック基板2及び半導体素子6上にゲル11が充填され、ケース9の開口部が樹脂12及びフタ13で封止されている。   The external connection terminal 9 bent at a right angle is further bent on the upper surface of the case 10 and is parallel to the surface on which the circuit pattern 5 is formed. The portion of the external connection terminal 9 that is further bent on the upper surface of the case 10 is exposed from the case 10 and performs input / output with the outside. In the present embodiment, since the extended circuit pattern 5 forms the external connection terminal 9, it is also necessary to bond the aluminum wire 8 between the circuit pattern 5 and the external connection terminal 9 with a bonding material. There is no need to join. In this embodiment, gel 11 is filled on the ceramic substrate 2 and the semiconductor element 6 in the case 9 and the opening of the case 9 is sealed with the resin 12 and the lid 13 in order to improve the insulation characteristics. ing.

以上のように、本実施の形態に記載の半導体装置では、セラミック基板2とセラミック基板2の表面に形成される回路パターン5と、回路パターン5上に実装される半導体素子6と、セラミック基板2及び半導体素子6を取り囲むケース10側壁を有すると、半導体素子6に対して入出力を行い、回路パターン5の一部を延在して形成される外部接続用端子9とを備え、外部接続用端子9の一部が、ケース10の側壁内に配設され、セラミック基板2を支持するので、回路パターン5が形成される面と平行な方向に移動することを規制し、セラミック基板2をケース9に強固に固定することができる。また、本実施の形態に記載の半導体装置では、回路パターン5と外部接続用端子9との間でアルミワイヤ8による接合がないので、組立が簡単で生産性が向上し、接合不良による信頼性低下が生じない。さらに、外部接続用端子9の折り曲げ部分は自由に変更できるため、半導体装置のパッケージを容易に縮小化することが可能である。   As described above, in the semiconductor device described in the present embodiment, the ceramic substrate 2, the circuit pattern 5 formed on the surface of the ceramic substrate 2, the semiconductor element 6 mounted on the circuit pattern 5, and the ceramic substrate 2. And having a side wall of the case 10 surrounding the semiconductor element 6, includes an external connection terminal 9 that inputs and outputs to the semiconductor element 6 and that is formed by extending a part of the circuit pattern 5. A part of the terminal 9 is disposed in the side wall of the case 10 and supports the ceramic substrate 2. Therefore, movement of the ceramic substrate 2 in the direction parallel to the surface on which the circuit pattern 5 is formed is restricted. 9 can be firmly fixed. Further, in the semiconductor device described in the present embodiment, since there is no bonding with the aluminum wire 8 between the circuit pattern 5 and the external connection terminal 9, the assembly is simple, the productivity is improved, and the reliability due to the bonding failure. There is no reduction. Furthermore, since the bent portion of the external connection terminal 9 can be freely changed, the package of the semiconductor device can be easily reduced.

(実施の形態2)
図4に、本実施の形態に係る半導体装置の一部の断面図を示す。本実施の形態は、図4に示すように、実施の形態1とほぼ同じ構造である。具体的には、銅ベース板1上に絶縁基板であるセラミック基板2を半田3で固定している。このセラミック基板2の表面には、銅の回路パターン5が形成されている。図4では、セラミック基板2の上下の表面に回路パターン5が形成されている。さらに、回路パターン5上には半導体素子6が実装される。半導体素子6と回路パターン5とは、半田7により接合されている。半導体素子6と回路パターン5との間には、必要に応じてアルミワイヤ8が設けられ、半導体素子6と回路パターン5とを電気的に接続している。
(Embodiment 2)
FIG. 4 is a partial cross-sectional view of the semiconductor device according to this embodiment. As shown in FIG. 4, the present embodiment has substantially the same structure as the first embodiment. Specifically, a ceramic substrate 2, which is an insulating substrate, is fixed on a copper base plate 1 with solder 3. A copper circuit pattern 5 is formed on the surface of the ceramic substrate 2. In FIG. 4, circuit patterns 5 are formed on the upper and lower surfaces of the ceramic substrate 2. Further, a semiconductor element 6 is mounted on the circuit pattern 5. The semiconductor element 6 and the circuit pattern 5 are joined by solder 7. An aluminum wire 8 is provided between the semiconductor element 6 and the circuit pattern 5 as necessary to electrically connect the semiconductor element 6 and the circuit pattern 5.

しかし、本実施の形態では、実施の形態1と比べて外部接続用端子9の形状が異なる。実施の形態1では、延在する回路パターン5を単に外部接続用端子9として用いている。本実施の形態では、延在する回路パターン5を折り返して2層構造の外部接続用端子9として用いている。図4では、実施の形態1の場合に比べほぼ2倍に延在した回路パターン5を外側に折り返して外部接続用端子9を形成している。図4でも、半導体素子6が実装される側を半導体装置の内側、その反対側を外側とする。なお、延在する回路パターン5の先端は、折り返すことによりセラミック基板2の近傍に位置している。また、図4でも、外部接続用端子9の一部が、回路パターン5の形成される面に対し略直角に折り曲げられている。   However, in the present embodiment, the shape of the external connection terminal 9 is different from that in the first embodiment. In the first embodiment, the extended circuit pattern 5 is simply used as the external connection terminal 9. In the present embodiment, the extended circuit pattern 5 is folded and used as the external connection terminal 9 having a two-layer structure. In FIG. 4, the external connection terminals 9 are formed by folding outward the circuit pattern 5 extending approximately twice as compared with the case of the first embodiment. Also in FIG. 4, the side on which the semiconductor element 6 is mounted is the inside of the semiconductor device and the opposite side is the outside. Note that the tip of the extended circuit pattern 5 is positioned in the vicinity of the ceramic substrate 2 by being folded back. Also in FIG. 4, a part of the external connection terminal 9 is bent at a substantially right angle with respect to the surface on which the circuit pattern 5 is formed.

図5に、本実施の形態に係る半導体装置の断面図を示す。図5では、実施の形態1同様、銅ベース板1を底面として、セラミック基板2及び半導体素子6を取り囲むように側壁を有する例えば樹脂製のケース10が形成されている。このケース10の側壁内には、外部接続用端子9の一部が埋め込まれている。埋め込む方法は、インサート成形であってもアウトサート形成であっても良い。本実施の形態でも、外部接続用端子9の一部をケース10の側壁内に埋め込む(配設する)ことにより、回路パターン5が形成される面と平行な方向に対して、外部接続用端子9がセラミック基板2及び半導体素子6を支持し、移動を規制している。   FIG. 5 shows a cross-sectional view of the semiconductor device according to the present embodiment. In FIG. 5, as in the first embodiment, for example, a resin case 10 having a side wall so as to surround the ceramic substrate 2 and the semiconductor element 6 is formed with the copper base plate 1 as a bottom surface. A part of the external connection terminal 9 is embedded in the side wall of the case 10. The embedding method may be insert molding or outsert formation. Also in the present embodiment, a part of the external connection terminal 9 is embedded (arranged) in the side wall of the case 10 so that the external connection terminal is oriented in a direction parallel to the surface on which the circuit pattern 5 is formed. 9 supports the ceramic substrate 2 and the semiconductor element 6 and restricts movement.

直角に折り曲げられた外部接続用端子9は、ケース10の上面でさらに折り曲げられ回路パターン5が形成される面と平行になっている。このケース10の上面でさらに折り曲げられた外部接続用端子9の部分が、ケース10から露出し、外部との間で入出力を行う。本実施の形態は、実施の形態1と比べて2層構造の外部接続用端子9以外は同じである。そのため、実施の形態1で示した効果は、本実施の形態も全て有している。   The external connection terminal 9 bent at a right angle is further bent on the upper surface of the case 10 and is parallel to the surface on which the circuit pattern 5 is formed. The portion of the external connection terminal 9 that is further bent on the upper surface of the case 10 is exposed from the case 10 and performs input / output with the outside. This embodiment is the same as the first embodiment except for the external connection terminal 9 having a two-layer structure. Therefore, all the effects shown in the first embodiment also have the present embodiment.

さらに、本実施の形態に記載の半導体装置は、外部接続用端子9が、延在する回路パターン5の一部を折り返して形成された2層構造であるので、外部接続用端子9が薄板であっても電流容量を増加させることができる。   Further, in the semiconductor device described in this embodiment, since the external connection terminal 9 has a two-layer structure formed by folding a part of the extending circuit pattern 5, the external connection terminal 9 is a thin plate. Even if it exists, current capacity can be increased.

(変形例)
上記で説明した本実施の形態では、図4に示すように実施の形態1の場合に比べほぼ2倍に延在した回路パターン5を外側に折り返して外部接続用端子9を形成していた。しかし、本変形例では、図6に示すように実施の形態1の場合に比べほぼ2倍に延在した回路パターン5を内側に折り返して外部接続用端子9を形成している。この点以外に、本実施の形態と本変形例との間に異なる点はない。そのため、図6についての詳細な説明は省略する。なお、図6でも、半導体素子6が実装される側を半導体装置の内側、その反対側を外側とする。
(Modification)
In the present embodiment described above, as shown in FIG. 4, the external connection terminal 9 is formed by folding back the circuit pattern 5 extending almost twice as compared with the case of the first embodiment. However, in this modified example, as shown in FIG. 6, the external connection terminal 9 is formed by folding inward the circuit pattern 5 extending approximately twice as compared with the case of the first embodiment. Other than this point, there is no difference between this embodiment and this modification. Therefore, the detailed description about FIG. 6 is abbreviate | omitted. In FIG. 6, the side on which the semiconductor element 6 is mounted is the inside of the semiconductor device, and the opposite side is the outside.

図7に、本変形例の形態に係る半導体装置の断面図を示す。図7に示す半導体装置は、図5に示す半導体装置と比べて延在する回路パターン5を内側に折り返している点以外は同じである。そのため、図7についての詳細な説明は省略する。本変形例では、本実施の形態で示した効果を全て含む。   FIG. 7 is a cross-sectional view of a semiconductor device according to this modification. The semiconductor device shown in FIG. 7 is the same as the semiconductor device shown in FIG. 5 except that the extending circuit pattern 5 is folded inward. Therefore, the detailed description about FIG. 7 is abbreviate | omitted. This modification includes all the effects shown in the present embodiment.

さらに、本変形例に記載の半導体装置は、延在する回路パターン5の一部が半導体素子6側に折り返されるので、延在する回路パターン5を外側に折り返す場合に比べ、外部接続用端子9と銅ベース板1との絶縁距離を大きく取ることができ、半導体装置の絶縁性を向上させることができる。   Further, in the semiconductor device described in the present modification, a part of the extended circuit pattern 5 is folded back to the semiconductor element 6 side, so that the external connection terminal 9 is compared with the case where the extended circuit pattern 5 is folded outward. The insulation distance between the semiconductor device and the copper base plate 1 can be increased, and the insulation of the semiconductor device can be improved.

(実施の形態3)
図8(a)に、本実施の形態に係る半導体装置の断面図を示す。図8(a)でも、延在する回路パターン5を折り返して2層構造の外部接続用端子9としている。この2層の間に導電性接着剤20が充填され、外部接続用端子9の2層が貼り合わされている。図8(a)に示す半導体装置は、導電性接着剤20で貼り合わされた外部接続用端子9以外、図5に示した半導体装置の断面図と基本的に同じである。そのため、図5に示す半導体装置と同じ符号を付した部分については詳細な説明を省略する。
(Embodiment 3)
FIG. 8A shows a cross-sectional view of the semiconductor device according to the present embodiment. Also in FIG. 8A, the extended circuit pattern 5 is folded to form the external connection terminal 9 having a two-layer structure. A conductive adhesive 20 is filled between the two layers, and the two layers of the external connection terminals 9 are bonded together. The semiconductor device shown in FIG. 8A is basically the same as the cross-sectional view of the semiconductor device shown in FIG. 5 except for the external connection terminals 9 bonded with the conductive adhesive 20. Therefore, detailed description of portions denoted by the same reference numerals as those of the semiconductor device illustrated in FIG. 5 is omitted.

延在する回路パターン5を折り返して2層の外部接続用端子9を形成する場合、折り返しによる復元力が延在する回路パターン5に生じることがある。そのため、折り返した回路パターン5の先端を導電性接着剤などで固着していた。しかし、単に先端を導電性接着剤などで固着するだけでは、折り返しによる復元力により固着部分が外れる場合があり、電流容量が低下する問題があった。そこで、本実施の形態では、外部接続用端子9の2層の間に導電性接着剤20を充填して貼り合わせている。その結果、本実施の形態では、折り返しによる復元力に対しても貼り合わせ部分が外れ難く、電流容量が低下する不具合を回避することができる。   When the extended circuit pattern 5 is folded to form the two-layer external connection terminals 9, a restoring force due to the folding may be generated in the extended circuit pattern 5. Therefore, the tip of the folded circuit pattern 5 is fixed with a conductive adhesive or the like. However, simply fixing the tip with a conductive adhesive or the like may cause the fixing portion to be detached due to the restoring force due to folding, resulting in a problem that the current capacity is reduced. Therefore, in the present embodiment, the conductive adhesive 20 is filled and bonded between the two layers of the external connection terminals 9. As a result, in the present embodiment, it is difficult for the bonded portion to come off even with a restoring force due to folding, and it is possible to avoid a problem that the current capacity is reduced.

本実施の形態では、外部接続用端子9の先端部近傍の1層に充填孔21を設け、この充填孔21から導電性接着剤20を外部接続用端子9の2層の間に充填している。図8(b)に、外部接続用端子9の先端部近傍の平面図を示す。充填孔21は、ほぼ直角に折り曲げられた2層の外部接続用端子9の間と直接繋がる貫通孔として2層のうちの1層(ケース10と反対側の層)に設けられる。図8(b)に示す外部接続用端子9の先端部近傍の1層に充填孔21を設け、この充填孔21から導電性接着剤20を充填することで、外部接続用端子9の2層の間に導電性接着剤20を容易に充填することができ生産性の向上を図れる。なお、図8(b)では、外部からの配線を接続するためのネジ穴22が記載されている。   In this embodiment, a filling hole 21 is provided in one layer near the tip of the external connection terminal 9, and the conductive adhesive 20 is filled between the two layers of the external connection terminal 9 through the filling hole 21. Yes. FIG. 8B shows a plan view of the vicinity of the tip of the external connection terminal 9. The filling hole 21 is provided in one of the two layers (the layer on the side opposite to the case 10) as a through hole that directly connects between the two layers of external connection terminals 9 that are bent substantially at a right angle. A filling hole 21 is provided in one layer near the tip of the external connection terminal 9 shown in FIG. 8B, and the conductive adhesive 20 is filled from the filling hole 21, thereby providing two layers of the external connection terminal 9. During this period, the conductive adhesive 20 can be easily filled, and productivity can be improved. In FIG. 8B, a screw hole 22 for connecting an external wiring is shown.

また、本実施の形態では、図8(c)に示すように導電性接着剤溜まり23が外部接続用端子9の基部近傍(セラミック基板2近傍)に設けられている。この導電性接着剤溜まり23は、延在する回路パターン5の折り返し前の先端部分に溝を形成して設けられている。そして、この導電性接着剤溜まり23は、充填孔21から充填し過ぎた導電性接着剤20を溜めることができ、外部接続用端子9外部への導電性接着剤20の流出を防いでいる。流出した導電性接着剤20が回路パターン5やアルミワイヤ8に付着することにより半導体装置の絶縁性が劣化する場合がある。本実施の形態に示した導電性接着剤溜まり23は、この絶縁性の劣化を防ぐことができる。   Further, in the present embodiment, as shown in FIG. 8C, the conductive adhesive reservoir 23 is provided in the vicinity of the base portion of the external connection terminal 9 (in the vicinity of the ceramic substrate 2). The conductive adhesive reservoir 23 is provided with a groove formed at the front end portion of the extending circuit pattern 5 before it is folded back. The conductive adhesive reservoir 23 can store the conductive adhesive 20 that has been excessively filled from the filling hole 21, and prevents the conductive adhesive 20 from flowing out of the external connection terminal 9. The conductive adhesive 20 that has flowed out adheres to the circuit pattern 5 or the aluminum wire 8, so that the insulating properties of the semiconductor device may deteriorate. The conductive adhesive reservoir 23 shown in the present embodiment can prevent this deterioration of insulation.

以上まとめると、本実施の形態に記載の半導体装置は、外部接続用端子9の2層が、導電性接着剤20で貼り合わされているので、外部接続用端子9の2層を安定して固着することができ、外部接続用端子9の電気容量を増加させることができる。   In summary, in the semiconductor device described in this embodiment, since the two layers of the external connection terminals 9 are bonded together with the conductive adhesive 20, the two layers of the external connection terminals 9 are stably fixed. It is possible to increase the electric capacity of the external connection terminal 9.

また、本実施の形態に記載の半導体装置は、外部接続用端子9の先端部近傍の1層に充填孔21をさらに備え、導電性接着剤21が、充填孔21から外部接続用端子9の2層の間に充填されるので、外部接続用端子9の2層の間に導電性接着剤20を容易に充填することができ生産性の向上を図れる。   In addition, the semiconductor device described in the present embodiment further includes a filling hole 21 in one layer in the vicinity of the tip of the external connection terminal 9, and the conductive adhesive 21 is connected to the external connection terminal 9 from the filling hole 21. Since it is filled between the two layers, the conductive adhesive 20 can be easily filled between the two layers of the external connection terminals 9, and the productivity can be improved.

(実施の形態4)
図9(a)に、本実施の形態に係る半導体装置の一部の断面図を示す。図9(a)でも、延在する回路パターン5を内側に折り返して2層構造の外部接続用端子9としている。本実施の形態では、この2層の間に導電性接着剤20を充填せずに、延在する回路パターン5の折り返し前の先端近傍(折り返し後は外部接続用端子9の基部に位置する)に設けた長孔25に固着材である半田26を充填して2層を固定している。図9(b)に、長孔25を半田26で固定する外部接続用端子9の拡大図を示す。図9(b)では、外部接続用端子9の基部近傍の1層に設けられた長孔25に半田26が充填されている様子が示されている。
(Embodiment 4)
FIG. 9A shows a partial cross-sectional view of the semiconductor device according to this embodiment. Also in FIG. 9A, the extending circuit pattern 5 is folded inward to form the external connection terminal 9 having a two-layer structure. In the present embodiment, the conductive adhesive 20 is not filled between the two layers, and the vicinity of the front end of the extending circuit pattern 5 before folding (positioned at the base of the external connection terminal 9 after folding). The two holes are fixed by filling the long holes 25 provided with the solder 26 as a fixing material. FIG. 9B shows an enlarged view of the external connection terminal 9 for fixing the long hole 25 with the solder 26. FIG. 9B shows a state where the long holes 25 provided in one layer near the base of the external connection terminal 9 are filled with the solder 26.

図9(a)に示す半導体装置では、長孔25を半田26で固定している以外、図7に示した半導体装置の断面図と基本的に同じである。そのため、図7に示す半導体装置と同じ符号を付した部分については、詳細な説明を省略する。図10に、長孔25を半田26で固定する外部接続用端子9の一部の平面図を示す。図10では、長孔25の形状が外部接続用端子9の幅方向に長い。しかし、本発明では長孔25の形状及び設ける位置については特に制限はない。   The semiconductor device shown in FIG. 9A is basically the same as the cross-sectional view of the semiconductor device shown in FIG. 7 except that the long holes 25 are fixed with solder 26. Therefore, detailed description of portions denoted by the same reference numerals as those of the semiconductor device illustrated in FIG. 7 is omitted. FIG. 10 is a plan view of a part of the external connection terminal 9 for fixing the long hole 25 with the solder 26. In FIG. 10, the shape of the long hole 25 is long in the width direction of the external connection terminal 9. However, in the present invention, there is no particular limitation on the shape and position of the long hole 25.

折り返した回路パターン5の先端を単に半田などで固着しようとすると、半田が流れ回路パターン5やアルミワイヤ8に付着する場合があった。半田が流れ不必要な部分に付着した場合、半導体装置の絶縁性が劣化することもあった。そこで、本実施の形態では、延在する回路パターン5の折り返し前の先端近傍(折り返し後は外部接続用端子9の基部に位置する)に設けた長孔25に半田26を充填して固定することで、外部接続用端子9の2層を貼り合わせている。その結果、本実施の形態では、半田26が長孔25から流れ出すことなく、半導体装置の絶縁性劣化を生じさせる不具合を回避することができる。   If the tip of the folded circuit pattern 5 is simply fixed with solder or the like, the solder may flow and adhere to the circuit pattern 5 or the aluminum wire 8. When the solder flows and adheres to unnecessary portions, the insulating properties of the semiconductor device may deteriorate. Therefore, in the present embodiment, the long hole 25 provided near the tip of the extended circuit pattern 5 before it is folded (positioned at the base of the external connection terminal 9 after it is folded) is filled with solder 26 and fixed. Thus, the two layers of the external connection terminals 9 are bonded together. As a result, in the present embodiment, the solder 26 does not flow out of the long hole 25, and the problem that causes the insulation deterioration of the semiconductor device can be avoided.

なお、本実施の形態では、延在する回路パターン5を内側に折り返す場合を示したが、本発明は、延在する回路パターン5を外側に折り返す場合であっても良い。さらに、長孔25を設ける数は、作業効率から考えると1つであることが好ましいが、外部接続用端子9の2層を安定して接合させる点から考えると長孔25を複数設けても良い。   In the present embodiment, the case where the extending circuit pattern 5 is folded back inside is shown, but the present invention may be a case where the extending circuit pattern 5 is folded outside. Further, the number of the long holes 25 is preferably one from the viewpoint of work efficiency, but a plurality of the long holes 25 may be provided from the viewpoint of stably joining the two layers of the external connection terminals 9. good.

以上のように、本実施の形態に記載の半導体装置は、外部接続用端子9の基部近傍の1層に長孔25をさらに備え、外部接続用端子9の2層が、長孔25に半田26を充填することで貼り合わされるので、半田26が長孔25から流れ出すことなく、半導体装置の絶縁性劣化を生じさせる不具合を回避することができる。また、1つの長孔25で接合する場合は、作業効率が高くなり生産性を向上させることができる。   As described above, the semiconductor device described in the present embodiment further includes the long hole 25 in one layer near the base of the external connection terminal 9, and the two layers of the external connection terminal 9 are soldered to the long hole 25. Since the bonding is performed by filling 26, the solder 26 does not flow out of the long hole 25, and it is possible to avoid the problem that causes the insulation deterioration of the semiconductor device. Moreover, when joining with one long hole 25, work efficiency becomes high and productivity can be improved.

(実施の形態5)
図11に、本実施の形態に係る半導体装置の一部の断面図を示す。本実施の形態では、延在する回路パターン5を折り返して2層構造の外部接続用端子9とするのではなく、外部接続用端子9とは別に形成した外部接続用補助端子30を貼り合わせることで2層構造としている。図11では、延在する回路パターン5で1層の外部接続用端子9を形成し、その上に別で形成した外部接続用補助端子30を貼り合わせている。なお、外部接続用端子9と外部接続用補助端子30との貼り合わせは、導電性接着剤20を2層の間に充填しても良いし、長孔に固着材を充填して固定しても良い。
(Embodiment 5)
FIG. 11 is a cross-sectional view of a part of the semiconductor device according to this embodiment. In the present embodiment, the extended circuit pattern 5 is not folded back to form the external connection terminal 9 having a two-layer structure, but the external connection auxiliary terminal 30 formed separately from the external connection terminal 9 is bonded. It has a two-layer structure. In FIG. 11, a single layer of external connection terminal 9 is formed by an extended circuit pattern 5, and an external connection auxiliary terminal 30 formed separately is bonded thereon. The bonding between the external connection terminal 9 and the external connection auxiliary terminal 30 may be performed by filling the conductive adhesive 20 between the two layers, or by fixing the long hole with a fixing material. Also good.

図11に示す半導体装置は、外部接続用補助端子30を貼り合わせる以外、図3に示した半導体装置の断面図と基本的に同じである。そのため、図3に示す半導体装置と同じ符号を付した部分については、詳細な説明を省略する。   The semiconductor device shown in FIG. 11 is basically the same as the cross-sectional view of the semiconductor device shown in FIG. 3 except that the auxiliary terminal 30 for external connection is bonded. Therefore, detailed description of portions denoted by the same reference numerals as those of the semiconductor device illustrated in FIG. 3 is omitted.

以上のように、本実施の形態に記載の半導体装置では、外部接続用端子9が、外部接続用端子9とは別に形成された外部接続用補助端子30を貼り合わせることで2層構造を形成するので、延在する回路パターン5を折り返す工程が不要となり、単純な形状である外部接続用補助端子30を貼り合わせるだけで製造が容易になり、生産性が向上する。   As described above, in the semiconductor device described in the present embodiment, the external connection terminal 9 forms a two-layer structure by bonding the external connection auxiliary terminal 30 formed separately from the external connection terminal 9. Therefore, the process of turning back the extended circuit pattern 5 is not required, and manufacturing is facilitated by simply attaching the auxiliary terminal 30 for external connection having a simple shape, thereby improving productivity.

なお、外部接続用補助端子30の形状は、延在する回路パターン5(1層の外部接続用端子9)の形状と同じであっても良いが、延在する回路パターン5の形状より大きくすることで、さらに電流容量を増加させることも可能である。   The shape of the external connection auxiliary terminal 30 may be the same as the shape of the extended circuit pattern 5 (one-layer external connection terminal 9), but is larger than the shape of the extended circuit pattern 5. Thus, the current capacity can be further increased.

本発明の実施の形態1に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態2に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態2の変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on the modification of Embodiment 2 of this invention. 本発明の実施の形態2の変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on the modification of Embodiment 2 of this invention. 本発明の実施の形態3に係る半導体装置を示す図である。It is a figure which shows the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態4に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on Embodiment 4 of this invention. 本発明の実施の形態4に係る外部接続用端子の平面図である。It is a top view of the terminal for external connection which concerns on Embodiment 4 of this invention. 本発明の実施の形態5に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on Embodiment 5 of this invention.

符号の説明Explanation of symbols

1 銅ベース板、2 セラミック基板、3,7,26 半田、5 回路パターン、6 半導体素子、8 アルミワイヤ、9 外部接続用端子、10 ケース、11 ゲル、12 樹脂、13 フタ、20 導電性接着剤、21 充填孔、22 ネジ穴、23 導電性接着剤溜まり、25 長孔、30 外部接続用補助端子。
1 Copper base plate, 2 Ceramic substrate, 3, 7, 26 Solder, 5 Circuit pattern, 6 Semiconductor element, 8 Aluminum wire, 9 External connection terminal, 10 Case, 11 Gel, 12 Resin, 13 Lid, 20 Conductive adhesion Agent, 21 filling hole, 22 screw hole, 23 conductive adhesive reservoir, 25 long hole, 30 auxiliary terminal for external connection.

Claims (5)

絶縁基板と、
前記絶縁基板の表面に形成される回路パターンと、
前記回路パターン上に実装される半導体素子と、
前記絶縁基板及び前記半導体素子を取り囲む側壁を有するケースと、
前記半導体素子に対して入出力を行い、前記回路パターンの一部を延在して形成される外部接続用端子とを備え、
前記外部接続用端子は、延在する前記回路パターンの一部を折り返して形成された2層構造で、且つ前記外部接続用端子の一部は、前記ケースの前記側壁内に配設され、前記絶縁基板を支持することを特徴とする、半導体装置。
An insulating substrate;
A circuit pattern formed on the surface of the insulating substrate;
A semiconductor element mounted on the circuit pattern;
A case having a side wall surrounding the insulating substrate and the semiconductor element;
Input / output to and from the semiconductor element, and an external connection terminal formed by extending a part of the circuit pattern,
The external connection terminal has a two-layer structure formed by folding a part of the extending circuit pattern, and a part of the external connection terminal is disposed in the side wall of the case, A semiconductor device which supports an insulating substrate.
請求項1に記載の半導体装置であって、The semiconductor device according to claim 1,
延在する前記回路パターンの一部は、前記半導体素子側に折り返されることを特徴とする、半導体装置。  A part of the extending circuit pattern is folded back to the semiconductor element side.
請求項1又は請求項2に記載の半導体装置であって、The semiconductor device according to claim 1 or 2, wherein
前記外部接続用端子の2層は、導電性接着剤で貼り合わされていることを特徴とする、半導体装置。  2. The semiconductor device according to claim 2, wherein the two layers of the external connection terminals are bonded together with a conductive adhesive.
請求項3に記載の半導体装置であって、The semiconductor device according to claim 3,
前記外部接続用端子の先端部近傍の1層に充填孔をさらに備え、  Further provided with a filling hole in one layer near the tip of the external connection terminal,
前記導電性接着剤は、前記充填孔から前記外部接続用端子の2層の間に充填され得ることを特徴とする、半導体装置。  The semiconductor device according to claim 1, wherein the conductive adhesive can be filled between the two layers of the external connection terminal through the filling hole.
請求項1又は請求項2に記載の半導体装置であって、The semiconductor device according to claim 1 or 2, wherein
前記外部接続用端子の基部近傍の1層に孔をさらに備え、  A hole is further provided in one layer near the base of the external connection terminal,
前記外部接続用端子の2層は、前記孔に固着剤を充填することで貼り合わされていることを特徴とする、半導体装置。  The semiconductor device according to claim 2, wherein the two layers of the external connection terminal are bonded together by filling the hole with a fixing agent.
JP2003346725A 2003-10-06 2003-10-06 Semiconductor device Expired - Lifetime JP4129219B2 (en)

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