JP4112647B2 - Driving circuit for matrix display device - Google Patents

Description

【０１１９】
次に、アドレス電極配線Ｗｋと隣接するアドレス電極配線Ｗｋ−１との間に形成される静電容量Ｃｗに起因した消費電力は以下のようになる。各アドレス電極配線Ｗｋ、Ｗｋ−１に印加されるアドレスパルスは、ｌ−１行選択期間からｌ行選択期間へと移行する際に、下表Ｂの（１）〜（１６）のような組み合わせのいずれかで変化する。そして、これらの（１）〜（１６）の場合における静電容量Ｃｗに起因した消費電力は、表Ｂの（１７）欄に示すようになる。
【表２】

【０１２０】
以上の表Ａ及び表Ｂのように、表示パターンに応じたアドレスパルスの変化から各放電セル毎に、データドライバの消費電力を求めることができる。よって、ドライバ電力予測演算部７２は、入力画像データ１から得られる点灯・非点灯情報に基づいて、表示パネル上の放電セルＤ（Ｗ，ＸＹ）のそれぞれについて、例えば、別途格納しておいた上記表Ａ、Ｂを参照して消費電力を求め、その総和を求めれば、一画面分のデータをＰＤＰ１２の各放電セルに書き込む際に要するデータドライバ消費電力を求めることができる。
【０１２１】
以上、この実施の形態８のようにデータドライバ消費電力を予測演算して、その結果に基づいて入力画像データから特定成分を除去する事とすれば、１フィールド毎の入力画像の明暗変化が大きい場合などにおいても、一時的にデータドライバでの消費電力が規定値を超えてしまうことを未然に防止できる。
【０１２２】
なお、以上に説明した各実施の形態１〜８においては、マトリクス表示装置としてプラズマディスプレイ装置を例にとって説明したが、これには限らず、液晶表示装置あるいはエレクトロルミネッセンス表示装置の各駆動回路においても、上述のような構成を採用することにより駆動電極ドライバの消費電力を低減あるいは一定範囲内に維持することができる。また、液晶表示装置及びエレクトロルミネッセンス表示装置において、駆動信号とは、プラズマディスプレイ装置でのアドレスパルスと同様に、各画素における点灯・非点灯を決定する信号であり、駆動電極配線は、このような駆動信号が印加される電極配線を意味する。また、走査信号とは、各画素でのより具体的な表示内容（輝度、階調など）を示す信号であり、走査電極配線とは、この走査信号が印加される電極配線である。
【０１２３】
例えば、アクティブマトリクス型液晶表示装置を例にとると、上記駆動電極配線はゲート電極配線、駆動信号はゲート信号、走査電極配線はソースあるいはドレイン電極配線、走査信号はデータ信号に相当する。
【０１２４】
【発明の効果】
以上のように、この発明によれば、プラズマディスプレイ装置、液晶表示装置、エレクトロルミネッセンス表示装置等のマトリクス表示装置の駆動回路において、互いに隣接する駆動電極配線にそれぞれ印加する前記駆動信号の立ち下がりと立ち上がりタイミングとが互いにずれるように制御するため、隣接する駆動電極配線間に形成される静電容量の充放電による駆動電極ドライバでの消費電力を低減することができる。このように消費電極を低減できれば、携帯用の表示装置においては携帯時の使用時間を伸ばすことが可能で、一方大画面の表示装置を実現するにあたっても発熱の問題を低減でき、極めて有利である。さらに最大許容消費電力の低い駆動電極ドライバを用いることができるため、装置のコストダウンを図ることもできる。
【図面の簡単な説明】
【図１】 この発明の実施の形態１に係るプラズマディスプレイ装置及びその駆動回路の構成を示す図である。
【図２】 図１のデータドライバ９の構成を示す図である。
【図３】 実施の形態１に係るアドレス電極配線の駆動波形を示す図である。
【図４】 実施の形態１の駆動方式におけるデータドライバでの消費電力を説明するための図である。
【図５】 図１の立ち上がり遅延回路３２の構成を示す図である。
【図６】 図５の立ち上がり遅延回路３２での駆動波形を示す図である。
【図７】 実施の形態１のアドレス電極配線と走査維持電極配線との駆動例を示す波形図である。
【図８】 この発明の実施の形態２に係るデータドライバの構成を示す図である。
【図９】 図８のデータドライバでの駆動波形を示す図である。
【図１０】 この発明の実施の形態３に係るプラズマディスプレイ装置の駆動回路の構成を示す図である。
【図１１】 この発明の実施の形態４に係るプラズマディスプレイ装置の駆動回路の構成を示す図である。
【図１２】 図１１の高域成分除去フィルタ２の構成を示す図である。
【図１３】 入力画像の空間周波数とフィルタゲインとの関係を示す図である。
【図１４】 図１１の電流検出器８の構成を示す図である。
【図１５】 入力画像の空間周波数とデータドライバの消費電力との関係について従来と実施の形態４の駆動方式の比較を示す図である。
【図１６】 この発明の実施の形態５に係るプラズマディスプレイ装置の駆動方式を説明する概念図である。
【図１７】 この発明の実施の形態６に係るプラズマディスプレイ装置の駆動回路の構成を示す図である。
【図１８】 実施の形態６における駆動方式を説明する概念図である。
【図１９】 この発明の実施の形態７に係るプラズマディスプレイ装置の駆動回路の構成を示す図である。
【図２０】 この発明の実施の形態８に係るプラズマディスプレイ装置の駆動回路の構成を示す図である。
【図２１】 実施の形態８の駆動方式を説明するための図である。
【図２２】 従来のブラズマディスプレイ装置及びその駆動回路を示す図である。
【図２３】 従来のブラズマディスプレイ装置の駆動方法を示す駆動波形図である。
【図２４】 図２２のデータドライバ１９の構成を示す図である。
【図２５】 プラズマディスプレイ装置及びデータドライバの等価回路を示す図である。
【図２６】 従来のプラズマディスプレイ装置のアドレス電極配線の駆動波形の一例を示す図である。
【図２７】 従来の駆動方式におけるデータドライバでの消費電力を説明するための図である。
【図２８】 プラズマディスプレイパネル上での表示例を示す図である。
【図２９】 図２８の表示を行うための従来の駆動波形を示す図である。
【符号の説明】
１ 画像データ（入力画像データ）、２ 高域成分除去フィルタ、３ 画像データ並べ換え部、４ フィルタコントローラ、５ シーケンスコントローラ、６データドライバ電源、８，９１ 電流検出器、９ データドライバ、１０ 維持ドライバ、１１ 走査維持ドライバ、１２ ＰＤＰ（プラズマディスプレイパネル）、１３ アドレス電極配線、１４ 維持電極配線、１５ 走査維持電極配線、１６ 駆動データ、２０，７０ コントローラ、２１ アドレスパルス、２２ 走査パルス、２３ パルス制御回路、２３ａ，２３ｂ，４４ アンド回路、２３ｃ オア回路、２４ シフトレジスタ、２５ ラッチ回路、２９，３０ ＦＥＴ、３２ 立ち上がり遅延回路、３３ 制御信号、４０，５０ 遅延回路、４３ コンデンサ、５１ データドライバ（Ａブロック）、５２ データドライバ（Ｂブロック）、６１ ＤＣＴ、６２ 高域成分除去部、６３ ＩＤＣＴ、７２ドライバ電力予測演算、８０ 電流検出抵抗、９２ ドライバブロック、９３最大値検出器。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving circuit for a matrix display device such as a plasma display panel, a liquid crystal display panel, or an electroluminescence panel, and more particularly to a driving circuit having a function for reducing power consumption.
[0002]
[Prior art]
FIG. 22 is a schematic configuration diagram of a driving circuit of a conventional alternating current (AC) type plasma display, and FIG. 23 is an example of a driving waveform of the plasma display.
[0003]
A plasma display panel (hereinafter referred to as PDP) 12 has a plurality of discharge cells arranged in a matrix. Each discharge cell has its discharge / non-discharge controlled by the address electrode wiring 13 and the scan sustain electrode wiring 15 and the sustain electrode wiring 14 orthogonal to the address electrode wiring 13 to obtain a desired light emitting display image as the entire panel 12. .
[0004]
The odd-numbered (W1, W3... W2n-1) and even-numbered (W2, W4... W2n) of the address electrode wiring 13 are connected to different data drivers 19, respectively. Further, the scan sustaining electrode lines Y1, Y2,... Yi (15) are connected to the scan sustaining driver 11, and the sustaining electrode lines X1, X2... Xi (14) are connected to the sustaining driver 10, and these electrode wirings W, Y and X are driven by corresponding drivers 19, 11, and 10, respectively.
[0005]
The input image data 1 supplied from the outside is supplied to the controller 20, and the controller 20 rearranges the input image data 1 in an order suitable for the display of the plasma display panel, and discharge / non-discharge of each discharge cell of the display. Drive data 16 indicating discharge is created and output to the data driver 19.
[0006]
The two data drivers 19 sequentially apply address pulses 101 as shown in FIG. 23 to the address electrode wirings W1, W2,... W2n−1, W2n based on the drive data 16 as drive signals.
[0007]
Simultaneously with the application of the address pulse 101, the scan pulse 102 is sequentially applied to the scan sustaining electrode wirings 15 (Y1 to Yi) of the corresponding discharge cells, and information on light emission / non-light emission to each discharge cell of the PDP 12 is obtained. Is written. Subsequently, sustain pulse 103 is alternately applied to sustain electrode line 14 and scan sustain electrode line 15 to maintain the discharge state, and a desired image is emitted and displayed on PDP 12.
[0008]
Next, the configuration and operation of the data driver 19 in FIG. 22 will be described with reference to FIG.
[0009]
The drive data 16 output as serial data from the controller 20 is sequentially supplied to the shift register 124, where it is converted into parallel data (parallel drive data S1, S2,... Sm) and output toward the latch circuit 125. The When the latch enable signal LE supplied to the latch circuit 125 is turned on (for example, H level), the latch circuit 125 latches the output from the shift register 124, and the latched drive data S 1 to Sm are latch data 131. (L1 to Lm) are supplied to the corresponding level shifter 126, the FET drive buffer 127, and the inverting FET drive buffer 128, respectively, and on / off of the field effect transistors (FETs) 29 and 30 constituting the totem pole circuit via these. Control. By controlling the FETs 29 and 30 in this manner, a voltage of Vw or 0 V is output from the output terminals O1 to Om of the totem pole circuit, and this output is applied to the corresponding address electrode wiring 13 as an address pulse. It will be.
[0010]
[Problems to be solved by the invention]
In a conventional driving circuit for a matrix display device such as a plasma display, a display image is obtained by driving a load that is a capacitive component such as a discharge cell or a liquid crystal by electrode wiring arranged in a matrix on a substrate as described above. Yes. For this reason, in terms of an equivalent circuit, a capacitance component is formed between the electrode wirings adjacent to each other, and it is difficult to keep the power consumption of the data driver low because of charge / discharge of the capacitance component described later. There was a problem.
[0011]
In addition, when the display image becomes finer and, further, for example, an image including a lot of high-frequency components such as a staggered pattern is displayed, the charge / discharge amount of the capacitance component is further increased according to the principle described later. Power consumption in the driver increases. As described above, the power consumption of the data driver is determined according to the input image data, and there is a second problem that it cannot be suppressed within a predetermined range.
[0012]
The relationship between the capacitance component between the electrode wirings and the power consumption in the data driver, which is the first problem, will be described below with reference to FIGS. FIG. 25 shows an output circuit of the data driver 19 of FIG. 22 and an equivalent circuit on the PDP 12.
[0013]
When viewed from the data driver 19 side, the PDP 12 has a capacitance Cw between the address electrode wires W and a capacitance Cxy between the sustain electrode wires X and the scan sustain electrode wires Y. The values of the capacitances Cw and Cxy vary depending on the panel size of the PDP 12, the layout of the electrode wiring, etc. For example, in the case of a 100 cm diagonal (40 type) plasma display panel, the capacitances Cw and Cxy are both It is about several tens of pF.
[0014]
In such a configuration, when the output O of the data driver 19 is switched between 0 V and Vw, charging and discharging are performed with the capacitances Cxy and Cw, and power is consumed in the data driver 19 along with this charging and discharging. The
[0015]
The energy consumed by charging / discharging in the capacitances Cxy and Cw can be estimated as follows.
[0016]
First, the energy consumed by charging / discharging the capacitance Cxy is as follows.
[0017]
When the voltage Vw is applied to the address electrode wiring W and the capacitance Cxy is charged, the driver power supply of the data driver 19 receives Cxy · Vw. ² Energy is output, of which (Cxy · Vw ² ) / 2 is accumulated in the capacitance Cxy, and the remaining (Cxy · Vw) ² ) / 2 is consumed in the data driver 19.
[0018]
Further, when the electrostatic capacity Cxy was discharged, it was accumulated in the electrostatic capacity Cxy (Cxy · Vw). ² ) / 2 energy is drawn into the data driver 19 and consumed there.
[0019]
Therefore, at the time of switching to the discharge cell once, both when the address pulse rises and when it falls, per one capacitance cxy (Cxy · Vw ² ) / 2 energy is consumed.
[0020]
Next, energy consumption by charging / discharging the electrostatic capacity Cw is as follows.
[0021]
As shown in FIG. 26, regarding the energy consumed by charging / discharging the electrostatic capacitance Cw, the address pulse applied to the address electrode wiring W corresponding to each output of the data driver 19 rises at the electrode wiring Wk. Consider a case where the electrode wiring Wk + 1 falls adjacent to the electrode wiring Wk simultaneously with the timing.
[0022]
Before the output of the data driver 19 is switched, the voltage Vw is applied to the capacitance Cw in the direction in which the electrode wiring Wk + 1 is positive, as shown in FIGS. 26 (a) and 27 (a). Is charged.
[0023]
From this state, when the output of the data driver 19 is switched, the electrode wiring Wk changes from 0 to Vw, and the electrode wiring Wk + 1 changes from Vw to 0, a current flows as shown by an arrow in FIG. The capacitance Cw is charged by applying a voltage Vw in a direction in which the electrode wiring Wk is positive. At this time, the amount of charge flowing from the driver power source into the capacitance Cw is 2 (Cw · Vw). The energy supplied from the driver power supply is (power supply voltage) × (charge amount), and as is clear from FIG. 27B, this energy is all consumed in the data driver 19.
[0024]
In other words, 2 (Cw · Vw) per capacitance Cw in one switching. ² ) Energy is consumed. For this reason, for example, when the electrostatic capacitance Cxy and the electrostatic capacitance Cw are the same value, the energy consumed by the electrostatic capacitance Cw is four times as much as the energy consumption by Cxy.
[0025]
As described above, the data driver 19 consumes energy each time the output is switched, and particularly includes a lot of high frequency components that are alternately switched on / off in adjacent pixels as described below. When an image is displayed, energy loss due to charging / discharging in the electrostatic capacity Cw between the address electrode wirings W becomes extremely large.
[0026]
Hereinafter, the relationship between the pattern of the display image, which is the second problem, and the power consumption in the data driver will be described with reference to FIGS. 25, 28, and 29. FIG. 28 shows lighting (with hatching) / non-lighting (without hatching) in each discharge cell of the PDP, and FIG. 29 shows voltage waveforms applied to each electrode wiring when a pattern as shown in FIG. 28 is displayed. Is shown.
[0027]
The address pulse 121 is applied to the address electrode wirings Wk-1, Wk, Wk + 1 according to the pattern to be displayed on each discharge cell, and at the same time, the negative scanning pulse 122 is sequentially applied to the scan sustaining electrode wirings Yl-1, Yl, Yl + 1. By applying, lighting / non-lighting data corresponding to the display image pattern is written in each discharge cell.
[0028]
Here, paying attention to the timing of tl, since the voltage applied to the address electrode wiring Wk changes from Vw (about 60 V) to 0, the charge (Cxy · Vw) accumulated in the capacitance Cxy is addressed. It flows into the data driver 19 from the electrode wiring Wk. Further, the charge of (Cw · Vw) flows from the address electrode wiring Wk + 1 through the electrostatic capacitance Cw toward the address electrode wiring Wk. Further, in the address electrode wiring Wk-1, the applied voltage is changed from 0 to Vw as opposed to the address electrode wiring Wk. Therefore, the address electrode wiring Wk-1 passes through the electrostatic capacitance Cw and 2 (Cw · The charge of Vw) flows toward the address electrode wiring Wk and is consumed by the data driver 19. As described above, at the timing tl, the power represented by the following expression (1) is consumed by the address electrode wiring Wk, that is, the data driver 19.
[0029]
[Equation 1]
(Cxy + 3 × Cw) × Vw ² / 2 (1)
On the other hand, at the instant of timing t + 1, as shown in FIG. 28, since the display patterns of the 1st row and the 1 + 1st row are the same, the potential of each address electrode wiring does not change. Therefore, at the timing of tl + 1, no current flows into the data driver 19 and no power is consumed.
[0030]
As described above, power is consumed by charging / discharging Cw and Cxy every time the address pulse output from the data driver 19 is switched, so that a finer pattern image is input and displayed. That is, as the high frequency component of the input image increases, the number of times the output of the data driver 19 is switched increases, and the power consumption increases correspondingly. And no method has been proposed for alleviating the increase in power consumption according to such display images. In addition, the increase in power consumption causes heat generation in the data driver 19, which necessitates the driver to take measures against heat generation, which causes an increase in cost.
[0031]
As described above, in the conventional drive circuit, the power consumption in the driver due to the capacitance between the adjacent electrode wirings is large, and the power consumption in such a driver is kept within a predetermined range. I couldn't.
[0032]
The present invention has been made to solve the above-described problems, and a first object is to exist between electrode wirings in a column or row direction to which a driving signal is applied in a driving circuit of a matrix display device. It is to reduce power consumption due to capacitance.
[0033]
The second object is to suppress the power consumption in the drive electrode driver within a certain range.
[0034]
[Means for Solving the Problems]
This invention AC type comprising a plurality of data lines for transmitting a lighting signal to the discharge cells, and a data driver having a respective data line driving unit connected to each of the plurality of data lines for applying the respective lighting signals. A driving circuit of a matrix display device of a plasma display, wherein each data wiring driving unit of the data driver inputs the respective lighting signals and has a rising latch enable signal and a falling latch having a difference in timing with each other An enable signal, and when the input lighting signal is at a high level, a data latch enable signal is output at the timing of the rising latch enable signal, and the input lighting signal is at a low level. In the case of, the falling latch enable The data driver comprises a pulse control circuit that outputs a data latch enable signal at the timing of the signal, and a latch circuit that latches the respective lighting signals at the timing of the data latch enable signal output from the pulse control circuit. Is a timing of a rising latch enable signal input to a pulse control circuit of a data wiring driving unit connected to the data wiring, or a lighting signal to be applied to the data wiring according to the signal level of the lighting signal or Delay until falling latch enable signal timing It is characterized by this.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0047]
Embodiment 1 FIG.
What is characteristic in the first embodiment is that adjacent drive electrodes are applied to electrode wirings for driving each pixel of a matrix display device such as a plasma display, a liquid crystal display device, and an EL (electroluminescence) display. Control is performed so that the drive signal rise and fall timings deviate between the electrode wirings.
[0048]
FIG. 1 shows a schematic configuration of a driving circuit of the plasma display apparatus according to the first embodiment.
[0049]
In FIG. 1, when input image data 1 is supplied from the outside, this is supplied to the image data rearrangement unit 3 in the driver controller 20. The image data rearrangement unit 3 rearranges the input image data 1 in an order suitable for display on the plasma display, and supplies drive data 16 indicating discharge / non-discharge of each discharge cell of the display to the two data drivers 9 respectively. Output. However, the data driver 9 may have a single configuration.
[0050]
Based on the drive data 16, the data driver 9 generates drive signals as address signals for the address electrode wirings W 1, W 3... W 2 n-1 and W 2, W 4. An address pulse is applied to determine whether each discharge cell is turned on or off.
[0051]
In the first embodiment, as will be described later, a rise delay circuit is provided in the data driver 9 as a signal application timing control means, whereby the rise and rise of the address pulse applied to the adjacent address electrode wiring 13 is provided. Control so that the falling timing is shifted.
[0052]
In addition, the sequence controller 5 provided in the controller 20 applies the scanning signal to the scanning electrode wiring of the corresponding matrix display device and the scanning sustaining electrode wiring 15 (Y1 to Yi) in the plasma display device simultaneously with the application of the address pulse. A scan pulse is applied, and lighting / non-lighting information is written in each discharge cell of the PDP panel 12. Further, sustain pulses are alternately applied to the sustain electrode lines 14 and the scan sustain electrode lines 15, and a desired image is emitted and displayed on the PDP 12.
[0053]
Next, the configuration and operation of the data driver 9 in FIG. 1 will be described with reference to FIG.
[0054]
When the drive data 16 is output as serial data from the controller 20, it is sequentially supplied to the shift register 24 and converted into parallel data. Next, parallel drive data S1, S2,... Sm are output to the latch circuit 25. When the supplied latch enable signal LE is turned on (for example, H level), the latch circuit 25 shifts accordingly. The output from the register 24 is latched, and the latched drive data S1 to Sm are output as latch data L1 to Lm, respectively.
[0055]
Each latch data output path of the latch circuit 25 is provided with a rising delay circuit 32 as signal application timing control means, and delays only the rising edge of the latch data L1 to Lm. The rising delay circuit 32 can be realized with a simple configuration as shown in FIG. 5, for example, and with such a circuit configuration, a signal (output OUTb) in which only the rising edge of the latch data pulse is delayed as shown in FIG. 6 is obtained. .
[0056]
The rising delay circuit 32 shown in FIG. 5 includes a delay circuit 40 that delays latch data output from the latch circuit 25 and an AND circuit 44. The delay circuit 40 includes buffers 41 and 42 and a capacitor 43, and delays the input INa as latch data by td as shown in FIG. 6 and uses this as a delay circuit output (OUTa) as one input of the AND circuit 44. Supply to the end. Latch data (input INa) is directly supplied to the other input terminal of the AND circuit 44. The AND circuit 44 ANDs the latch data without delay and the data delayed by td, and as a result, a signal in which only the rising edge of the pulse is delayed by td is output from the AND circuit 44 as shown in the output OUTb of FIG. Is done.
[0057]
The latch data L1 to Lm delayed in the rise timing in the rise delay circuit 32 in this way are supplied to the corresponding level shifter 26, FET drive buffer 27, and inverted FET drive buffer 128, respectively, and through these totems Electricity that constitutes a pole circuit World On / off of the effect transistors (FETs) 29 and 30 is controlled. As a result, a voltage of Vw or 0 V is output from each of the output terminals O1 to Om of the totem pole circuit, and this output, that is, an address pulse delayed in rising timing, is applied to the corresponding address electrode wiring 13.
[0058]
The data driver 9 is formed by integrating circuit blocks as shown in FIG. 2, but actually, an integrated circuit is formed for each output of about several tens of bits, and a combination of these is used to display one sheet. Often drives the panel.
[0059]
Next, the operation of reducing the power consumption in the data driver 9 according to the first embodiment will be described with reference to FIGS.
[0060]
As described above, in the data driver 9, the rising edge of the address pulse applied to each address electrode wiring W is delayed. Therefore, when attention is paid to the address electrode wirings Wk and Wk + 1 arranged adjacent to each other on the PDP 12, the address pulse in each electrode wiring has a voltage waveform as shown in FIG. 3, for example. The timing of the rising edge of the address pulse and the falling edge of the other address pulse are shifted by td. This timing shift td is set to be substantially equal to the period required for the rising and falling of the address pulse, so that the rising and falling timings of the address pulse are surely shifted between adjacent electrode wirings. It becomes possible. The deviation td can be easily changed by adjusting the capacitance of the capacitor 43 of the delay circuit 40.
[0061]
In the period (a) of FIG. 3, when the address electrode wiring Wk is 0 V and the adjacent address electrode wiring Wk + 1 is Vw, the capacitance Cw between the electrode wirings is the address electrode as shown in FIG. The wiring Wk + 1 side is charged so as to be positive.
[0062]
Assume that the address electrode wiring Wk + 1 falls from Vw to 0 V in the period (b) of FIG. Conventionally, the address electrode wiring Wk changes from 0 V to Vw at the same timing as the change of the address pulse of the address electrode wiring Wk + 1. However, in the first embodiment, the rise timing of the pulse is delayed. Therefore, the address pulse of the address electrode wiring Wk does not change during this period (b). Therefore, in the capacitance Cw, only the address electrode wiring Wk + 1 side changes from Vw to 0 V, current flows in the direction as shown in FIG. 4B, and the capacitance Cw is discharged (Cw・ Vw ² ) / 2 power is consumed by the data driver 9.
[0063]
When the address pulse of the address electrode wiring Wk rises from 0 to Vw during the period (c), a current flows and the capacitance Cw is charged as shown in FIG. At this time, Cw / Vw from the driver power supply ² Of energy, of which (Cw · Vw ² ) / 2 is accumulated in the capacitance Cw, and the remaining (Cw · Vw) ² ) / 2 is consumed in the data driver 9.
[0064]
As is clear from the above description, by controlling as in the first embodiment, Cw · Vw per one capacitance Cw in the switching operation of one address pulse. ² Of power will be consumed. And this consumption is the conventional (2 × Cw · Vw ² The power consumption of the data driver 9 can be surely reduced by delaying the rising timing of the address pulse. However, since the power consumption due to charging / discharging to / from Cxy is the same as the above-described calculation, the description is omitted here.
[0065]
In the above description, only the rising timing of the address pulse is delayed. However, the timing is not necessarily limited to the rising timing, and the falling timing may be delayed. That is, from the viewpoint of reducing the power consumption of the data driver 9, in the adjacent address electrode wiring, if the timing of rising and falling of each address pulse does not coincide, either rising or falling may be first.
[0066]
However, the falling edge of the address pulse is better in view of the characteristics of the display panel. That is, it is more preferable to delay the rising timing of the address pulse than to delay the falling timing. This is because when the fall timing is delayed, the other address pulse rises before the one address pulse falls between the adjacent address electrode wires, and the output of the two electrode wires becomes the H level. This is because if this timing further overlaps with the scanning pulse, a malfunction may occur in which the two discharge cells related to both electrode wirings are in a light emitting state.
[0067]
Further, in order to minimize the malfunction in the display panel, as shown in FIGS. 7A and 7B, the falling of the address pulse 21 is performed first, and FIGS. As shown in d), it is preferable to align the rising edge of the address pulse 21 and the application timing of the scan pulse 22 to the scan sustain electrode wiring Y (15). This can be realized, for example, by providing a delay circuit 40 similar to that shown in FIG. 5 in the scan maintaining driver 11 and delaying the rising and falling timings of the scanning pulse 22 by the same amount as the rising timing td of the address pulse 21.
[0068]
Embodiment 2. FIG.
Next, Embodiment 2 will be described with reference to FIGS. The overall drive circuit configuration of the plasma display device is the same as that shown in FIG. In the following description of the present embodiment, the same reference numerals are given to the same components as those already described, and the description thereof is omitted.
[0069]
In the second embodiment, the rising and falling timing of the address pulse applied to the address electrode wiring 13 is controlled by an external signal. Specifically, a pulse control circuit 23 as shown in FIG. 8 is provided as a signal application timing control means, and this circuit 23 is controlled by external control signals (rising latch enable signal LE, falling latch enable signal LE). To do.
[0070]
The pulse control circuit 23 includes two AND circuits 23a and 23b, and an OR circuit 23c that takes the output of the two AND circuits and outputs the result. Outputs corresponding to outputs S1 to Sm from the shift register are supplied to the inverting input terminal of the AND circuit 23a and one input terminal of the AND circuit circuit 23b. A falling latch enable signal LE is supplied to the non-inverting input terminal of each AND circuit 23a, and a rising latch enable signal LE is supplied to the other input terminal of the AND circuit 23b. Further, the output of the corresponding OR circuit 23c is supplied as a latch enable signal LE to the latch control terminal of the latch circuit 25 that latches the output data from the shift register 24, respectively. The latch circuit 25 latches the output signal from the shift register 24 when the signal LE is turned on.
[0071]
The operation of the data driver 9 of the second embodiment is as follows.
[0072]
Focusing on the predetermined output data Sk and Sk + 1 from the shift register 24, when the output data Sk is at the H level and the output data Sk + 1 is at the L level as shown in FIGS. 9A and 9B, FIG. When the falling latch enable signal LE is turned on (H level) as described above, the output of the (k + 1) -th AND circuit 23a that receives the output data Sk + 1 becomes H, and this becomes the H level latch enable from the OR circuit 23c as it is. The signal LEk + 1 is applied to the corresponding (k + 1) th latch circuit 25. For this reason, the (k + 1) th latch circuit 25 latches the L level output Sk + 1 of the shift register, and the output Ok + 1 of the totem pole circuit becomes L level as shown in FIG. 9 (h).
[0073]
Next, as shown in FIG. 9D, when the rising latch enable signal becomes H level, the output of the AND circuit 23b of the kth pulse control circuit 23 becomes H level, and the OR circuit 23c outputs an H level latch enable signal LEk. Applied to the kth latch circuit 25. As a result, the kth latch circuit 25 latches the H level output data Sk as shown in FIG. 9G, and the output Ok rises to the H level.
[0074]
By configuring the data driver 9 as described above, it is possible to selectively control the rising timing (or falling timing) of the address pulse from the outside with a simple configuration. Similarly, power consumption in the data driver can be reduced.
[0075]
In particular, in the second embodiment, unlike the first embodiment, the timing of the address pulse can be controlled from the outside, and therefore the output timing deviation of the address pulse due to the variation of the delay circuit 40 in FIG. Etc. can be eliminated. Furthermore, it is easy to finely adjust the rising and falling timings of the address pulse in accordance with the characteristics of the driving load, that is, the capacitance of the display panel. Therefore, the timing of the address pulse as the drive pulse can be optimized, and the display characteristics on the display can be stabilized.
[0076]
In addition, by using the rising latch enable signal for controlling the output timing of these address pulses as an external signal, this signal can be used as a signal for controlling the output timing of the scan pulse to the scan maintenance driver 11 shown in FIG. More easily, the rising edge of the address pulse can be synchronized with the rising edge of the scanning pulse.
[0077]
Embodiment 3 FIG.
Next, Embodiment 3 will be described with reference to FIG. As shown in the figure, the greatest point of interest in the third embodiment is that the data driver is divided into, for example, two blocks, and the data driver (A block) 51 is odd-numbered address electrode wirings W1 and W3. .. W2n-1 is driven, and the data driver (B block) 52 is driving even-numbered address electrode wirings W2, W4, and W2n.
[0078]
That is, in the third embodiment, since the two data drivers 51 and 52 drive adjacent address electrode wirings on the PDP 12, the two data drivers 51 and 52 output address pulses at different timings. By controlling in this way, it is possible to automatically shift the rising / falling timing of the applied drive electrode between adjacent drive electrode wirings.
[0079]
Specifically, a delay circuit 50 is provided as a signal application timing control means, and this is provided in the output wiring path of the latch enable signal supplied from the controller 20 to one of the data drivers 51 and 52 (this embodiment). 3, the latch timing in the latch circuit in one of the data drivers 51 and 52 is delayed.
[0080]
As a result, the output timing of the address pulse from one data driver (in this case, the data driver 52) is delayed so that the rising timing and falling timing of the address pulse do not coincide between the adjacent address electrode wirings on the PDP 12. Is controlling.
[0081]
As described above, in the third embodiment, it is not necessary to manufacture an integrated circuit exclusively as a data driver and use it as in the above embodiment, and it corresponds to either one of the data drivers that drive the adjacent address electrode wiring. Thus, the power consumption of the data driver can be reduced to the same extent as in the first embodiment only by providing the delay circuit 50.
[0082]
Embodiment 4 FIG.
For example, when an image including a high frequency component in which lighting / non-lighting is switched for each pixel is displayed on the PDP, as is apparent from FIGS. 28 and 29, inversion of the address pulse frequently occurs. As described above, the power consumption of the data driver increases due to the capacitance Cw between the electrode wirings.
[0083]
Therefore, in the fourth embodiment, the power consumption of the data driver is detected, and the high frequency component of the original image data (input image data) is removed by the display image control means in accordance with the detected value. Feedback control is performed so that the power consumption is within a predetermined range.
[0084]
FIG. 11 shows a configuration of a driving circuit of a plasma display device for performing such control. The difference from FIG. 1 is that first, as a display image control means for removing the high frequency component of the input image data 1 according to the power consumption of the data driver, the high frequency component is removed from the input image data 1 in the controller 70. A high frequency component removal filter 2 and a filter controller 4 for controlling the filter 2.
[0085]
Further, in the power supply unit 60 of the drive circuit, the current detector 8 is provided as a detecting means for detecting the power consumption of the data driver power supply 6, and the high frequency component is determined according to the detection result 34 by the detector 8. The high frequency component is removed by the removal filter 2.
[0086]
FIG. 12 is a configuration example of the high-frequency component removal filter 2. In the fourth embodiment, a discrete cosine transform (DCT) 61 is provided to perform discrete cosine transform on the input image data 1, and a high frequency component removal unit 62 filters out the obtained spatial frequency component data. Based on the control of the controller 4, the high frequency component is preferentially removed from the high frequency side according to the detection result 34. After the removal, an inverse discrete cosine transform unit (IDCT: Inverse DCT) 63 demodulates the spatial frequency component data into the original format image data. FIG. 13 shows the characteristic (gain) of the high-frequency component removal filter 2 with respect to the spatial frequency of the display image. As shown in FIG. 13, if the data driver power consumption is large as a result of current detection, the filter gain is made lower than the normal value as the spatial frequency of the image increases, and the high frequency component is removed from the input image data. Increase the amount.
[0087]
When the power consumption of the data driver is relatively small, the high frequency component is not removed from the input image to a higher range than when the spatial frequency of the display image is “high”.
[0088]
Next, a configuration example of the current detector 8 will be described with reference to FIG. The current detector 8 shown in FIG. 14 inserts a current detection resistor 80 into the power supply line from the data driver power supply 6 to the data driver 9 and obtains the amount of current based on the voltage drop at the resistor 80. Since the power consumption in the data driver 9 corresponds to the power supplied from the power source 6 to the data driver 9, the power consumption in the data driver 9 based on the current value detected by the power supply line as shown in FIG. Can be detected. If the detection resistor 80 is inserted into the power supply line, the current detection resistor 80 can be configured using an external circuit corresponding to the data driver power supply voltage or the like.
[0089]
Further, since the output voltage of the data driver power supply is as high as about 60 V, for current detection, first, the level shifters 82 and 84 are used to shift to a low voltage to make the voltage low, as shown in FIG. In the differential amplifier 86, the voltage difference is obtained and the current value is obtained. The detection result 34 obtained by the differential amplifier 86 is supplied to the filter controller 4, and the filter controller 4 controls the removal of the high frequency component from the input image data 1 based on the detection result 34 as described above. .
[0090]
FIG. 15 shows a comparative example of the fineness of the original image (the number of high frequency components of the input image) and the power consumption in the data driver in the case of the conventional driving method and the driving method of the fourth embodiment. Show. In the conventional driving method, even if the input image includes a high frequency component, it is displayed on the display as it is. Therefore, as the high frequency component of the input image increases as shown by the dotted line in FIG. As a result, power consumption in the data driver is increasing.
[0091]
On the other hand, in the fourth embodiment, based on the detection result of the current detector 8, as the power consumption in the data driver increases, the high frequency component of the image is removed so that the power consumption does not exceed a certain value. Feedback control. Therefore, as shown by a solid line in FIG. 15, in the fourth embodiment, the peak of power consumption in the data driver can be cut and the power consumption of the data driver can be clamped to a predetermined value or less.
[0092]
In order to clamp the detected power consumption at a predetermined value, the filter controller 4 performs control so that the degree of high-frequency removal in the high-frequency component removal filter 2 is appropriate according to the detected current value. Can be achieved relatively easily.
[0093]
Further, in the fourth embodiment, if an appropriate time constant is given to the response to the current detection result 34 from the current detector 8 in the filter controller 4, the high frequency component is changed with respect to the change of the input image data 1. Removal will follow with a little delay. For this reason, the change in the display image due to the removal of the high frequency component from the input image data 1 can be made difficult to visually understand.
[0094]
As described above, in the fourth embodiment, the high frequency component of the image is removed based on the power consumption in the data driver, and control is performed so that the power consumption does not become excessive. Therefore, a driver circuit with a small maximum allowable loss can also be used as a data driver, and the cost of the driver circuit can be easily reduced. Furthermore, it becomes easy to design heat resistance considering the amount of heat generated by power consumption. In addition, since the high frequency component in the display image data is difficult to be visually detected, it is possible to suppress degradation of image quality due to high frequency component removal relatively small.
[0095]
By the way, in the first to third embodiments described above, the signal application timing control means is provided, and the rising and falling edges of the pulse are set so that the rising and falling edges of the address pulse do not coincide between the adjacent address electrode wirings 13. I have control. Also in the fourth embodiment, the rising delay circuit 32 and the pulse control circuit 23 are provided in the data driver 9 as in the first and second embodiments, or the delay circuit 50 is provided as in the third embodiment. A configuration in which control is performed so as to shift the rising and falling timing of the address pulse between the adjacent address electrode wirings 13 is applicable. As described above, if the timing of the address pulse is controlled and the high frequency component of the image data is appropriately removed so that the power consumption of the data driver does not exceed a certain level, the effect of reducing the power consumption in the data driver 9 is further increased. It becomes possible to make it higher.
[0096]
Embodiment 5. FIG.
In the fifth embodiment, as in the fourth embodiment, the high frequency component of the original image, that is, the input image data is removed based on the current detection result in the data driver power supply 6. A difference from the fourth embodiment is a high-frequency removal method in the high-frequency component removal filter 2 of FIG. In the fourth embodiment, the spatial frequency data of the input image data 1 is obtained by discrete cosine transform to remove high frequency components (see FIG. 12). In contrast, in the fifth embodiment, as shown in FIG. 16, the original image data is divided into blocks of vertical h pixels × horizontal j pixels (h and j are positive integers), and each pixel in each block The high frequency component is removed by converting the image data into common data in the block. Hereinafter, the fifth embodiment will be described with reference to FIGS. 11 and 16.
[0097]
First, the filter controller 4 outputs a control signal 33 to the high-frequency component removal filter 2 based on the current detection value detected by the current detector 8 as in the fourth embodiment. In response to this, the high-frequency component removal filter 2 determines the size (vertical h pixels × horizontal j pixels) of a unit block for sharing image data.
[0098]
For example, when the detected power consumption of the data driver is small, even if the input image data 1 is fine as shown in FIG. 16A, the input image data 1 is displayed as it is on the PDP 12 as display pixel data.
[0099]
When the power consumption of the data driver increases, as shown in FIG. 16B, the high frequency component removal filter 2 decomposes the input image data 1 into, for example, 2 × 2 horizontal blocks, It converts into common data (for example, the lighting / non-lighting state is the same), and thereby removes the high frequency component. Note that lighting / non-lighting for each block can be determined by, for example, majority vote according to the number of lighting / non-lighting in the block in the input image data 1 that is the original image.
[0100]
When the power consumption is further increased, the high-frequency component removal filter 2 decomposes the input image data 1 into larger blocks, for example, 3 × 2 blocks as shown in FIG. Lighting / non-lighting is determined, and an image as shown in the figure is displayed on the PDP 12.
[0101]
Even with the configuration as described above, it is possible to remove the high frequency component of the input image data according to the power consumption of the data driver, and to control the power consumption within a predetermined range while suppressing the deterioration of the image quality. Is possible.
[0102]
Further, in the above-described image processing, when digital RGB image data is displayed, if digital data for each pixel in the same block is preferentially shared in the block from the low bit component (LSB) side. The high frequency component of the image can be removed while minimizing the deterioration of the image quality of the display image, and the power consumption in the data driver 9 can be maintained within a predetermined range.
[0103]
Embodiment 6 FIG.
Next, the sixth embodiment will be described with reference to FIGS. 17 and 18. In the sixth embodiment, when gradation display is performed in a plasma display device, one field (for example, 16.7 ms for a TV screen in the case of television screen display) is divided into a plurality of subfields for display. The subfield gradation display method is used.
[0104]
In the sub-field gray scale display method, as shown in FIG. 18, one field corresponds to the number N of display gray scale bits in order from the highest bit (MSB) side of the number of bits. Field SF2... Sixth subfield SF6 (lowest bit (LSB) side) is assigned (in the sixth embodiment, N = 6). In each subfield, an address period 56 in which address pulses and scanning pulses are applied to each discharge cell to write lighting / non-lighting information in each discharge cell, and display sustaining in which display discharge is maintained by applying a sustain pulse. Period 57. The difference in operation in each of the subfields SF1 to SF6 is the difference in the number of sustain pulses applied during one subfield period, and the number of sustain pulses applied is reduced as the display gradation bit is lowered. ing. Therefore, the power consumption of the data driver in each subfield is a value that does not change so much because there is only a difference in the number of sustain pulses.
[0105]
In the sixth embodiment, when the image display is performed by such a subfield gradation display method, the power consumption of the data driver 9 is increased based on the detected current value in the current detector 8. Depending on the degree, the display is omitted sequentially from the subfield SF6 on the low bit side (LSB) side.
[0106]
In the plasma display device, the sequence controller 5 normally controls the subfield gradation display. Therefore, in the case of the sixth embodiment, the detection result 34 from the current detector 8 is supplied to the sequence controller 5, and the sequence controller 5 serves as the display image control means of the sixth embodiment based on this detection result 34. Control subfield pauses.
[0107]
FIG. 18B shows an example in which the writing operation in the address period 56 and the sustaining operation in the display sustaining period 57 are suspended for the subfield SF6. Thereby, compared with the case where all the subfields SF1 to SF6 are displayed as shown in FIG. 18A, in the case of the same display data, the power consumption in the data driver 9 is set to 5/6 by simple calculation. Is possible.
[0108]
FIG. 18C shows a state where the operations of the two subfields SF6 and SF5 are suspended when the power consumption in the data driver 9 further increases. Therefore, since the subfields SF6 and SF5 are not displayed, the power consumption of the data driver can be reduced to 2/3 by simple calculation as described above as compared with FIG.
[0109]
As described above, according to the driving method according to the sixth embodiment, Current The power consumption of the data driver can be controlled by the detector 8 and the sequence controller 5, and it is not necessary to provide the high-frequency component removal filter 2 and the filter controller 4 as in the fourth and fifth embodiments. Therefore, with a simple configuration, when the power consumption of the data driver is large, the peak of the power consumption of the data driver 9 can be surely reduced by lowering the gray level somewhat.
[0110]
If the sixth embodiment is combined with the configuration of the first embodiment that shifts the rising and falling timing of the address pulse, and the fourth and fifth embodiments that remove the high frequency components of the original image, The power consumption of the data driver can be reduced more reliably.
[0111]
Embodiment 7 FIG.
The feature of the seventh embodiment is not a single current detector 8 as in the fourth, fifth and sixth embodiments, but a plurality of integrated circuits in which circuit blocks constituting the data driver 9 are integrated for each predetermined number. For each, a corresponding current detector is provided. As described above, the data driver 9 is often configured using a plurality of integrated circuits in which circuit blocks as shown in FIGS. 2 and 8, for example, are integrated for each predetermined number of outputs.
[0112]
For this reason, depending on the content of the display image, the power consumption may be different for each integrated circuit or each of a plurality of integrated circuits that can transfer heat to each other, and there may be variations in the allowable range of power consumption. . Therefore, even if the power consumption of the data driver 9 as a whole is within a predetermined allowable range, any of the integrated circuits may exceed the allowable range.
[0113]
Therefore, in the seventh embodiment, each integrated circuit or a plurality of integrated circuits that can transfer heat to each other by proximity arrangement or the like is defined as one driver block, and as shown in FIG. A current detector 91 is provided individually, and a maximum value detector 93 is provided to supply the detection result of each current detector 91 to the maximum value detector 93. Then, when any of the current detection results obtained by each current detector 91 exceeds a predetermined value, the maximum value detector 93 detects this, and the filter controller 4 or the sequence controller 5 in the controller 70 detects this. The detection result 34 is supplied to.
[0114]
In this way, by applying feedback to the high-frequency component removal or subfield removal operation based on the current detection result in the individual driver block 92, control is performed so that any driver block 92 does not exceed the allowable power consumption range. Is possible. Therefore, according to the seventh embodiment, the reliability of the data driver can be further improved.
[0115]
Embodiment 8 FIG.
The feature of the eighth embodiment is based on the input image data 1 supplied to the controller 70 instead of directly detecting the power consumption of the data driver by the current detector as in the fourth to seventh embodiments. Thus, the power consumption in the data driver 9 is predicted. As described with reference to FIGS. 28 and 29, the power consumption in the data driver 9 is determined by the switching of address pulses, that is, the number of switching of the data driver output Om.
[0116]
Therefore, in the eighth embodiment, as shown in FIG. 20, a driver power prediction calculation unit 72 is provided in the controller 70 and the power consumption in the data driver 9 is predicted based on the input image data 1. The prediction result 35 is supplied to the filter controller 4, and when the power consumption is predicted to increase, the filter controller 4 determines this and outputs a predetermined control signal 33 to the high-frequency component removal filter 2. Based on the control signal 33, the high frequency component removal filter 2 removes the high frequency component from the input image data 1 by the same method as in the fourth and fifth embodiments. Note that the sequence controller 5 may be controlled based on the calculation result of the prediction calculation unit 72 to pause some subfields.
[0117]
Next, a method of calculating power consumption in the data driver 9 based on the input image data 1 will be described with reference to FIGS. 21, 25, Table A, and Display B. In FIG. 21, the column direction is the address electrode wiring W, the row direction is the scan sustaining electrode wiring Y, and the intersection D (W, XY) of each electrode wiring represents a matrix-like discharge cell. .
[0118]
When the display of the discharge cells D (k, l-1) and D (k, l) changes as shown in (1) to (4) of the following table (1), the address electrode wiring Wk and the scan sustaining electrode wiring The power consumption caused by the capacitance Cxy formed by Y and the sustain electrode wiring X is as shown in the column (5) of Table A below.
[Table 1]

[0119]
Next, the power consumption due to the capacitance Cw formed between the address electrode wiring Wk and the adjacent address electrode wiring Wk-1 is as follows. The address pulses applied to the address electrode wirings Wk and Wk-1 are combined as shown in (1) to (16) in Table B below when the l-1 row selection period shifts to the l row selection period. It changes with either. And the power consumption resulting from the electrostatic capacitance Cw in the cases (1) to (16) is as shown in the column (17) of Table B.
[Table 2]

[0120]
As shown in Tables A and B above, the power consumption of the data driver can be obtained for each discharge cell from the change of the address pulse according to the display pattern. Therefore, the driver power prediction calculation unit 72 separately stores, for example, each of the discharge cells D (W, XY) on the display panel based on the lighting / non-lighting information obtained from the input image data 1. If the power consumption is obtained with reference to Tables A and B and the sum is obtained, the data driver power consumption required for writing data for one screen in each discharge cell of the PDP 12 can be obtained.
[0121]
As described above, if the data driver power consumption is predicted and calculated as in the eighth embodiment, and the specific component is removed from the input image data based on the result, the change in brightness of the input image for each field is large. Even in a case, it is possible to prevent the power consumption of the data driver from temporarily exceeding a specified value.
[0122]
In each of the first to eighth embodiments described above, the plasma display device has been described as an example of the matrix display device. However, the present invention is not limited to this, and each drive circuit of a liquid crystal display device or an electroluminescence display device is also used. By adopting the above-described configuration, the power consumption of the drive electrode driver can be reduced or maintained within a certain range. In addition, in the liquid crystal display device and the electroluminescence display device, the drive signal is a signal for determining lighting / non-lighting in each pixel similarly to the address pulse in the plasma display device. It means an electrode wiring to which a drive signal is applied. The scanning signal is a signal indicating more specific display contents (luminance, gradation, etc.) in each pixel, and the scanning electrode wiring is an electrode wiring to which the scanning signal is applied.
[0123]
For example, taking an active matrix liquid crystal display device as an example, the driving electrode wiring corresponds to a gate electrode wiring, the driving signal corresponds to a gate signal, the scanning electrode wiring corresponds to a source or drain electrode wiring, and the scanning signal corresponds to a data signal.
[0124]
【The invention's effect】
As described above, according to the present invention, in the drive circuit of a matrix display device such as a plasma display device, a liquid crystal display device, or an electroluminescence display device, the falling of the drive signal applied to the drive electrode wirings adjacent to each other Since the rising timing is controlled so as to be shifted from each other, it is possible to reduce power consumption in the drive electrode driver due to charge / discharge of capacitance formed between adjacent drive electrode wirings. If the consumption electrodes can be reduced in this way, it is possible to extend the usage time when carrying in a portable display device, and on the other hand, the problem of heat generation can be reduced in realizing a large-screen display device, which is extremely advantageous. . Furthermore, since a drive electrode driver having a low maximum allowable power consumption can be used, the cost of the apparatus can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a plasma display device and a drive circuit thereof according to Embodiment 1 of the present invention.
FIG. 2 is a diagram illustrating a configuration of a data driver 9 of FIG.
FIG. 3 is a diagram showing a drive waveform of an address electrode wiring according to the first embodiment.
4 is a diagram for explaining power consumption in a data driver in the driving method according to the first embodiment. FIG.
5 is a diagram showing a configuration of a rise delay circuit 32 in FIG. 1. FIG.
6 is a diagram showing drive waveforms in the rise delay circuit 32 of FIG.
7 is a waveform diagram showing an example of driving the address electrode lines and the scan sustain electrode lines in the first embodiment; FIG.
FIG. 8 is a diagram showing a configuration of a data driver according to a second embodiment of the present invention.
FIG. 9 is a diagram showing drive waveforms in the data driver of FIG.
FIG. 10 is a diagram showing a configuration of a driving circuit of a plasma display device according to a third embodiment of the present invention.
FIG. 11 is a diagram showing a configuration of a drive circuit of a plasma display device according to a fourth embodiment of the present invention.
12 is a diagram showing a configuration of a high-frequency component removal filter 2 in FIG.
FIG. 13 is a diagram illustrating a relationship between a spatial frequency of an input image and a filter gain.
14 is a diagram showing a configuration of the current detector 8 of FIG.
FIG. 15 is a diagram showing a comparison between a conventional driving method and a driving method according to a fourth embodiment regarding a relationship between a spatial frequency of an input image and power consumption of a data driver.
FIG. 16 is a conceptual diagram illustrating a driving method of a plasma display device according to a fifth embodiment of the present invention.
FIG. 17 is a diagram showing a configuration of a driving circuit of a plasma display device according to a sixth embodiment of the present invention.
18 is a conceptual diagram illustrating a driving method in Embodiment 6. FIG.
FIG. 19 is a diagram showing a configuration of a driving circuit of a plasma display device according to a seventh embodiment of the present invention.
FIG. 20 is a diagram showing a configuration of a driving circuit of a plasma display device according to an eighth embodiment of the present invention.
FIG. 21 is a diagram for explaining a driving method according to an eighth embodiment;
FIG. 22 is a diagram showing a conventional plasma display device and its driving circuit.
FIG. 23 is a driving waveform diagram showing a driving method of a conventional plasma display device.
24 is a diagram showing a configuration of a data driver 19 of FIG.
FIG. 25 is a diagram showing an equivalent circuit of a plasma display device and a data driver.
FIG. 26 is a diagram illustrating an example of driving waveforms of address electrode wirings in a conventional plasma display device.
FIG. 27 is a diagram for explaining power consumption in a data driver in a conventional driving method.
FIG. 28 is a diagram showing a display example on the plasma display panel.
FIG. 29 is a diagram showing a conventional drive waveform for performing the display of FIG.
[Explanation of symbols]
1 image data (input image data), 2 high-frequency component removal filter, 3 image data rearrangement unit, 4 filter controller, 5 sequence controller, 6 data driver power supply, 8, 91 current detector, 9 data driver, 10 sustain driver, 11 Scan sustain driver, 12 PDP (plasma display panel), 13 address electrode wiring, 14 sustain electrode wiring, 15 scan sustain electrode wiring, 16 drive data, 20, 70 controller, 21 address pulse, 22 scan pulse, 23 pulse control circuit , 23a, 23b, 44 AND circuit, 23c OR circuit, 24 shift register, 25 latch circuit, 29, 30 FET, 32 rising delay circuit, 33 control signal, 40, 50 delay circuit, 43 capacitor, 51 data driver (A block) ), 52 de Motor driver (B block), 61 DCT, 62 high frequency component removing unit, 63 IDCT, 72 driver power prediction calculation, 80 current sensing resistor, 92 driver block, 93 a maximum value detector.

Claims (1)

A plurality of data lines for transmitting a lighting signal to the discharge cells;
A data driver having a respective data line driver connected to apply each of the lighting signals to each of the plurality of data lines;
A drive circuit for a matrix display device of an AC type plasma display comprising:
Each data wiring driver of the data driver is
Each of the lighting signals is input, and a rising latch enable signal and a falling latch enable signal having a difference in timing are input. When the input lighting signals are at a high level, the rising signals are input. A pulse control circuit that outputs a data latch enable signal at the timing of the latch enable signal, and outputs a data latch enable signal at the timing of the falling latch enable signal when each of the inputted lighting signals is at a low level;
A latch circuit that latches each of the lighting signals at the timing of the data latch enable signal output from the pulse control circuit;
Consists of
The data driver is a rising latch enable signal that is input to a pulse control circuit of a data line driving unit connected to the data line, in accordance with a signal level of the lighting signal. A drive circuit for a matrix display device, wherein the delay time is delayed until the timing of the falling latch enable signal .

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