JP4107196B2 - Physical random number generator and physical random number generator - Google Patents

Description

  The present invention relates to a physical random number generator and a physical random number generator suitable for use in various applications. Specific examples of the application include security, encryption, authentication, locking, encrypted communication, smart card (for example, , Electronic money, credit card, examination ticket), home security, car security, keyless entry, probability, lottery, game, amusement (eg, pachinko, pachislot), simulation (eg, Monte Carlo in weather, academic calculation, stock price), graphics (For example, CG, automatic music), control, measurement, FA, robot control (artificial intelligence), and the like.

Conventionally, as a physical random number generator of this type, as disclosed in Patent Document 1, for example, a physical unit composed of a phase adjustment unit including two delays and a selector, a flip-flop, and a feedback circuit One with a random number generator is known.
JP 2003-29964 A

  However, this requires two delays and selectors corresponding to the two signal lines input to the clock terminal and the data terminal of the flip-flop, so that the scale of the phase adjustment unit, and hence the physical random number generator, is increased. In addition to an increase in the area occupied, the power consumption increases. In particular, when a physical random number generator is incorporated in many functions such as CPU (Central Processing Unit), ROM (Read Only Storage Device), RAM (Read / Write Storage Device) and IC (Integrated Circuit), It is strongly desired to reduce the area occupied by the physical random number generator as much as possible.

  In view of such circumstances, an object of the present invention is to provide a physical random number generator with a small occupation area and low power consumption, and a physical random number generator incorporating the physical random number generator.

  First, the invention according to claim 1 of the present invention is an integration circuit that integrates a clock signal with a resistor and a capacitor and outputs an integrated waveform, a noise source, and a noise signal that is amplified by the noise of the noise source and is output. Each of the edges, an amplifier for mixing the integrated waveform and the noise signal, and two edge detection circuits for detecting the first edge of jitter generated based on the output waveform of the mixer. A flip-flop that outputs “0” or “1” based on the phase difference of the output signal of the detection circuit, a delay that adjusts the phase of the input signal input to each integration circuit, a first selector, and an up / down A phase adjustment unit comprising a down counter is provided so that “0” or “1” output from the flip-flop converges to 50%. In the physical random number generator provided with a feedback circuit that feeds back the output of the flip-flop to the phase adjustment unit, a second selector and a third selector are provided in the preceding stage of each integrating circuit, respectively, and the maximum of the up / down counter is provided. A polarity switching circuit is provided for switching the polarity of the input to the first selector, the second selector, and the third selector by the upper bits.

  The invention according to claim 2 of the present invention includes one integration circuit that integrates a clock signal with a resistor and a capacitor and outputs an integrated waveform, a noise source, and a noise generated by amplifying the noise of the noise source. Two amplifiers for outputting a signal, a mixer for mixing the integrated waveform and the noise signal, and two edge detection circuits for detecting the first edge of jitter generated based on the output waveform of the mixer, In a physical random number generator having a flip-flop that outputs “0” or “1” based on the phase difference between the output signals of the edge detection circuits, the phase of the input signal input to the flip-flop is adjusted. A variable delay composed of a delay and a selector is provided before or after each edge detection circuit, and is output from the flip-flop. "Or" 1 "is configured to output of the flip-flop so as to converge to the 50% respectively provided a feedback circuit for feeding back to the variable delay.

  According to a third aspect of the present invention, an FET is added in parallel with the capacitor of the integration circuit in the subsequent stage of the resistance of the integration circuit.

  According to a fourth aspect of the present invention, a constant current circuit is provided in place of the resistor of the integrating circuit.

  Furthermore, in the invention according to claim 5 of the present invention, two or more physical random number generators are connected in parallel, and the parallel physical random numbers input to each of the physical random number generators are rearranged into serial physical random numbers and output. It is constructed in this way.

  According to the invention according to claim 1 of the present invention, since the number of gates can be reduced by halving the delay and the first selector, the scale of the physical random number generator is reduced and the occupied area is reduced, The power consumption can be reduced.

  According to the second aspect of the present invention, only one integrating circuit is required for the two signal lines, and the phase adjustment range due to errors in the resistors and capacitors constituting the integrating circuit is narrowed. Therefore, since the variable delay can be reduced and the number of gates can be reduced, the physical random number generator can be reduced in size to reduce the occupied area and reduce the power consumption.

  According to the invention of claim 3 of the present invention, by discharging the charge charged in the capacitor of the integrating circuit and returning the potential to the base point of the integrated waveform, the base point of the integrated waveform, and hence the distribution of jitter can be obtained. It can stabilize and generate good random numbers. In addition, the electric charge charged in the capacitor of the integration circuit is discharged at high speed, and the electric potential also returns to the base point of the integrated waveform at high speed. Since the potential can be forcibly lowered to the base point without waiting for it to rise, the time can be further shortened, and the random number generation speed can be greatly increased.

  Further, according to the invention according to claim 4 of the present invention, the integral waveform at the time of charging of the capacitor constituting the integrating circuit becomes a straight line, and the distortion of jitter modulated with respect to noise is eliminated, so that the quality of random numbers is improved. Can be made.

  Furthermore, according to the fifth aspect of the present invention, the quality of the random number of the physical random number generator comprising a plurality of physical random number generators can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing a first embodiment of a physical random number generator according to the present invention,
2 is a circuit diagram showing details of an edge detection circuit of the physical random number generator shown in FIG.
FIG. 3 is a diagram showing operation waveforms of the physical random number generator shown in FIG.

  In this physical random number generator 1, as shown in FIGS. 1 and 3, an integration circuit 5 that integrates a clock signal with a resistor R and a capacitor (capacitor) C and outputs an integrated waveform, a noise source 6, An amplifier 7 that amplifies noise from the noise source 6 and outputs a noise signal, a mixer 8 that mixes the integrated waveform and the noise signal, and a first edge of jitter generated based on the output waveform of the mixer 8 is detected. Two edge detection circuits 9 are provided. Each of the edge detection circuits 9 has a circuit configuration as shown in FIG. 2, and a phase difference between the output signals of the edge detection circuits 9 is shown in the subsequent stage of the edge detection circuit 9 as shown in FIG. A D-type flip-flop 10 that outputs “0” or “1” based on this is provided. Further, a D-type flip-flop 11 that synchronizes a random number with a clock signal is provided at the subsequent stage of the flip-flop 10.

  In addition, a phase adjustment unit 2 that adjusts the phase of the input signal input to each integration circuit 5 is provided at the forefront of the physical random number generator 1. The phase adjustment unit 2 includes a delay 21 and a first selector. 22 and an up / down counter 23.

  Further, a feedback circuit 3 is provided between the output of the flip-flop 11 and the up / down counter 23, and “0” or “1” output from the flip-flop 11 converges to 50%. Thus, the output of the flip-flop 11 is fed back to the phase adjustment unit 2. That is, the feedback circuit 3 includes a first counter 31, a comparator 32, a second counter 33, a register 34, a comparator 35, a shift register / register 36, and an adder 37, and the first counter 31 and the comparator 32. Generates a feedback cycle with a random number (2 × m). The second counter 33, the register 34 and the comparator 35 count (n) the number of “0” or “1” in the feedback period (2 × m), and output the comparison data to the up / down counter 23. To output a feedback signal for correcting the uniformity of the random number. Further, the shift register / register 36 and the adder 37 obtain a random number (m) for determining a feedback cycle from the output (OUT). As a result, it is possible to prevent a decrease in the quality of random numbers (癖) due to the feedback period.

  Further, a second selector 15 and a third selector 16 are provided between the phase adjusting unit 2 and each integrating circuit 5, and polarity switching is performed between the first selector 22 and the up / down counter 23. A circuit 13 is provided, and as shown in Table 1, the polarity of the input to the first selector 22, the second selector 15, and the third selector 16 is switched by the most significant bit MSB of the up / down counter 23.

  Therefore, compared to a conventional physical random number generator that requires two delays and selectors corresponding to two signal lines, the number of gates can be reduced by halving the delay 21 and the first selector 22. Therefore, the physical random number generator 1 can be reduced in size to reduce the occupied area and reduce its power consumption.

<Second Embodiment>
FIG. 4 is a circuit diagram showing a second embodiment of the physical random number generator according to the present invention.

  In this physical random number generator 1, as shown in FIG. 4, one integration circuit 5 that integrates a clock signal by a resistor R and a capacitor C and outputs an integrated waveform is provided, and a noise source 6, An amplifier 7 that amplifies the noise of the noise source 6 and outputs a noise signal, a mixer 8 that mixes the integrated waveform and the noise signal, and a first edge of jitter generated based on the output waveform of the mixer 8 Two edge detection circuits 9 for detection are provided. A D-type flip-flop 10 that outputs “0” or “1” based on the phase difference of the output signal of each edge detection circuit 9 is provided at the subsequent stage of these edge detection circuits 9. A D-type flip-flop 11 that synchronizes the random number with the clock signal is provided at the subsequent stage of the flop 10.

  A variable delay 19 including a delay and a selector is provided between the flip-flop 10 and each edge detection circuit 9 (after the edge detection circuit 9), and is input to the flip-flop 10. The phase of the input signal can be adjusted.

  Further, a feedback circuit 3 is provided between the output of the flip-flop 11 and the up / down counter 23, and “0” or “1” output from the flip-flop 11 converges to 50%. Thus, the output of the flip-flop 11 is fed back to the variable delay 19.

  Therefore, in addition to the fact that only one integrating circuit 5 is required for the two signal lines, the phase adjustment range due to the error of the resistor R and capacitor C constituting the integrating circuit 5 can be narrowed. Since the variable delay 19 can be reduced and the number of gates can be reduced, it is possible to reduce the scale of the physical random number generator 1 to reduce the occupied area and reduce the power consumption.

<Other embodiments>
In the second embodiment described above, an FET (field effect transistor) 17 may be added in parallel with the capacitor C after the resistor R of the integrating circuit 5 as shown in FIG. In this case, as shown in FIG. 6, by discharging the charge charged in the capacitor C of the integrating circuit 5 and returning the potential to the base point of the integrated waveform, the base point of the integrated waveform is always stable, and as a result, jitter The distribution of is also stable. Furthermore, stabilization of the jitter distribution leads to generation of high-quality random numbers. The random number generation must wait until the potential returns to the base point, but the charge charged in the capacitor C of the integration circuit 5 is discharged at high speed, and the potential also returns to the base point of the integrated waveform at high speed. The waiting time can be shortened. In addition, since the potential can be forcibly lowered to the base point without waiting for the waveform potential to rise after random number generation, the time can be further shortened (the potential can be returned to the base point immediately after random number generation). ). Thereby, the random number generation speed can be greatly increased. Similarly, in the first embodiment described above, an FET 17 can be added in parallel with the capacitor C after the resistor R of each integrating circuit 5.

  In the second embodiment described above, a constant current circuit 18 may be provided instead of the resistor R of the integrating circuit 5 as shown in FIG. In this case, as shown in FIG. 8, the integrated waveform when the capacitor C is charged becomes a straight line, and the distortion of jitter modulated with respect to noise is eliminated, so that the quality of random numbers is improved. Similarly, in the first embodiment described above, a constant current circuit 18 can be provided instead of the resistor R of each integrating circuit 5.

  Further, as shown in FIG. 9, k physical random number generators 1 described above (k is 2 or more) are connected in parallel, and the parallel physical random numbers input to each physical random number generator 1 are converted into k serial physical random numbers. By rearranging and outputting via an exclusive OR (XOR) element, the quality of the random number of the physical random number generator composed of a plurality of physical random number generators 1 can be improved.

  In the first and second embodiments described above, the case where a D-type flip-flop is used as a flip-flop for generating random numbers has been described. However, the present invention is not limited to this. A flip-flop having a function equivalent to this can be substituted.

  In the above-described second embodiment, as shown in FIG. 4, the case where the variable delay 19 including the delay and the selector is provided in the subsequent stage of the edge detection circuit 9 has been described. You may provide in the front | former stage of 9.

1 is a circuit diagram showing a first embodiment of a physical random number generator according to the present invention. FIG. It is a circuit diagram which shows the detail of the edge detection circuit of the physical random number generator shown in FIG. It is a figure which shows the operation | movement waveform of the physical random number generator shown in FIG. It is a circuit diagram which shows 2nd Embodiment of the physical random number generator which concerns on this invention. It is a circuit diagram which shows another example of an integration circuit. It is a figure which shows the operation | movement waveform of the physical random number generator using the integration circuit shown in FIG. It is a circuit diagram which shows another example of an integration circuit. It is a figure which shows the operation | movement waveform of the physical random number generator using the integration circuit shown in FIG. It is a circuit diagram showing one embodiment of a physical random number generator concerning the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Physical random number generator 5 ... Integration circuit 6 ... Noise source 7 ... Amplifier 8 ... Mixer 9 ... Edge detection circuit 10, 11 ... Flip-flop 2 ... Phase adjustment part 15 ... 2nd Selector 16 …… Third selector 21 …… Delay 22 …… First selector 23 …… Up / down counter 3 …… Feedback circuit 17 …… FET
R …… Resistance C …… Capacitor 18 …… Constant current circuit

Claims (5)

An integration circuit that integrates a clock signal with a resistor and a capacitor to output an integrated waveform, a noise source, an amplifier that amplifies the noise of the noise source and outputs a noise signal, and the integrated waveform and the noise signal are mixed And two edge detection circuits for detecting the first edge of jitter generated based on the output waveform of the mixer,
A flip-flop that outputs "0" or "1" based on the phase difference between the output signals of the edge detection circuits;
A phase adjustment unit comprising a delay for adjusting the phase of an input signal input to each integration circuit, a first selector, and an up / down counter;
In a physical random number generator comprising a feedback circuit that feeds back the output of the flip-flop to the phase adjustment unit so that “0” or “1” output from the flip-flop converges to 50%,
A second selector and a third selector are provided in front of each integrating circuit,
A physical random number generator comprising a polarity switching circuit for switching the polarity of the input to the first selector, the second selector, and the third selector according to the most significant bit of the up / down counter. One integration circuit that integrates the clock signal with a resistor and capacitor and outputs an integrated waveform,
A noise source, an amplifier that amplifies the noise of the noise source and outputs a noise signal, a mixer that mixes the integrated waveform and the noise signal, and a first jitter generated based on the output waveform of the mixer Two edge detection circuits for detecting edges,
In a physical random number generator comprising a flip-flop that outputs “0” or “1” based on the phase difference between the output signals of the edge detection circuits,
A variable delay comprising a delay and a selector for adjusting the phase of the input signal input to the flip-flop is provided in the front stage or the rear stage of each edge detection circuit,
Physical random number generation characterized by providing a feedback circuit that feeds back the output of the flip-flop to the variable delay so that “0” or “1” output from the flip-flop converges to 50%, respectively. vessel. 3. The physical random number generator according to claim 1, wherein an FET is added in parallel with a capacitor of the integration circuit in a subsequent stage of the resistance of the integration circuit. The physical random number generator according to any one of claims 1 to 3, wherein a constant current circuit is provided in place of the resistance of the integration circuit. Two or more physical random number generators according to any one of claims 1 to 4 are connected in parallel, and the parallel physical random numbers input to each of the physical random number generators are rearranged into serial physical random numbers and output. A physical random number generator characterized by the above.

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