JP4075593B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device configured by stacking semiconductor chips on a semiconductor substrate and electrically connecting them, and a method for manufacturing the semiconductor device.
[0002]
[Prior art]
  In order to improve the mounting density of semiconductor devices, attempts to make a semiconductor device (semiconductor package) by stacking a plurality of semiconductor chips such as memories have been conventionally made. In this case, since there is little interference of electrical signals between the stacked semiconductor chips, the semiconductor chips can be stacked easily.
  For example, it has been proposed to stack another IC chip on one IC chip (see, for example, Patent Document 1).
[0003]
[Patent Document 1]
  JP 2001-257310 A (first page, FIG. 1)
[0004]
[Problems to be solved by the invention]
  However, this conventional method of stacking one IC chip and another IC chip has a structure in which the conductor of one IC chip and the conductor of another IC chip are exposed on the same surface. Therefore, since a large number of conductors for electrical connection from each IC chip have to be led out to one surface side, there is a problem that the surface area of the semiconductor device increases.
  Such an IC chip is obtained by dividing a semiconductor wafer into individual pieces. The semiconductor wafer needs a dicing street portion for performing this dicing. However, the dicing street portion is not effectively used to electrically connect each IC chip of the semiconductor device.
  Therefore, the present invention solves the above-mentioned problems, makes it possible to stack the semiconductor chips of one semiconductor wafer on the portion of the other semiconductor wafer, and to make electrical connection reliably by using dicing street effectively. An object of the present invention is to provide a semiconductor device that can be miniaturized and a method for manufacturing the semiconductor device.
[0005]
[Means for Solving the Problems]
  The invention of claim 1 is a semiconductor device comprising a semiconductor chip singulated from a first semiconductor wafer and a portion of a lower substrate singulated from a second semiconductor wafer, the singulated A semiconductor chip includes a plurality of electrode pads and a circuit unit disposed on an upper substrate, an electrical insulating film formed on the upper substrate, on the electrode pad, on the circuit unit, and on an outer periphery of the upper substrate, and the electrode Vias formed in the electrical insulating film on the pad and on the outer periphery of the upper substrate, electrical wiring portions for electrically connecting the electrode pads and the inner periphery of the upper substrate, and connected to the electrical wiring portion A metal post; a buffer layer formed around the metal post; and an external electrode formed with respect to the metal post. The separated lower substrate portion is provided on the lower substrate. Passive and active elements, An electrode pad arranged on peripherals serial lower substrateA bump formed of a conductive paste on the electrode pad;An electrical wiring portion provided in the upper substrate outer peripheral via, and an electrode pad disposed on the lower substrate as a peripheralThe bump is thermocompression bondedThe semiconductor device is characterized in that the individual semiconductor chips are stacked on the part of the lower substrate that is electrically connected and separated.
[0006]
  The semiconductor device according to claim 1 is a first semiconductor wafer.More individualizedSemiconductor chip, second semiconductor waferLower substrate that is more individualizedIt is comprised by laminating | stacking with respect to this part and electrically connecting.
  The semiconductor chip has a wiring pattern. The type of wiring pattern is formed by cutting a semiconductor chip into pieces from a first semiconductor wafer by cutting along a dicing street.
  This semiconductor chip has an electrical insulating film and an electrical wiring part. The electrical insulating film covers the wiring pattern and the dicing street. The electrical wiring section has a hole in the electrical insulation film at a position corresponding to the dicing street.openThus, the conductive via (Via) is formed. The electrical wiring portion is electrically connected to the electrode pad of the wiring pattern with respect to the portion of the second semiconductor wafer.
  Thereby, the first semiconductor waferMore individualizedThe semiconductor chip is the second semiconductor waferLower substrate that is more individualizedA semiconductor chip and a second semiconductor waferLower substrate that is more individualizedThis portion can be electrically connected through the electric wiring portion by effectively utilizing the dicing street portion. For this reason, the surface area of the semiconductor device can be reduced, and the semiconductor device can be miniaturized.
[0007]
  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor chip is the second semiconductor wafer.Lower substrate that is more individualizedIt is mounted face-up on the part of.
[0008]
  The semiconductor chip may be the second semiconductor wafer.Lower substrate that is more individualizedIt is mounted face-up on the part of. As a result, the semiconductor chip becomes the second semiconductor wafer.Lower substrate that is more individualizedFor example, a semiconductor chip having an active circuit and a portion of a second semiconductor wafer having an active element and a passive element circuit can be easily formed. The problem of mutual interference can be prevented.
[0009]
  Claim3The present invention provides a method of manufacturing a semiconductor device in which a semiconductor chip of a first semiconductor wafer and a portion of a second semiconductor wafer are electrically connected by being stacked, and each semiconductor chip of the first semiconductor wafer Forming a groove in a dicing street around the wiring pattern, covering the wiring pattern with an electric insulating film, and forming an insulating film; and forming an electrode on the portion of the electric insulating film corresponding to the electrode pad of the wiring pattern Forming an electrical connection portion in the portion of the electrical insulating film corresponding to the dicing street, and forming an electrical connection portion in the electrode window and the via; and for the electrical connection portion A first piece that forms an external electrode and cuts the semiconductor chip by cutting the dicing street of the first semiconductor wafer. Mounting the separated semiconductor chip on the second semiconductor wafer and electrically connecting the wiring portion of the semiconductor chip to the electrode of the second semiconductor wafer, A second singulation step of separating the second semiconductor wafer portion and the stack of semiconductor chips into pieces by cutting the wafer along the dicing street along with the semiconductor chips. A method for manufacturing a semiconductor device.
[0010]
  According to a third aspect of the present invention, in the groove forming and insulating film forming steps, grooves are formed in the dicing street around the wiring pattern of each semiconductor chip of the first semiconductor wafer, and the wiring pattern is covered with an electric insulating film.
  In the electrical connection part formation step, an electrode window is formed in the part of the electrical insulating film corresponding to the electrode pad of the wiring patternopenA via is formed in the portion of the electrical insulating film corresponding to the dicing street. In the electrical connection portion forming step, a conductive electrical connection portion is formed in the electrode window and the via.
  In the first singulation step, external electrodes are formed on the electrical connection portions and cut at dicing streets of the first semiconductor wafer to divide the semiconductor chips.
  In the second singulation step, the singulated semiconductor chip is mounted on the second semiconductor wafer, and the wiring portion of the semiconductor chip is electrically connected to the electrode of the second semiconductor wafer. Then, in the second singulation step, the second semiconductor wafer is cut along the dicing street along with the semiconductor chips, so that the second semiconductor wafer portion and the semiconductor chip stack are singulated.
  As a result, the semiconductor chip of the first semiconductor wafer is stacked on the second semiconductor wafer portion, and the semiconductor chip and the second semiconductor wafer portion are electrically used by effectively utilizing the dicing street portion through the electric wiring portion. Can be connected. For this reason, the surface area of the semiconductor device can be reduced, and the semiconductor device can be miniaturized.
[0011]
  Claim4The invention of claim3In the method of manufacturing a semiconductor device according to the item 1, in the second singulation step, each of the semiconductor chips is mounted face-up on a portion of the second semiconductor wafer.
[0012]
  Claim4In the second singulation step, the semiconductor chip is mounted face up on the second semiconductor wafer.
  Thus, the semiconductor chip can easily form a circuit on the opposite side of the active circuit of the semiconductor chip with respect to the second semiconductor wafer portion. For example, the semiconductor chip having the active circuit, and the circuit of the active element and the passive element It is possible to prevent the problem of mutual interference with the portion of the second semiconductor wafer having
[0013]
  Claim5The invention of claim4In the method for manufacturing a semiconductor device according to claim 1, the electrical connection between the electrode pad of the semiconductor chip and the electrical wiring portion of the via, the extraction portion of the external electrode with respect to the electrode pad, and the electrical insulating film are: The first semiconductor wafer is formed on the first semiconductor wafer before being divided into individual semiconductor chips.
[0014]
  Claim5Then, the electrical connection portion between the electrode pad of the semiconductor chip and the electrical wiring portion of the via, the lead-out portion of the external electrode with respect to the electrode pad, and the electrical insulating film are in the state of the first semiconductor wafer and are provided in each semiconductor chip. Prior to separation, the first semiconductor wafer is formed.
  Thereby, the electrical connection portion between the electrode pad and the electrical wiring portion of the via, the lead-out portion of the external electrode, and the electrical insulating film can be efficiently formed on the first semiconductor wafer.
[0015]
  Claim6The invention of claim5In the method for manufacturing a semiconductor device according to the item 1, the electric insulating film is an electric insulating resin, and the electric insulating film covers the semiconductor chip.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.
  The embodiment described below is a preferred specific example of the present invention, and thus various technically preferable limitations are given. However, the scope of the present invention is particularly limited in the following description. Unless otherwise stated, the present invention is not limited to these forms.
[0017]
  FIG. 1 shows a first semiconductor wafer (hereinafter referred to as an upper substrate) 1 for manufacturing a semiconductor device of the present invention.
  FIG. 2 shows a second semiconductor wafer (hereinafter referred to as a lower substrate) 2 used for manufacturing the semiconductor device of the present invention.
  The upper substrate 1 shown in FIG. 1 has an orientation flat 1A. The lower substrate 2 shown in FIG. 2 also has an orientation flat 2A.
  The upper substrate 1 shown in FIG. 1 and the lower substrate 2 shown in FIG. 2 respectively have dicing streets 1B and 2B formed in the same position in the vertical direction and the horizontal direction, for example. However, the dicing streets 1B and 2B may be at different positions.
[0018]
  FIG. 3 shows an enlarged portion A of the upper substrate 1 of FIG. 1 as an example. In FIG. 3, the dicing street 1B is formed in the vertical direction and the horizontal direction. Each circuit portion 1C partitioned by the dicing street 1B has an electrode pad 1D. The electrode pads 1D of the adjacent circuit portions 1C are arranged on the peripheral along the dicing street 1B.
  Similarly, the dicing street 2B of FIG. 2 is formed in the vertical direction and the horizontal direction. Although not shown, each circuit unit has a plurality of electrode pads. The electrode pads of the adjacent circuit portions are arranged on the peripheral along the dicing street 2B.
[0019]
  Each circuit portion 1C shown in FIGS. 1 and 3 is an active element circuit having active elements, for example. The circuit unit shown in FIG. 2 is an active passive circuit having an active element and a passive element. The upper substrate 1 shown in FIGS. 1 and 3 is a so-called analog circuit substrate. The lower substrate 2 shown in FIG. 2 is a so-called digital circuit substrate.
  Since the circuit portion of the lower substrate 2 has active elements and passive elements, for example, a matching circuit or a filter used in a high frequency circuit can be configured.
  By laminating the circuit portion 1C of the upper substrate 1 and the circuit portion of the lower substrate 2, a semiconductor device 10 on which a so-called system in package as shown in FIG. 17 is mounted can be configured.
  Orientation flats 1A and 2A shown in FIGS. 1 and 2 show crystal orientation axes.
[0020]
  The electrode pad 1D shown in FIG. 3 and the electrode pad 2D of the lower substrate 2 (not shown) are respectively disposed on the peripheral. The peripherals are arranged in this manner when the semiconductor is wire-bonded and electrically connected to the lead frame to form a semiconductor package after resin sealing, or when bumps are applied to the electrode pads. This is because there is a case where flip chip is formed.
  However, in the embodiment of the present invention, the arrangement of the electrode pads 1D of the circuit portion 1C of the semiconductor chip described later is not changed, and the layout of the electrode pads of the circuit portion of the lower substrate 2 is not changed. By stacking the circuit portion 1C and the circuit portion of the lower substrate 2, a semiconductor device as a system-in-package can be manufactured.
[0021]
  The widths of the dicing streets 1B and 2B shown in FIG. 3 are determined in consideration of the width that can be cut by the dicing blade and chipping. In recent years, in order to improve the profitability in a semiconductor wafer, the thickness of the dicing blade tends to be thin and the width is also narrowed.
  In the embodiment of the present invention, the width of the dicing street can be suppressed to, for example, about 150 μm by setting the via diameter described later to, for example, 30 μm. Further, the deterioration of the profitability in the semiconductor wafer can be suppressed to 10%, for example, and the arrangement of the electrical wiring portion using the via is facilitated.
[0022]
  Next, a method for manufacturing a semiconductor device of the present invention will be sequentially described with reference to FIG.
Reference is first made to FIG. FIG. 4 shows a partially omitted cross-sectional structure of the upper substrate 1.
A plurality of semiconductor chips 30 are arranged at intervals on the surface 20 of the upper substrate 1. These semiconductor chips 30 have a circuit portion 1C (also referred to as a circuit pattern) shown in FIG.
The circuit unit 1C of the semiconductor chip 30 has a plurality of electrode pads 1D and a passivation film 31. The passivation film 31 is formed so as to cover the surface 20 and the electrode pad 1D. However, the electrode pad 1 </ b> D is exposed to the outside through the opening 33 of the passivation film 31.
  The upper substrate 1 having a plurality of semiconductor chips 30 is prepared as shown in FIG.
[0023]
  Groove formation and insulating film formation step ST1
  In the trench formation and insulating film formation step ST1 shown in FIG. 18, the steps shown in FIGS. 5 to 7 are performed.
  The electrode pads shown in FIGS. 4 and 5 are made of, for example, Al or Au. The passivation film 31 covers the electrode pad 1D and its peripheral circuit portion. The passivation film 31 is made of, for example, SiO 2₂, SiN, TEOS, Al₂O₃Etc. are made. The opening 33 is an opening having a size of about 70 μm, for example.
[0024]
  As shown in FIG. 5, grooves 34 are formed in the plurality of dicing streets 1 </ b> B of the upper substrate 1. That is, each semiconductor chip 30 is in a state of being separated by the groove 34 of each dicing street 1B. When the diameter of the via 50 shown in FIG. 8 described later is, for example, 30 μm, the width d of the dicing street shown in FIG. 5 is, for example, 150 μm.
  For example, when the groove 34 is formed in the dicing street 1B, the height of the groove 34 is 60 ± 5 μm if formed with a blade having a width of 150 μm. The bevel cut is also performed on a semiconductor chip that requires attention to contamination.
  As processing conditions of the groove 34, for example, the spindle rotation speed of the dicing blade was 30,000 rpm, and the feed rate was up to 5 mm / second.
[0025]
  Next, as shown in FIG. 6, an electrical insulating film 40 is formed on the upper substrate 1 and each semiconductor chip 30. The electrical insulating film 40 is formed, for example, by applying photosensitive polyimide by spin coating.
  When the thickness E of the electrical insulating film 40 after the planarization shown in FIG. 7 is, for example, 50 μm, the viscosity of the photosensitive polyimide is 60 posi. When the thickness E is 100 μm, the viscosity of the photosensitive polyimide is 100 posi. When the thickness E is 50 μm, the coating is performed at a rotation speed of 800 rpm / 30 s (seconds) +1100 rpm / 30 s, and the prebaking temperature is 90 ° C. and 240 s + 110 ° C. and 240 s. The curing temperature was 0.5 hour at 200 ° C. and 1 hour at 320 ° C.
  When the thickness E is 100 μm, coating is performed at a rotation speed of 800 rpm / 30 s + 1500 rpm / 30 s, and the pre-baking temperature is 90 ° C., 300 s + 110 ° C., and 300 s. The curing temperature was 200 ° C. for 0.5 hour + 320 ° C. for 1 hour.
  The electric insulating film 40 is an electric insulating resin film, and this material may be, for example, an epoxy type, a silicon type, or a polyolefin type. The electrical insulating film 40 may be formed by a film by vacuum lamination instead of varnish.
[0026]
  Next, the process proceeds to step ST1 shown in FIG.
  In FIG. 7, the surface of the electrical insulating film 40 is planarized. The flattening process of the electrical insulating film 40 is performed in order to prevent uneven exposure during the wiring pattern in the next process and to correctly perform fine wiring of about 10 μm. For this reason, the surface of the electrical insulating film 40 is subjected to a planarization process with a grinder to a surface roughness of about 1S. After the planarization surface 41 of the electrical insulating film 40 is formed, the surface is cleaned by desmear treatment with sulfuric acid / hydrogen peroxide.
[0027]
  Wiring part forming step ST2
  The wiring part forming step ST2 of FIG. 18 is shown in FIGS.
  First, FIG. 8 shows the formation of vias and electrode windows.openThe process is shown.
  In FIG. 8, electrode windows 45 and vias 50 are formed in the electrical insulating film 40. The electrode window 45 is formed at a position of the electrical insulating film 40 corresponding to the electrode pad 1 </ b> D and the opening 33 of each semiconductor chip 30.
  The via 50 is formed, for example, about 30 μm outside the semiconductor chip, and the via 50 is formed in the electrical insulating film 40 at the position of the groove 34 of the dicing street 1B. The diameter of the via 50 is, for example, 30 μm. The via 50 and the electrode window 45 are formed by patterning. When the electrical insulating film 40 is, for example, photosensitive polyimide, since it has a photosensitive group, a resist mask is not required for patterning. The via 50 extends from the surface of the electrical insulating film 40 to the inner bottom surface of the groove 34 and is formed perpendicular to the upper substrate 1.
[0028]
  Via 50 windowopenAnd electrode window 45 windowopenForming is performed with a g-line, i-line or broadband exposure through a mask, and a window with an alkali developer.openTo do. When photosensitive polyimide is used, descum is performed by plasma with CF4 or O2 to remove imide residues.
  The thickness of the electrical insulating film 40 in the vicinity of the electrode pad 1D of the semiconductor chip 30 is, for example, about 10 μm. The thickness of the electrical insulating film 40 near the via 50 is, for example, about 60 μm. Therefore, as an example, the exposure condition of 60 μm is 200 mJ / cm.²The exposure was performed with the above exposure time.
[0029]
  Next, referring to FIG. 9, when the formation of the via 50 and the electrode window 45 is completed as described above, a Cu wiring process is performed next. For the Cu wiring, NiCu or CrCu is sputtered to deposit the metal sputtered film 60 by 100 nm. The sputtered metal film 60 is also formed on the outer surface of the electrical insulating film 40, in the via 50, and in the electrode window 45.
  Moving to FIG. 10, when this sputtering is completed, a metal plating 61 which is Cu electrolytic plating is formed on the surface of the metal sputter film 60 and the surface of the electrode pad 1D with a thickness of about 5 μm, for example.
  11, the pattern of the via 50 and the electrode pad 1D is formed with a resist, and the metal plating 61 is etched with a nitric acid-based solution. As a result, a metal plating wiring patterning 63 which is a metal layer by UBM (Under Bump Metal) processing is formed using Cu of the metal plating 61 as a mask.
[0030]
  First singulation step ST3
  FIG.The firstThe single piece step ST3 is shown in FIGS.
  In FIG. 12, a metal post 70 and a buffer layer 71 are formed. The metal post 70 is electrically connected to the metal plating 61. A buffer layer 71 is formed around the metal post 70.
  Since the buffer layer 71 may be mounted with a glass epoxy substrate such as FR-4 on each semiconductor chip 30 in a later step, the thermal expansion between the glass epoxy substrate and each semiconductor chip 30 is performed. In order to avoid disconnection due to coefficient mismatch (mismatch), it is formed as a stress relaxation layer.
  The buffer layer 71 has, for example, an elastic modulus of about 2G, and the buffer layer 71 is formed by spin coating or transfer mold printing. The metal post 70 is a lead-out portion for the external electrode, and is made of, for example, Cu.
[0031]
  The metal sputtered film 60 and the metal plating 61 shown in FIGS. 9 and 10 are electric wiring portions formed in the via 50. Moreover, the metal plating 61 and the metal sputtered film 60 that are the electrical wiring portions of the electrode pad 1D and the via 50 are electrically connected by the metal plating 61 that is an electrical connection portion.
  As shown in FIGS. 8 to 12, the metal plating 61 as the electrical connection portion, the metal post 70 and the electrical insulating film 40 as the external electrode take-out portion shown in FIG. 12 are the first semiconductor wafer. The upper substrate 1 is formed on the first semiconductor wafer in a state before being divided into individual semiconductor chips 30.
  In this way, the electrical connection portion, the external electrode lead-out portion, and the electrical insulating film can be efficiently formed corresponding to each semiconductor chip 30.
[0032]
  Next, in FIG. 13, in the case of the vertical stacking process to be performed later, the thickness portion 1E of the upper substrate 1 shown in FIG. It is removed by back grinding. Such removal of the thickness portion 1E is performed, for example, about 50 μm and is performed up to the position of the inner bottom surface of the groove 34. Thereby, the thickness of each semiconductor chip 30 can be reduced.
[0033]
  Next, as shown in FIG. 14, the external electrodes 80 are formed and rearranged on the metal posts 70 that are the external electrode extraction portions. The external electrode 80 is, for example, a spherical bump, and the bump is formed of, for example, solder, Sn, Ag, Cu, or the like.
And each semiconductor chip 30 is individualized by the cut line 81 shown in FIG. 14, and thereby the semiconductor chips 30 can be formed separately as shown in FIG.
[0034]
  If the vertical and horizontal dicing streets 1B of the upper substrate 1 shown in FIG. 1 are at the same positions as the vertical and horizontal dicing streets 2B of the lower substrate 2 shown in FIG. 2, the upper substrate 1 shown in FIG. 1 and the lower substrate shown in FIG. 2 is bonded together.
  However, in other cases, for example, as shown in FIG. 14 and FIG. In this individualization, since the vias 50 and 50 are formed in the 50 μm portions on both sides within the dicing street width of 150 μm, the blade is cut by applying a 30 μm width blade to the 50 μm portion between the vias 50 and 50. I do. For example, a kerf of ± 10 μm does not affect the via.
[0035]
  Second fragmentation step ST4
  The second singulation step ST4 shown in FIG. 18 is shown in FIGS.
  In FIG. 16, a plurality of individual semiconductor chips 30 are mounted on the upper surface of the lower substrate 2. Lower substrate 2 electrodepadFor 2D, bumps 90 are formed from a conductive paste.
  The bumps 90 are electrically connected to the metal plating 61 which is an electric wiring portion of each semiconductor chip 30 by thermocompression bonding. When each semiconductor chip 30 is mounted on the upper surface of the corresponding lower substrate 2, the lower substrate 2 is cut so as to correspond to each semiconductor chip 30 along the cut line 96 corresponding to the dicing street of the lower substrate 2. Is done.
[0036]
  In this manner, the semiconductor device 10 constituted by the semiconductor chip 30 and the lower substrate portion (second semiconductor wafer portion) 97 as shown in FIG. 17 is completed.
  The lower substrate portion 97 is a portion obtained by cutting the lower substrate 2 along the cut line 96, and the active device 100 and the passive device 101 are mounted on the lower substrate 97.
  The active element 100 and the passive element 101 are electrically insulated from the semiconductor chip 30 by an electrical insulating material 103. In this way, the semiconductor chip 30 is embedded with the electric insulating film 40, and the semiconductor chip 30 on the upper substrate 1 side and the lower substrate portion 97 are electrically connected by the metal plating 61 that is the electric wiring portion in the via 50. Can be reliably connected.
[0037]
  As described above, the formation of the electrical insulating film 40 as shown in FIGS. 6 and 7, the electrical connection portion of the metal plating 61 which is the electrical wiring portion of the electrode pad 1D and the via 50, and the external electrode to the electrode pad 1D The metal post 70 shown in FIG. 12 as the take-out portion can be formed when the upper substrate 1 is a semiconductor wafer. Thus, the number of processes can be reduced, and the semiconductor device 10 which is a stacked module with high positional accuracy can be formed as shown in FIG. The electrical connection portion between the electrode pad and the electrical wiring portion of the via, the lead-out portion of the external electrode, and the electrical insulating film can be efficiently formed on the first semiconductor wafer.
  Conventionally, in a so-called rewiring type WLCSP (wafer level chip size package) or the like, stacking with a thickness of about 50 μm was impossible due to the problem of warpage. A portion 97 of the substrate can be stacked.
[0038]
  The semiconductor chip of the first semiconductor wafer can be stacked on the portion of the second semiconductor wafer and can be electrically connected through the electric wiring portion by effectively using the portion of the dicing street. For this reason, it is not necessary to ensure a large surface area of the semiconductor device as in the prior art, and the semiconductor device can be downsized.
  The semiconductor chip can easily form a peripheral circuit on the opposite side of the active circuit of the semiconductor chip with respect to the portion of the second semiconductor wafer. For example, the semiconductor chip includes a semiconductor chip having an active circuit and circuits of active elements and passive elements. The problem of mutual interference with the second semiconductor wafer portion can be prevented.
[0039]
  In the embodiment of the present invention, the semiconductor chip 30 is arranged on the upper side of the semiconductor device 10, and the lower substrate portion 97 is laminated on the lower side of the semiconductor chip 30. The semiconductor chip 30 and the lower substrate portion 97 can be electrically connected by using a metal plating 61 (electric wiring portion) disposed at the position of the dicing street. The semiconductor chip is embedded with an electrical insulating film.
  The semiconductor chip 30 stacked on the lower substrate portion 97 is mounted on the lower substrate portion 97 in a so-called face-up state. Since the semiconductor chip 30 is mounted face up in this way, the electrode pad 1D of the semiconductor chip 30 does not directly face the active element 100 and the passive element 101 of the lower substrate portion 97. Therefore, even when the semiconductor chip 30 as an analog chip and the lower substrate portion 97 as a digital chip are stacked, it is possible to prevent the semiconductor chip 30 and the lower substrate portion 97 from interfering with each other. Since the active element 100 and the passive element 101 of the lower substrate portion 97 can be formed on the opposite side of the active circuit of the semiconductor chip 30, mutual interference can be prevented.
[0040]
  In the embodiment of the present invention, after the semiconductor chips 30 are individualized, each semiconductor chip 30 is arranged on a wafer-like lower substrate. Then, the lower substrate 2 is cut along the cut lines 96 corresponding to the dicing streets of the lower substrate 2 so as to correspond to the respective semiconductor chips 30, whereby the semiconductor device 10 as shown in FIG. 17 can be obtained. Therefore, both the upper substrate and the lower substrate can be separated into individual semiconductor devices using the dicing street portion, and the productivity of the semiconductor device can be improved. Further, the semiconductor chip 30 and the lower substrate portion 97 can be reliably aligned. The manufacturing efficiency of the semiconductor device 10 can be increased as compared with the case where the semiconductor chip 30 and the lower substrate portion 97 are individually separated and pasted.
[0041]
  As shown in FIG. 17, the metal plating 61 in the dicing street portion is completely covered with the electrical insulating film 40, so that any part of the semiconductor chip 30 including the metal plating 61 is completely outside from the electrical insulating film 40. Not exposed. Thus, electrical insulation can be reliably achieved.
[0042]
【The invention's effect】
  As described above, according to the present invention, one semiconductor wafer can be effectively used by using dicing street.More individualizedSemiconductor chips can be stacked and electrically connected to the other wafer portion, and the semiconductor device can be miniaturized.
[Brief description of the drawings]
FIG. 1 is a plan view showing a first semiconductor wafer (upper substrate) of the present invention.
FIG. 2 is a view showing a second semiconductor wafer (lower substrate) of the present invention.
FIG. 3 is an enlarged view showing a portion A of the upper substrate.
FIG. 4 is a cross-sectional view of an upper substrate including a plurality of semiconductor chips.
FIG. 5 is a view showing a state in which grooves are formed on a dicing street of an upper substrate.
FIG. 6 is a cross-sectional view showing a state where an electrical insulating film is formed on the surface side of the upper substrate.
FIG. 7 is a diagram in which a planarized surface is formed on an electrical insulating film.
FIG. 8 is a diagram in which via windows and electrode windows are formed in an electrical insulating film.
FIG. 9 is a diagram in which a metal sputtered film 60 is formed in a window of a via and an electrode.
FIG. 10 is a diagram in which metal plating is formed on a metal sputtered film.
FIG. 11 is a diagram in which wiring patterning is performed on metal plating.
FIG. 12 is a diagram in which a buffer layer and a metal post are formed.
FIG. 13 is a diagram in which the upper substrate is thinned.
FIG. 14 is a diagram in which an external electrode is attached to a metal post.
FIG. 15 shows a semiconductor chip separated into pieces.
FIG. 16 is a diagram in which individual semiconductor chips are stacked on a lower substrate.
FIG. 17 shows a semiconductor device including a semiconductor chip and a lower substrate.
18 is a view showing a method for manufacturing a semiconductor device of the present invention. FIG.
[Explanation of symbols]
  DESCRIPTION OF SYMBOLS 1 ... Upper substrate (1st semiconductor wafer), 2 ... Lower substrate (2nd semiconductor wafer), 1B, 2B ... Dicing street, 1D ... Electrode pad, 30 ... Semiconductor chip, 33 ... Opening, 34 ... Dicing street groove, 40 ... Electric insulating film, 50 ... Via, 45 ... Electrode window, 60 ... Metal sputtered film Part), 61 ... metal plating (part of the electrical wiring part), 63 ... wiring patterning of the metal plating, 70 ... metal post (external electrode extraction part), 71 ... buffer layer, 80 ... External electrode, 97 ... Lower substrate part, 100 ... Active element, 101 ... Passive element

Claims (6)

A semiconductor device comprising a semiconductor chip separated from a first semiconductor wafer and a lower substrate portion separated from a second semiconductor wafer,
The separated semiconductor chip is:
A plurality of electrode pads and circuit portions disposed on the upper substrate; and an electrical insulating film formed on the upper substrate, on the electrode pads, on the circuit portion, and on the outer periphery of the upper substrate;
Vias formed in the electrical insulating film on the electrode pads and on the outer periphery of the upper substrate;
An electrical wiring portion for electrically connecting the electrode pad and the upper substrate outer periphery via;
A metal post connected to the electrical wiring section;
A buffer layer formed around the metal post;
An external electrode formed with respect to the metal post,
The part of the lower substrate separated into pieces is as follows:
A passive element and an active element provided on the lower substrate;
An electrode pad disposed on the lower substrate on the periphery, and a bump formed of a conductive paste on the electrode pad;
The electrical wiring portion provided in the upper substrate outer peripheral portion via and the electrode pad disposed in the peripheral on the lower substrate are electrically connected by the thermocompression bonding of the bump ,
A semiconductor device, wherein the separated semiconductor chip is stacked on the separated lower substrate portion.   The semiconductor device according to claim 1, wherein the semiconductor chip is mounted face-up on a portion of the second semiconductor wafer. A method of manufacturing a semiconductor device electrically connected by stacking a semiconductor chip separated from a first semiconductor wafer and a portion of a lower substrate separated from a second semiconductor wafer,
Forming a groove in a dicing street around a wiring pattern of each of the semiconductor chips of the first semiconductor wafer, and forming a groove and an insulating film to cover the wiring pattern with an electric insulating film;
An electrode window is opened in a portion of the electrical insulating film corresponding to the electrode pad of the wiring pattern, and a via is formed in the portion of the electrical insulating film corresponding to the dicing street, and an electrical connection portion is connected to the electrode window and the via. Forming an electrical connection part forming step;
A first singulation step of forming an external electrode for the electrical connection portion and cutting the semiconductor chip by cutting at the dicing street of the first semiconductor wafer;
The separated semiconductor chip is mounted on the second semiconductor wafer, the wiring portion of the semiconductor chip is electrically connected to the electrode of the second semiconductor wafer, and the second semiconductor wafer is connected to the semiconductor A semiconductor device comprising: a second singulation step for separating a portion of the second semiconductor wafer and a stacked body of the semiconductor chips by cutting at a dicing street according to a chip. Production method.   4. The method of manufacturing a semiconductor device according to claim 3, wherein, in the second singulation step, each of the semiconductor chips is mounted face-up on a portion of the second semiconductor wafer.   The electrical connection between the electrode pad of the semiconductor chip and the electrical wiring portion of the via, the lead-out portion of the external electrode with respect to the electrode pad, and the electrical insulating film are in the state of the first semiconductor wafer. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is formed on the first semiconductor wafer before being divided into individual semiconductor chips.   The method of manufacturing a semiconductor device according to claim 5, wherein the electrical insulation film is an electrical insulation resin, and the electrical insulation film covers the semiconductor chip.

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