JP4044306B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using different gate materials for an n-type MIS transistor and a p-type MIS transistor and a manufacturing method thereof.
[0002]
[Prior art]
With the miniaturization of MOSFETs, the gate oxide film is becoming thinner, and an extremely thin gate oxide film thickness of about 1 nm is required for a gate length of 50 nm or less. One of the factors is depletion of polysilicon used for the gate electrode. When the polysilicon is not depleted, the gate oxide film can be thickened by about 0.5 nm. Accordingly, a so-called metal gate electrode MOSFET (MISFET) using a metal without gate depletion as a gate electrode has attracted attention.
[0003]
However, when one kind of metal is used as the gate electrode, there are the following problems. Since the work function of the gate electrode is the same for the n-type and p-type MISFET, gate electrodes having different work functions such as a polysilicon gate cannot be formed separately for the n-type MISFET and the p-type MISFET, and the threshold value It becomes very difficult to optimize the voltage. In particular, in order to realize a low threshold value of 0.5 V or less, a material having a work function of 4.6 eV or less, preferably 4.3 eV or less is used for the gate electrode of the n-type MISFET, and a work function is used for the gate electrode of the p-type MISFET. Is required to be 4.6 eV or more, preferably 4.9 eV or more. Therefore, a so-called dual metal gate process using different metal materials for the n-type MISFET and the p-type MISFET as the gate electrode is required.
[0004]
In the dual metal gate process, the gate electrode material for one MISFET (for example, n-type) is formed on the entire surface including the formation region of the n-type and p-type MISFET because it is necessary to create a gate electrode separately for the n-type and p-type MISFET. After that, only the gate electrode material formed in the formation region of the other MISFET (for example, p-type) is removed, and then the gate electrode material for the other MISFET (for example, p-type) is formed.
[0005]
For example, when hafnium nitride is used as the gate electrode material of the n-type MISFET and tungsten is used as the gate electrode material of the p-type MISFET, the hafnium nitride in the p-type MISFET formation region is made of, for example, hydrogen peroxide using a resist as a mask. And removed by wet etching.
[0006]
However, when the gate electrode material such as hafnium nitride is removed by wet etching, the gate insulating film in the p-type MISFET formation region is exposed to the etching solution. Further, when the resist used as the mask is peeled off, the gate insulating film in the p-type MISFET formation region is also exposed to an organic solvent used as a peeling solution. Therefore, the dual metal gate process described above has a problem that the reliability of the gate insulating film of the p-type MISFET is significantly lowered.
[0007]
[Problems to be solved by the invention]
As described above, a dual metal gate process using gate electrode materials having different work functions or the like has been proposed for n-type MISFETs and p-type MISFETs, but the etching solution and resist for removing the gate electrode materials are removed. Since the gate insulating film is exposed to the stripping solution, there is a problem that the reliability of the gate insulating film is significantly lowered.
[0008]
The present invention has been made to solve the above-described conventional problems, and provides a semiconductor device capable of improving the above-described problems of the dual metal gate process and improving element characteristics and reliability, and a method of manufacturing the same. The purpose is to do.
[0009]
[Means for Solving the Problems]
The present invention is a semiconductor device having an n-type MIS transistor and a p-type MIS transistor, wherein a gate electrode of one of the n-type and p-type MIS transistors is a first gate material formed on a gate insulating film. A second gate material film formed on the first gate material film and a third gate material film formed on the second gate material film, and the other of the n-type and p-type MIS transistors. The gate electrode of the transistor includes a third gate material film formed on the gate insulating film, and the first gate material film is a metal film made of antimony, bismuth, indium, lead, tin, or tellurium, or these A metal compound film containing any of the above metal elements.
[0010]
The present invention also relates to a method of manufacturing a semiconductor device having an n-type MIS transistor and a p-type MIS transistor, the step of forming a gate insulating film on a semiconductor substrate, and a first gate material on the gate insulating film. A step of forming a film, a step of forming a second gate material film on the first gate material film, and a second region of the first region where one of the n-type and p-type MIS transistors is formed. A step of selectively removing the gate material film to expose the first gate material film in the first region, and a step of selectively sublimating the exposed first gate material film in the first region by heat treatment. The step of exposing the gate insulating film in the first region, the second region in the second region where the other transistor of the n-type and p-type MIS transistors is formed on the exposed gate insulating film in the first region. Gate material In the upper, characterized by comprising a step of forming a third gate material film.
[0011]
[Action]
According to the present invention, since the gate insulating film is exposed by selectively sublimating the first gate material film with respect to the second gate material film by heat treatment, the gate material film is removed as in the prior art. The gate insulating film is not exposed to the etching solution or the stripping solution used to strip the resist. Therefore, it is possible to prevent the reliability of the gate insulating film from being lowered. In particular, when antimony, bismuth, indium, lead, tin, or tellurium, or a compound thereof is used as the first gate material film, these materials generally sublime at a relatively low temperature. A semiconductor device using a gate material different from that of the type MIS transistor can be easily obtained, and a semiconductor device having excellent element characteristics and reliability can be obtained.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0013]
(Embodiment 1)
FIG. 1A to FIG. 6L are cross-sectional views showing manufacturing steps of a MISFET (MIS transistor) according to the first embodiment of the present invention. This embodiment is an example in which a MISFET is manufactured using a so-called damascene gate technique.
[0014]
First, as shown in FIG. 1A, an element isolation region 11 is formed in the surface region of the silicon substrate 10 using an STI technique or the like. Subsequently, as a dummy gate structure to be removed in the future, for example, a laminated structure of a gate oxide film 12 having a thickness of about 6 nm, a polysilicon film 13 having a thickness of about 150 nm, and a silicon nitride film 14 having a thickness of about 50 nm is formed by an oxidation technique. It is formed using a CVD technique, a lithography technique, and an RIE technique. Subsequently, the extension diffusion layer region 15 is formed using an ion implantation technique. Further, a gate sidewall 16 made of a silicon nitride film and having a width of about 40 nm is formed using the CVD technique and the RIE technique.
[0015]
Next, as shown in FIG. 1B, a source / drain diffusion layer 17 is formed by an ion implantation technique. Thereafter, using a salicide process technique, a silicide film (for example, cobalt silicide film) 18 having a thickness of about 40 nm is formed only in the source / drain regions using the dummy gate structure and the gate sidewall 16 as a mask. At this time, as the dopant of the source / drain regions, arsenic is used for the n-type region and gallium is used for the p-type region. ¹⁵ / Cm ² Ions are implanted with the above dose. These dopants can suppress the aggregation of silicide and greatly improve the heat resistance.
[0016]
Next, as shown in FIG. 2C, a silicon oxide film, for example, is deposited as the interlayer film 19 by the CVD method. Further, the silicon oxide film is planarized by CMP technique to expose the upper surfaces of the silicon nitride film 14 and the silicon nitride film 16.
[0017]
Next, as shown in FIG. 2D, the silicon nitride film 14 is selectively removed from the interlayer film 19 using phosphoric acid, for example. At this time, the silicon nitride film 16 on the gate sidewall is also etched to the height of the polysilicon film 13. Subsequently, the polysilicon film 13 that is a dummy gate is selectively removed from the interlayer film 19 and the gate sidewall 16 by using, for example, radical atom etching technology.
[0018]
Next, as shown in FIG. 3E, the surface of the silicon substrate 10 is exposed by removing the dummy gate oxide film 12 by wet processing such as hydrofluoric acid. Subsequently, the gate insulating film 20 is formed on at least the bottom of the gate trench thus obtained. As the gate insulating film 20, for example, a silicon oxide film obtained by thermally oxidizing the silicon substrate 10 can be used. Further, a silicon oxide film whose surface is further nitrided with nitrogen plasma may be used. Further, as described below, a high dielectric film may be used for the gate insulating film 20.
[0019]
An example of the high dielectric film used for the gate insulating film 20 is a hafnium oxide film. This hafnium oxide film is, for example, HfCl. _Four And NH _Three After the hafnium nitride film is formed by using a CVD method using a CVD method, a CVD method using an organic Hf gas, or a sputtering method using a hafnium nitride target or a hafnium target, the hafnium nitride film is oxidized. Can be formed. The thickness of the hafnium nitride film to be oxidized is preferably as thin as several nm. This is because crystallization is likely to occur as the thickness of the hafnium nitride film increases. When hafnium nitride is formed by sputtering, the energy of the sputtered hafnium or hafnium nitride particles is preferably 100 eV or less, more preferably 50 eV or less. This is because, as the energy of the sputtered particles increases, the sputtered particles bite into the silicon substrate and the morphology of the channel surface deteriorates.
[0020]
Next, as shown in FIG. 3F, as an electrode material having a work function of 4.6 eV or less, an antimony film (first gate material film) 21 is formed to a thickness of about 10 nm, preferably less than that, A film is formed on the bottom of the gate groove. For film formation, a sputtering method, a CVD method, or an evaporation method may be used. Since antimony has a low melting point of 630 ° C., it can be easily formed by thermal evaporation.
[0021]
When the sputtering method is used, it is desirable to control the energy of the sputtered antimony particles to 100 eV or less, preferably 50 eV or less. By setting the energy of the antimony particles to such a low energy, the antimony particles do not bite into the underlying gate insulating film 20 and the reliability of the gate insulating film is remarkably improved.
[0022]
As shown in FIG. 4G, a coating solution in which antimony is dissolved is applied to the entire surface of the wafer, and after baking, antimony is etched back by a dry etching technique, and an antimony film is formed only on the bottom of the gate groove. 21 may be left. Also in this case, it is desirable that the film thickness of the antimony film 21 be 10 nm or less.
[0023]
Next, as shown in FIG. 4H, a tungsten film (second gate material film) 22 is formed on the entire surface. As the film formation method, a sputtering method, a CVD method, a coating method, or the like may be used. The film thickness of tungsten 22 is not particularly limited, but is desirably about 20 nm or less, and the reason will be described later.
[0024]
Next, the process proceeds to the process of FIG. From FIG. 5 (i), the left side is the n-type MISFET formation region and the right side is the p-type MISFET formation region (the same applies to the subsequent drawings). In this step, a pattern of the resist 23 having an opening only in the p-type MISFET region is formed by using a lithography technique.
[0025]
Next, as shown in FIG. 5J, the tungsten film 22 is selectively removed only in the p-type MISFET region by performing wet etching with hydrogen peroxide using the resist 23 as a mask. Since the antimony film 21 is insoluble in hydrogen peroxide, only the tungsten film 22 can be selectively removed. Further, since the gate insulating film 20 is covered with the antimony film 21, it is not necessary to be exposed to the hydrogen peroxide solution. Further, by reducing the thickness of the tungsten film 22 to about 20 nm or less, the etching amount can be reduced.
[0026]
Next, as shown in FIG. 6 (k), the resist 23 is removed with an organic solvent or the like, but at this time, the gate insulating film 20 is covered with the antimony film 21, so that it is not exposed to the organic solvent or the like. . Thereafter, heat treatment is performed at a temperature of about 500 ° C. in a nitrogen atmosphere, for example. By this heat treatment, the antimony film 21 exposed on the surface of the p-type MISFET region is not sublimated, and the gate insulating film 20 in the p-type MISFET region is exposed. On the other hand, since the antimony film 21 in the n-type MISFET region is covered with the tungsten film 22, it does not sublime. The pressure of the atmosphere during the heat treatment is about atmospheric pressure (1 × 10 ^Five However, when it is desired to sublimate antimony more efficiently, heat treatment is performed at a pressure equal to or lower than atmospheric pressure.
[0027]
Next, as shown in FIG. 6L, a tungsten film (third gate material film) 24 is deposited on the entire surface by sputtering or CVD. Subsequently, by performing CMP of the antimony film 21, the tungsten film 22, and the tungsten film 24, the antimony film 21, the tungsten film 22, and the tungsten film 24 are formed in the p-type MISFET region in the gate groove of the n-type MISFET region. The gate electrode structure in which the tungsten film 24 is buried is obtained.
[0028]
When a sputtering method is used for forming the tungsten film 24, it is desirable to control the energy of the sputtered tungsten particles to 100 eV or less, preferably 50 eV or less. By setting the energy of the tungsten particles to such low energy, the tungsten particles do not bite into the underlying gate insulating film 20, and the reliability of the gate insulating film is remarkably improved.
[0029]
As described above, the n-type MISFET has a gate electrode structure formed of a laminated film of the antimony film 21, the tungsten film 22, and the tungsten film 24, and the p-type MISFET has a gate electrode structure CMISFET formed of a single layer film of the tungsten film 24. The
[0030]
As described above, in this embodiment, an antimony film (work function of about 4.2 eV) is used as the lowermost layer of the gate electrode of the n-type MISFET, and a tungsten film (work function of about 4.9 eV) is used as the gate electrode of the p-type MISFET. Both the n-type MISFET and the p-type MISFET can optimize the work function of the gate electrode. Therefore, the threshold voltages of the n-type MISFET and the p-type MISFET can be optimized.
[0031]
Further, when the gate insulating film of the p-type MISFET is exposed, the antimony film is selectively sublimated by heat treatment, so that the surface of the gate insulating film may be exposed to a wet etching solution, an organic solvent, or the like as in the prior art. Absent. Therefore, it is possible to manufacture a MISFET with excellent gate insulating film reliability.
[0032]
In order to increase the reliability of the gate insulating film, it is desirable to apply the following method.
[0033]
First, it is desirable to perform from the step of forming the gate insulating film 20 to the step of forming the antimony film 21 without being exposed to the atmosphere. In other words, it is desirable that the wafer transfer between the film formation apparatus for the gate insulating film 20 and the film formation apparatus for the antimony film 21 be performed in a space filled with nitrogen to expel the atmosphere or in a vacuum space. Further, it is desirable to carry out the wafer transfer between the heat treatment apparatus for sublimating the antimony film 21 and the film formation apparatus for the tungsten film 24 in the same manner.
[0034]
The heat treatment apparatus for sublimating the antimony film 21 and the film formation apparatus for the tungsten film 24 may be the same apparatus. Specifically, a so-called single-wafer type film forming apparatus for forming a film for each wafer may be used. In this case, first, before forming the tungsten film 24 in the chamber in which the tungsten film 24 is formed, the silicon wafer is heated to, for example, about 500 ° C. to sublimate the antimony film 21 in the p-type MISFET region. The silicon wafer may be heated, for example, by irradiating light or by heating a wafer chuck that is a mounting table for the silicon wafer. Thereafter, the tungsten film 24 is formed without exposing the wafer to the atmosphere in the same chamber.
[0035]
By applying the above method, the tungsten film 24 can be formed without exposing the gate insulating film 20 in the p-type MISFET region to the atmosphere.
[0036]
(Embodiment 2)
FIG. 7A to FIG. 10H are cross-sectional views showing manufacturing steps of a MISFET (MIS transistor) according to the second embodiment of the present invention.
[0037]
First, as shown in FIG. 7A, the element isolation region 31 is formed in the surface region of the silicon substrate 30, and then the gate insulating film 32 is formed. The method for forming the gate insulating film 32 is the same as that in the first embodiment. For example, the gate insulating film 32 made of a hafnium oxide film is formed on the entire surface. Further, as in the first embodiment, an antimony film (first gate material film) 33 is formed on the entire surface of the gate insulating film 32 with a thickness of about 10 nm, preferably less than that, and subsequently the thickness. A tungsten film (second gate material film) 34 of about 20 nm is formed on the entire surface.
[0038]
Next, the process proceeds to the process of FIG. From FIG. 7B, the left side of the figure is an n-type MISFET formation region, and the right side is a p-type MISFET formation region (the same applies to the subsequent drawings). In this step, a pattern of the resist 35 having an opening only in the p-type MISFET region is formed using a lithography technique.
[0039]
Next, as shown in FIG. 8C, only tungsten film 34 formed in the p-type MISFET region is selectively removed by performing wet etching with hydrogen peroxide solution. Since the gate insulating film 32 is covered with the antimony film 33, it is not necessary to be exposed to the hydrogen peroxide solution.
[0040]
Next, as shown in FIG. 8 (d), the resist 35 is removed with an organic solvent or the like. At this time, the gate insulating film 32 is covered with the antimony film 33, so that it is not exposed to the organic solvent or the like. . Thereafter, as in the first embodiment, for example, heat treatment is performed at a temperature of about 500 ° C. in a nitrogen atmosphere. By this heat treatment, the antimony film 33 exposed on the surface of the p-type MISFET region is not sublimated, and the gate insulating film 32 in the p-type MISFET region is exposed. On the other hand, the antimony film 33 in the n-type MISFET region is not sublimated because it is covered with the tungsten film 34.
[0041]
Next, as shown in FIG. 9E, a tungsten film (third gate material film) 36 is deposited to a thickness of about 50 nm on the entire surface by sputtering or CVD. Further, a silicon nitride film 37 is deposited to a thickness of about 50 nm on the entire surface by using a CVD technique or the like.
[0042]
Next, as shown in FIG. 9F, the silicon nitride film 37, the tungsten film 36, the tungsten film 34, and the antimony film 33 are etched using the lithography technique and the RIE technique, so that the n-type and p-type MISFET regions are formed. A gate electrode is formed. The gate insulating film 32 in the region where the source / drain is formed may also be removed using the RIE technique. Here, the case of removal is illustrated.
[0043]
Next, as shown in FIG. 10G, the extension diffusion layer region 38 is formed by an ion implantation technique using the gate electrode formed as described above as a mask. Thereafter, a gate sidewall 39 having a width of about 40 nm made of a silicon nitride film is formed. Further, after the source / drain diffusion layer 40 is formed by the ion implantation technique, a heat treatment for impurity activation is performed. If the gate insulating film 32 in the source / drain region is not removed in the step of FIG. 9F, the source / drain region in the etch-back process using the RIE technique for forming the gate sidewall 39 is formed. The gate insulating film 32 is also etched.
[0044]
Next, as shown in FIG. 10H, a silicide film (for example, cobalt silicide film) 41 having a thickness of about 40 nm is formed only in the source / drain regions by using a salicide process technique.
[0045]
As described above, the n-type MISFET has a gate electrode structure formed of a laminated film of an antimony film 33, a tungsten film 34, and a tungsten film 36, and the p-type MISFET has a gate electrode structure CMISFET formed of a single layer film of the tungsten film 36. The
[0046]
Also in the present embodiment, as in the first embodiment, the MISFET has excellent device characteristics and excellent reliability, such as optimization of the work function of the gate electrode of the n-type and p-type MISFET and improvement of the reliability of the gate insulating film. Can be obtained.
[0047]
In the first and second embodiments described above, antimony (Sb) is used as the first gate material film and tungsten (W) is used as the second and third gate material films. It is also possible to use materials having conductivity other than these materials.
[0048]
In the first and second embodiments, the gate electrode of the n-type MISFET is composed of the first, second and third gate material films, and the gate electrode of the p-type MISFET is composed of the third gate material film. By appropriately selecting a combination of the first, second and third gate material films, the gate electrode of the p-type MISFET is the first, second and third gate material films, and the gate electrode of the n-type MISFET. Can be formed of a third gate material film.
[0049]
As a first gate material film, when applied to a gate electrode of an n-type MISFET, a material having a work function of 4.6 eV or less, preferably 4.3 eV or less, and when applied to a gate electrode of a p-type MISFET, It is desirable to use a material having a work function of 4.6 eV or higher, preferably 4.9 eV or higher. Further, it is desirable that the material can be sublimated at a temperature that does not damage the gate insulating film, for example, a temperature of about 800 ° C. or less.
[0050]
Specifically, in addition to the above-described antimony, metals such as bismuth (Bi), indium (In), lead (Pb), tin (Sn), and tellurium (Te) can be used. Antimony, bismuth, indium, lead and tin can be used mainly for the gate electrode of the n-type MISFET, and tellurium can be used mainly for the gate electrode of the p-type MISFET.
[0051]
Bismuth, indium, lead, tin, and tellurium are less likely to sublime than antimony, but sublimate if the atmospheric pressure during heat treatment is reduced to an appropriate value in consideration of the vapor pressure. For example, in bismuth, the vacuum level is 1 × 10 ^-1 Sublimation can be achieved by heat treatment at about 500 ° C. at about Pa or less. 1 × 10 for indium ^-Four About 600 ℃ at Pa or less, 1 × 10 for lead ^-2 Sublimation can be achieved by heat treatment at about 600 ° C. under Pa.
[0052]
Alternatively, a metal compound containing one or more metal elements selected from antimony, bismuth, indium, lead, tin, and tellurium can be used as the first gate material film. The compound of these two or more metal elements may be sufficient, and the compound of these one or more metal elements and another metal element may be sufficient.
[0053]
Specifically, indium tin oxide is mainly used as a compound suitable for the gate electrode of n-type MISFET. Also, as compounds suitable for the gate electrode of p-type MISFET, indium arsenide, indium antimonide, bismuth telluride, indium arsenide and indium antimonide compounds, lead telluride, tin telluride, lead telluride and tellurium And tin selenide compounds, lead selenide and tin selenide compounds.
[0054]
Among the metal compounds described above, indium antimonide and indium arsenide are semiconductors, but have band gaps of about 0.17 eV and 0.35 eV, which are much smaller than the band gap of silicon (1.1 eV). Such a material having a small band gap exhibits electrical conductivity close to that of a metal because a large number of electrons and holes are generated at room temperature. Therefore, such a compound can be used as the first gate material.
[0055]
It is also possible to reduce the band gap. For example, the band gaps of lead telluride and tin telluride are 0.22 eV and 0.25 eV, respectively. By mixing lead telluride and tin telluride in a molar ratio of about 3: 2, the band gap is reduced to zero. It is also possible to do. The same applies to the other semiconductors described above.
[0056]
As the second gate material film, a material having a sublimation temperature higher than that of the first gate material film is used under a predetermined temperature and pressure. Specifically, it is desirable to use a material that does not sublime at the temperature and pressure of the step of sublimating the first gate material and has a sufficiently high melting point than the temperature of the step. For example, when antimony is used as the first gate material film, the heat treatment temperature in the process of sublimating antimony is about 800 ° C. or lower, so the melting point is preferably about 1000 ° C. or higher. Specifically, a metal such as tungsten (W) or molybdenum (Mo) or a metal nitride such as tungsten nitride, molybdenum nitride, or titanium nitride (TiN) is used as the second gate material film. desirable. These are desirable materials because they do not easily react with antimony.
[0057]
As the third gate material film, when applied to an n-type MISFET (when applied to a gate material film in contact with the gate insulating film of the n-type MISFET), the work function is 4.6 eV or less, preferably 4.3 eV or less. When applying to the gate electrode of the material, p-type MISFET (when applying to the gate material film in contact with the gate insulating film of the p-type MISFET), use a material having a work function of 4.6 eV or higher, preferably 4.9 eV or higher. Is desirable.
[0058]
Specifically, as the third gate material film, a metal such as tungsten (W), molybdenum (Mo), platinum (Pt), iridium (Ir), or ruthenium (Ru), iridium oxide, ruthenium oxide, or the like. It is desirable to use the conductive metal oxide. Tungsten, molybdenum, and platinum are difficult materials to diffuse into the silicon oxide film, and thus can be said to be particularly desirable materials when a silicon oxide film is used as the gate insulating film.
[0059]
Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if several constituent requirements are deleted from the disclosed constituent requirements, the invention can be extracted as an invention as long as a predetermined effect can be obtained.
[0060]
【The invention's effect】
According to the present invention, problems of a semiconductor device using a conventional dual metal gate process are improved, and a semiconductor device having excellent element characteristics and reliability can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a part of a manufacturing process of a MIS transistor according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a part of the manufacturing process of the MIS transistor according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a part of the manufacturing process of the MIS transistor according to the first embodiment of the invention.
FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the MIS transistor according to the first embodiment of the invention.
FIG. 5 is a cross-sectional view showing a part of the manufacturing process of the MIS transistor according to the first embodiment of the invention.
FIG. 6 is a cross-sectional view showing a part of the manufacturing process of the MIS transistor according to the first embodiment of the invention.
FIG. 7 is a cross-sectional view showing a part of a manufacturing process of a MIS transistor according to a second embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a part of a manufacturing process of a MIS transistor according to a second embodiment of the present invention.
FIG. 9 is a sectional view showing a part of a manufacturing process of a MIS transistor according to a second embodiment of the invention.
FIG. 10 is a cross-sectional view showing a part of a manufacturing process of a MIS transistor according to a second embodiment of the invention.
[Explanation of symbols]
10, 30 ... silicon substrate
11, 31 ... element isolation region
12 ... Gate oxide film
13 ... Polysilicon film
14 ... Silicon nitride film
15, 38 ... Extension diffusion layer region
16, 39 ... Gate side wall
17, 40 ... Source / drain diffusion layers
18, 41 ... Silicide film
19 ... Interlayer film
20, 32 ... Gate insulating film
21, 33 ... antimony film (first gate material film)
22, 34 ... Tungsten film (second gate material film)
23, 35 ... resist
24, 36 ... Tungsten film (third gate material film)
37 ... Silicon nitride film

Claims (11)

A semiconductor device having an n-type MIS transistor and a p-type MIS transistor,
The gate electrode of one of the n-type and p-type MIS transistors includes a first gate material film formed on the gate insulating film, a second gate material film formed on the first gate material film, and a second gate material film. and a third gate material film formed on the second gate material layer,
The gate electrode of the other transistor of the n-type and p-type MIS transistor, and a third gate material film formed on the gate insulating film,
The first gate material film, antimony, bismuth, indium, lead, a metal film made of tin or tellurium, or a metal compound film der containing these metal elements is,
The second gate material film is made of a material that does not sublime under the condition that the first gate material film is sublimated,
The semiconductor device, wherein the third gate material film is made of a material having a work function different from that of the first gate material film . The semiconductor device according to claim 1, wherein the second gate material film is a tungsten film, a molybdenum film, a tungsten nitride film, a molybdenum nitride film, or a titanium nitride film. The semiconductor device according to claim 1, wherein the third gate material film is a tungsten film, a molybdenum film, a platinum film, an iridium film, a ruthenium film, an iridium oxide film, or a ruthenium oxide film. 4. The semiconductor device according to claim 1, wherein constituent materials of the second gate material film and the third gate material film are the same. 5. A method of manufacturing a semiconductor device having an n-type MIS transistor and a p-type MIS transistor,
Forming a gate insulating film on the semiconductor substrate;
Forming a first gate material film on the gate insulating film;
Forming a second gate material film on the first gate material film;
selectively removing the second gate material film in the first region where one of the n-type and p-type MIS transistors is formed, and exposing the first gate material film in the first region; ,
A step of selectively sublimating the exposed first gate material film in the first region by heat treatment to expose the gate insulating film in the first region;
A third gate material film is formed on the exposed gate insulating film in the first region and on the second gate material film in the second region where the other of the n-type and p-type MIS transistors is formed. Forming, and
Equipped with a,
The first gate material film is a metal film made of antimony, bismuth, indium, lead, tin or tellurium, or a metal compound film containing those metal elements,
The second gate material film is made of a material that does not sublime under the condition that the first gate material film is sublimated,
The method of manufacturing a semiconductor device, wherein the third gate material film is made of a material having a work function different from that of the first gate material film . The method of manufacturing a semiconductor device according to claim 5 , wherein the second gate material film is a tungsten film, a molybdenum film, a tungsten nitride film, a molybdenum nitride film, or a titanium nitride film. The semiconductor device according to claim 5 or 6 , wherein the third gate material film is a tungsten film, a molybdenum film, a platinum film, an iridium film, a ruthenium film, an iridium oxide film, or a ruthenium oxide film. Method. The method for manufacturing a semiconductor device according to claim 5, wherein the second gate material film and the third gate material film are made of the same material. 9. The method according to claim 5 , further comprising processing the first, second, and third gate material films to form gate electrodes of n-type and p-type MIS transistors. The manufacturing method of the semiconductor device of description. 10. The semiconductor device according to claim 5, wherein the steps from the sublimation of the first gate material film to the step of forming the third gate material film are performed without being exposed to the atmosphere. Production method. In the step of sublimating the first gate material film, according to any one of claims 5 to 10 heat treatment temperature was as 800 ° C. or less, and characterized by a heat treatment atmosphere with 1 × 10 ⁵ Pa or less semiconductor Device manufacturing method.

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