JP4040357B2 - Clock transmission apparatus and image forming apparatus using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to EMI countermeasures in an apparatus that transmits a clock used in common between circuits, and particularly relates to a clock whose timing needs to be strictly matched between some circuits. The present invention relates to an image forming apparatus using a clock that needs to be strictly matched.
[0002]
[Prior art]
In recent years, the frequency of a clock generated by a crystal oscillator or the like has increased, and countermeasures for EMI (Electromagnetic Interference) have become necessary. EMI noise can be dealt with to some extent by using a shield plate for circuit boards, etc., but the clock transmission line was routed in order to use a common clock between circuits separated from each other. In such a case, it is not easy to take sufficient measures due to leakage from the gap of the shield housing.
[0003]
In particular, in an image forming apparatus such as a copying machine or a facsimile machine, a CCD reference clock for reading a document image is often arranged between a plurality of substrates structurally, and the frequency itself is relatively high. Therefore, there are frequent cases of problems as EMI.
[0004]
On the other hand, the EMI noise level is a value obtained by integrating the electromagnetic wave received by the antenna for each frequency component for a predetermined time. Therefore, in the conventional EMI countermeasure, the frequency of the clock is always changed, so A spread spectrum technique for suppressing radiation noise is used. For example, USP. No. 5,488,627.
[0005]
However, such a conventional technique can be applied to a circuit such as a microprocessor in which a certain degree of fluctuation is allowed in the clock frequency. However, in the image forming apparatus, for example, a polygon mirror and the CCD are used. In some cases, there are circuits whose timings must be strictly matched.
[0006]
Therefore, another conventional technique for solving such a problem is shown in FIG. In this clock transmission device 81, the clock CLK generated by the clock oscillation circuit 82 is directly supplied from the transmission buffer 83 via the clock transmission path 84 and the reception buffer 85 to the device 86 whose timing needs to be strictly matched. The The clock CLK is modulated by the modulation circuit 87 into the spread spectrum clock CLKa, and then transmitted from the transmission buffer 88 to the device 91 to which frequency fluctuation is allowed via the clock transmission path 89 and the reception buffer 90. Supplied.
[0007]
[Problems to be solved by the invention]
However, the conventional technology as described above has a problem that the clock transmission path 84 to which no spread spectrum modulation is applied remains, and EMI noise cannot be reliably suppressed.
[0008]
An object of the present invention is to provide a clock transmission device and an image forming apparatus that can maintain strict timing between specific circuits while suppressing EMI noise.
[0009]
[Means for Solving the Problems]
The clock transmission device according to the present invention is a device for transmitting a clock to use a common clock between a plurality of circuits. A clock transmission line that distributes the received clock to the plurality of reception side circuits, and a part of the reception side circuit that is not allowed to fluctuate in frequency, despreading the spectrum spread clock from the clock transmission line, And a demodulating circuit for restoring the clock without frequency fluctuation.
[0010]
According to the above configuration, when taking measures against EMI noise on a clock routed to match the timing between circuits, first, a spread spectrum technique is used to ensure the EMI noise in all clock transmission paths. To suppress. Then, it is necessary to match the timing exactly as in some circuits of the image forming apparatus, and between the circuits in which the frequency fluctuation is not allowed, the spectrum spread clock is despread so that the frequency fluctuation does not occur. Restore the clock and use it in common.
[0011]
Therefore, when transmitting a clock, it is possible to maintain strict timing between specific circuits while reliably suppressing EMI noise.
[0012]
In the clock transmission device of the present invention, the frequency division ratio is an integer.
[0013]
According to the above configuration, the frequency divider can be realized with a simple configuration such as a counter.
[0014]
Furthermore, in the clock transmission apparatus of the present invention, the frequency division ratio is set in units of 2 factorials.
[0015]
According to said structure, the frequency divider comprised by the said counter can be comprised by a simple binary counter.
[0016]
Further, in the clock transmission device of the present invention, the demodulation circuit is set from a frequency divider that is set to an equal frequency division ratio and receives and divides the spread spectrum clock from the clock transmission path. A duty discrimination circuit is provided that receives a frequency division signal and resets the frequency divider in response to the duty of the frequency division signal.
[0017]
According to the above configuration, the phase between clocks output from the demodulation circuit can be strictly matched.
[0018]
Furthermore, an image forming apparatus of the present invention uses any one of the clock transmission devices described above.
[0019]
According to the above configuration, the image forming apparatus must strictly match the timing, such as between a polygon mirror and an image reading element, and cannot use a spread spectrum technique for EMI countermeasures. Therefore, the above method is particularly effective for EMI countermeasures.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
The following describes the first embodiment of the present invention with reference to FIG. 1 and FIG.
[0021]
FIG. 1 is a block diagram showing an electrical configuration of a clock transmission device 1 according to a first embodiment of this invention. This clock transmission device 1 is used to share the clock CLK1 generated by the clock oscillation circuit 2 between the devices 11, 21, 31, 41 of each part. It should be noted that in the clock transmission device 1, spread spectrum modulation is used for transmission of the clock CLK1, and the devices 11 and 21 operate using the modulated clock CLK2 as they are. The devices 31 and 41 operate by using clocks CLK3 and CLK4, respectively, which have exactly the same timing and have no frequency fluctuation, such as the polygon mirror and the CCD.
[0022]
For this reason, the modulation circuit 3 on the transmission side includes a frequency divider 4 that divides the clock CLK1 generated by the clock oscillation circuit 2 into 1 / m (m is an integer), and a VCO that generates the clock CLK2. Voltage controlled oscillator) 5, frequency divider 6 that divides clock CLK 2 generated by VCO 5 into 1 / m, and the phases of frequency-divided signals S 1 and S 2 from frequency dividers 4 and 6. From the phase comparator 7, a loop filter 8 that smoothes the output from the phase comparator 7, an integrator 9 that integrates the frequency-divided signal S 1 from the frequency divider 4, and the integrator 9 The adder 10 is added to the output from the phase comparator 7 and supplied to the VCO 5.
[0023]
The modulated clock CLK2 is output from the transmission buffer 51 to the clock transmission path 52. On the other hand, the receiving side of the devices 11 and 21 receives the clock CLK2 at the receiving buffers 12 and 22, and supplies the clocks CLK2 to the corresponding devices 11 and 21, respectively. On the other hand, on the reception side of the devices 31 and 41, the clock CLK2 received by the reception buffers 32 and 42 is demodulated into clocks CLK3 and CLK4 by the demodulation circuits 33 and 43, and then is transmitted to the corresponding devices 31 and 41, respectively. Given.
[0024]
The demodulating circuit 33 divides the modulated clock CLK2 by 1 / m, the VCO 35 for generating the clock CLK3, and the clock CLK3 generated by the VCO 35 by 1 / m. The frequency divider 36 that divides the frequency, the phase comparator 37 that compares the phases of the frequency-divided signals S4 and S5 from the frequency dividers 34 and 36, and the output from the phase comparator 37 are smoothed. And a loop filter 38 to be supplied to the VCO 35.
[0025]
Similarly, the demodulation circuit 43 includes a frequency divider 44 that divides the modulated clock CLK2 into 1 / n (n is an integer), a VCO 45 that generates the clock CLK4, and a clock that is generated by the VCO 45. From the frequency divider 46 that divides CLK4 into 1 / n, the phase comparator 47 that compares the phases of the frequency-divided signals S6 and S7 from the frequency dividers 44 and 46, and the phase comparator 47 And a loop filter 48 for smoothing the output of the signal and supplying it to the VCO 45.
[0026]
FIG. 2 is a waveform diagram for explaining the operation of the clock transmission apparatus 1 configured as described above. In the modulation circuit 3, the configuration excluding the integrator 9 and the adder 10 is a normal phase-locked loop circuit configuration. In this case, the configuration is generated by the clock CLK1 generated by the clock oscillation circuit 2 and the VCO5. Since the frequency dividing ratios of the frequency dividers 4 and 6 are both equal to 1 / m, the clock CLK2 is a signal having the same frequency and the same phase.
[0027]
However, in this modulation circuit 3, when the level of the frequency-divided signal S1 from the frequency divider 4 is switched, the integration output S3 of the integrator 9 to which the frequency-divided signal S1 is given is also the frequency-divided signal S1. The increase / decrease is switched in response to the level. Therefore, by adding the integrated output S3 to the output from the loop filter 8, the clock CLK2 has a center frequency equal to the clock CLK1, and a signal to which fluctuation is given to the frequency in the period of the divided signal S1. It has become.
[0028]
As a result, the EMI noise level in the clock transmission path 52 can be reliably suppressed. The divided signal S1 and the divided signal S2 are derived so that the phase comparator 7 derives outputs so that the phases of the divided signal S1 and the divided signal S2 are equal to each other. As shown by 2, they are synchronized with each other.
[0029]
On the other hand, the demodulating circuits 33 and 43 have a normal phase-locked loop circuit configuration. Since the phase comparators 37 and 47 derive outputs so that the phases between the frequency-divided signal S4 and the frequency-divided signal S5 and the phase between the frequency-divided signal S6 and the frequency-divided signal S7 are equal to each other, Even if there is a phase difference at the start of transmission, when a steady state is reached, they are synchronized with each other as shown in FIG. Further, since the frequency dividing ratios between the frequency dividers 34, 36 and 44, 46 are 1 / m and 1 / n, respectively, the clocks CLK3 and CLK4 have the same frequency as shown in FIG. The signal is equal to the center frequency of CLK2 and the period of each pulse is constant and does not fluctuate, that is, a signal equal to the clock CLK1. Thereby, the exact timing between the devices 31 and 41 can also be maintained.
[0030]
Further, since the frequency dividing ratios m and n are integers, the frequency dividers 4, 6; 34, 36; 44, 46 can be realized with a simple configuration such as a counter.
[0031]
The clocks CLK1, CLK3 and CLK4 do not have to have the same frequency as described above, and the frequency dividing ratios between the frequency dividers 34 and 36 and the frequency dividers 44 and 46 are mutually different. By setting to different values, different frequencies can be set.
[0032]
In the above description, the frequency dividing ratios of the frequency dividers 34 and 36 and the frequency dividers 44 and 46 are m and n. However, as shown in FIG. If the frequencies are equal, the same frequency division ratio is usually selected (n = m).
[0033]
Furthermore, in FIG. 2, as described above, the frequencies of the demodulated clock CLK3 and the clock CLK4 are equal, and the frequency-divided signals S6 and S7 on the reception side are equal to the frequency-divided signals S4 and S5. As in n = 2m, 1 / n of the division ratio on the reception side may be set to 1 / integer with respect to 1 / m of the division ratio on the transmission side. However, when n = m, even if there is a phase difference between the frequency-divided signals S1, S2 (S4, S5) and the frequency-divided signals S6, S7 at the start of transmission, the phase comparator 47 does not Since the output is derived so that the duty between the frequency signals S1, S2 (S4, S5) and the frequency-divided signals S6, S7 is maintained at 50%, as shown in FIG. If the frequency division ratio n is 2k (k is an integer) multiple of m while being synchronized, the frequency division signals S6 and S7 can be divided even if they are switched at any switching timing of the clock CLK2. Since 50% of the duty of the signals S1, S2 (S4, S5) can be maintained, the phase of the frequency-divided signals S1, S2 (S4, S5) may be shifted and stabilized. An example in the case of k = 1, that is, n = 2m is indicated by reference numerals S6 ′ and S7 ′ in FIG.
[0034]
The following describes the second embodiment of the present invention with reference to FIG.
[0035]
FIG. 3 is a block diagram showing an electrical configuration of the clock transmission device 61 according to the second embodiment of this invention. The clock transmission device 61 is similar to the clock transmission device 1 described above, and corresponding portions are denoted by the same reference numerals and description thereof is omitted. It should be noted that in this clock transmission device 61, the frequency dividing ratios of the frequency dividers 4a and 6a of the modulation circuit 3a on the transmission side and the frequency dividers 34a and 36a; 44a and 46a of the demodulation circuits 33a and 43a on the reception side are the same. 2 is set in factorial units.
[0036]
Therefore, these frequency dividers 4a, 6a; 34a, 36a; 44a, 46a constituted by the counter can be constituted by simple binary counters.
[0037]
The following describes the third embodiment of the present invention with reference to FIGS. 4 to 7 and FIG.
[0038]
FIG. 4 is a block diagram showing an electrical configuration of the clock transmission apparatus 71 according to the third embodiment of the present invention. The clock transmission device 71 is similar to the above-described clock transmission device 61, and corresponding portions are denoted by the same reference numerals and description thereof is omitted. It should be noted that in the clock transmission device 71, the frequency dividers 34b and 44b of the demodulation circuits 33b and 43b on the receiving side respond to the frequency-divided signals S4 ″ and S6 ″ from the frequency dividers 34b and 44b. The duty is discriminated by the duty discriminating circuits 39 and 49. The demodulation circuits 33b and 43b use frequency dividers 34b and 36b; 44b and 46b having equal frequency division ratios (1/2 ^{n in} FIG. 4).
[0039]
FIG. 5 is a block diagram showing a configuration example of the phase comparators 37 and 47. The phase comparators 37 and 47 are realized by a PLLIC 14046 manufactured by Motorola, etc., and generally include a D flip-flop 72, OR gates 73 and 74, and an exclusive OR gate 75.
[0040]
The input PCBin which is the frequency-divided signals S5 ″ and S7 ″ from the frequency dividers 36b and 46b on the VCO 35 and 45 side, and the frequency-divided signals S4 ″ and S6 from the frequency dividers 34b and 44b on the clock CLK2 side. The exclusive OR gate 75 supplies the output PC1out as shown in FIG. 6 to the duty determination circuits 39 and 49 with respect to the two inputs with the input PCAin being ''.
[0041]
The two inputs PCBin and PCAin are given to one input of OR gates 73 and 74, respectively, and the other inputs of these OR gates 73 and 74 have outputs / Q, Q ( / Represents that it is an inverted output), and the outputs of these OR gates 73 and 74 are applied to the set input S and reset input R of the D flip-flop 72, respectively. Accordingly, the output PC2out as shown in FIG. 7 is output from the output Q of the D flip-flop 72 and input to the loop filters 38 and 48. The smooth output from the loop filters 38 and 48 is also shown as VCOin in FIG.
[0042]
By the phase comparators 37 and 47 configured as described above, the output PC2out to the loop filter controls the VCOs 35 and 45 so that the rising edges of the two inputs PCBin and PCAin coincide.
[0043]
On the other hand, since the frequency dividers 36b and 46b divide the output of the VCOs 35 and 45, the duty is constant at 50%, and the output PC1out of the exclusive OR gate 75 is the frequency signal S4 ′. When the rising edge of ', S6''coincides with the frequency-divided signals S5 ", S7" and the duty of the frequency-divided signals S4 ", S6" becomes 50%, the output is always low. If the duty of the circumferential signals S4 ″ and S6 ″ deviates from 50%, the difference from the frequency-divided signals S5 ″ and S7 ″ becomes high.
[0044]
Therefore, the duty determination circuits 39 and 49 determine whether the duty is higher or lower than 50% by comparing the output PC1out of the exclusive OR gate 75 with the frequency-divided signals S4 ″ and S6 ″. The amount of duty deviation can be determined by comparing the output PC1out with the clocks CLK3 and CLK4 from the VCOs 35 and 45. Accordingly, the duty discriminating circuits 39 and 49 reset the frequency dividers 34b and 44b at the rising timing or the falling timing of the integration output S3 from the integrator 9, whereby the frequency-divided signals S4 '' and S6 are reset. The phase of '' and the divided signals S5 '' and S7 '', and thus the phase of the clock CLK3 and the clock CLK4, can be matched exactly. FIG. 2 shows a state where the divided signals S4 ″, S5 ″, S6 ″ and S7 ″ are in phase with the divided signals S1 and S2.
[0045]
As described above, the clock transmission apparatuses 1, 61, 71 of the present invention transmit the clock CLK2 obtained by spectrum-spreading the clock CLK1, and take measures against EMI, between the demodulated clocks CLK3, CLK4 and / or their This is particularly effective for an image forming apparatus in which the timings between the clocks CLK3 and CLK4 and the clock CLK1 must be strictly matched.
[0046]
【The invention's effect】
As described above, the clock transmission apparatus according to the present invention first uses a spread spectrum technique to apply a countermeasure against EMI noise to a clock routed so as to match the timing between circuits. It is necessary to reliably suppress the EMI noise and to precisely match the timing, and between circuits in which frequency fluctuation is not allowed, a spread spectrum clock is despread to restore the clock without frequency fluctuation. Commonly used.
[0047]
Therefore, it is possible to maintain strict timing between specific circuits while reliably suppressing EMI noise.
[0048]
In the clock transmission device of the present invention, the frequency division ratio is an integer as described above.
[0049]
Therefore, the frequency divider can be realized with a simple configuration such as a counter.
[0050]
Furthermore, the clock transmission apparatus of the present invention sets the frequency division ratio in units of 2 as described above.
[0051]
Therefore, the frequency divider constituted by the counter can be constituted by a simple binary counter.
[0052]
Further, as described above, the clock transmission device of the present invention sets the demodulation circuits to equal frequency division ratios, and receives and divides the spread spectrum clock from the clock transmission path. A frequency division signal is input from the frequency divider, and a duty discrimination circuit is provided for resetting the frequency divider in response to the duty of the frequency division signal.
[0053]
Therefore, the phase between clocks output from the demodulation circuit can be strictly matched.
[0054]
Further, as described above, the image forming apparatus of the present invention uses any one of the clock transmission devices described above.
[0055]
Therefore, the image forming apparatus is equipped with a circuit that must strictly match the timing, such as between a polygon mirror and an image reading element, and cannot use a spread spectrum technique for EMI countermeasures. It is particularly effective.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an electrical configuration of a clock transmission apparatus according to a first embodiment of this invention.
FIG. 2 is a waveform diagram for explaining the operation of the clock transmission device of FIGS. 1 and 4;
FIG. 3 is a block diagram showing an electrical configuration of a clock transmission apparatus according to a second embodiment of the present invention.
FIG. 4 is a block diagram showing an electrical configuration of a clock transmission apparatus according to a third embodiment of the present invention.
5 is a block diagram showing an example of the configuration of a phase comparator in the clock transmission apparatus shown in FIG.
6 is a waveform diagram for explaining the operation of the phase comparator shown in FIG. 5. FIG.
7 is a waveform diagram for explaining the operation of the phase comparator shown in FIG. 5; FIG.
FIG. 8 is a block diagram showing an electrical configuration of a conventional clock transmission device.
[Explanation of symbols]
1, 61, 71 Clock transmission device 2 Clock oscillation circuit 3, 3a Modulation circuit 4, 6; 4a, 6a Frequency divider 5, 35, 45 VCO
7, 37, 47 Phase comparator 8, 38, 48 Loop filter 9 Integrator 10 Adder 11, 21, 31, 41 Device 12, 22, 32, 42 Reception buffer 33, 33a, 33b; 43, 43a, 43b Demodulation Circuits 34, 34a, 34b; 36, 36a, 36b Frequency dividers 39, 49 Duty determination circuits 44, 44a, 44b; 46, 46a, 46b Frequency divider 51 Transmission buffer 52 Clock transmission path 72 D flip-flops 73, 74 OR Gate 75 Exclusive OR gate

Claims (5)

A clock oscillation circuit, a transmission side circuit, a plurality of reception side circuits, and a clock transmission path;
In order to use the clock oscillated from the clock oscillation circuit in each of the plurality of reception side circuits, the clock is transmitted to each of the plurality of reception side circuits via the transmission side circuit and the clock transmission path. In transmission equipment,
The transmission side circuit has a modulation circuit that spreads a spectrum of a clock oscillated from the clock oscillation circuit and outputs a modulation clock obtained by the spread,
The clock transmission path has a transmission path for transmitting the modulation clock output from the modulation circuit to each of the plurality of reception side circuits,
A first receiver circuit included in the plurality of receiver circuits is set to supply the first device without demodulating the modulation clock;
The second receiving circuit included in the plurality of receiving circuits has a demodulating circuit that despreads the modulated clock and outputs a demodulated clock obtained by the despreading, and supplies the demodulated clock to the second device A clock transmission device that is set to The modulation circuit includes:
A first frequency divider that outputs a first frequency-divided signal by dividing a clock oscillated from the clock oscillation circuit; a frequency divider having the same frequency division ratio as the first frequency divider; and the modulation A second divider that outputs a second divided signal by dividing a clock; a first phase comparator that compares the phase of the first divided signal and the phase of the second divided signal; A first loop filter for smoothing and outputting a comparison result of the first phase comparator; an integrator for outputting an integration signal by integrating the first frequency-divided signal; and an output of the first loop filter at the output An adder that outputs an addition signal obtained by adding the integration signals, and a first voltage-controlled oscillator that outputs the modulation clock based on the addition signal,
The demodulation circuit includes:
A third frequency divider that outputs a third frequency-divided signal by dividing the modulation clock transmitted through the clock transmission path; and a frequency divider having the same frequency division ratio as the third frequency divider. And a fourth divider that outputs a fourth divided signal by dividing the demodulated clock, and a second phase that compares the phase of the third divided signal with the phase of the fourth divided signal. A comparator, a second loop filter that smoothes and outputs a comparison result of the second phase comparator, and a second voltage-controlled oscillator that outputs the demodulated clock based on the output of the second loop filter. The clock transmission device according to claim 1, further comprising: 3. The clock according to claim 2, wherein a division ratio of each of the first divider, the second divider, the third divider, and the fourth divider is an integer. Transmission equipment. 4. The frequency division ratio of each of the first frequency divider, the second frequency divider, the third frequency divider, and the fourth frequency divider is a factorial of 2. 5. The clock transmission device described. An image forming apparatus comprising the clock transmission device according to claim 1.

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