JP4026425B2 - Digital detector - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital detector. More specifically, for example, the present invention relates to a digital detection device that performs detection so that noise in a flaw detection signal of eddy current flaw detection can be suppressed using a phase difference from the flaw signal.
[0002]
[Prior art]
Conventionally, eddy current flaw detection has been performed as a flaw detection method for detecting a flaw on the surface layer portion of a conductive specimen in a non-contact manner (see, for example, JP-A-2001-296279). In eddy current testing, the eddy current generated in the specimen is affected by many other factors such as the geometry of the specimen, electromagnetic characteristics, and the relative position between the specimen and the sensor coil. Signal processing for suppressing noise due to noise is important for reliably detecting flaws. As such signal processing, phase detection (phase analysis) is performed in which a flaw detection signal is detected so as to suppress noise by using a phase difference between the flaw signal and noise in an AC flaw detection signal. (For phase detection in an electrostatic sensor, see JP-A-8-278336).
[0003]
The phase detection is intended to improve the S / N ratio by suppressing noise using the phase difference under a flaw detection condition set so that a large phase difference occurs between the flaw signal and noise. As a specific implementation method, a synchronous detection method is representative. The synchronous detection method includes a method using an electronic switching circuit and a method using a multiplication operation element. As shown in FIG. 10, the synchronous detection by the switching circuit is performed by switching among the flaw detection signals in FIG. The phase difference corresponding to the area S ′ of the shaded portion of the figure is obtained by obtaining only the output waveform of the figure (c) by cutting out only the period when the control signal of the figure (b) is ON by the circuit. θ ′ is obtained.
[0004]
On the other hand, as shown in FIG. 11, in the synchronous detection by the multiplication operation element, the reference signal q ′ and the flaw detection signal p ′ multiplied by K1 by the amplifier 102 are input to the multiplier 101 as the multiplication operation element. the detection signal f _d obtained by multiplying is passed through the low-pass filter (LPF) 103, so as to multiply K2 phase component extracted by this is passed through the amplifier 104 to obtain an average of the detection signal f _d Thus, the phase difference θ ′ is obtained.
[0005]
However, since all of these conventional phase detections use analog elements as arithmetic elements such as switching circuits and multipliers, the following problems generally occur.
[0006]
(1) Since the detection characteristic depends on the frequency characteristic of the analog element, it cannot cope with high-frequency phase detection (when a commercially available analog multiplier is used, the corresponding frequency is limited to 10 megahertz).
[0007]
(2) The measurement accuracy depends on the accuracy of the analog element, and high accuracy is difficult.
[0008]
(3) A high-speed analog multiplier is expensive.
[0009]
Further, there are the following problems when phase detection of eddy current flaw detection is performed by an analog multiplier.
[0010]
(11) In phase detection of eddy current flaw detection, it is normal that the flaw detection signal is accompanied by not only the phase change but also the amplitude change. Therefore, the result of multiplication is changed by the amplitude change, and the amount of change only in the phase is taken out. Have difficulty.
[0011]
(12) When the amplitude change is extremely larger than the phase change, the circuit must be adjusted with the maximum value of the amplitude change so as to avoid saturation, and therefore the S / N ratio is lowered and the accuracy is deteriorated for a signal having a small amplitude. . For this reason, it is difficult to handle a signal having a large input change such as a scanning eddy current flaw detection method.
[0012]
(13) When a printed coil is used as a sensor coil, the characteristics of each coil vary greatly, and it is difficult to cope with a case where the flaw detection apparatus has a plurality of channels.
[0013]
(14) In flaw detection of nonmagnetic steel, the phase change is extremely small, and the output saturation of the analog multiplier is likely to occur.
[0014]
[Problems to be solved by the invention]
The present invention has been made in view of the problems of the prior art, and provides a digital detection device capable of improving detection accuracy while reducing costs by performing phase detection by digital signal processing. It is an object.
[0015]
[Means for Solving the Problems]
The digital detector of the present invention is a digital detector comprising a phase detector, an amplitude detector, and a phase calculator,
An input signal-side zero-cross detector that detects a zero-cross of an input signal sampled at a predetermined interval; an input-side frequency divider disposed downstream of the input signal-side zero-cross detector; A reference signal-side zero-cross detector that detects a zero-cross of a reference signal sampled at intervals, a reference-side frequency divider disposed downstream of the reference-signal-side zero-cross detector, and a phase signal generator ,
The division ratio of the input side divider and the reference side divider is the same,
The input signal side zero cross signal is divided by the input side divider so that the error is constant regardless of the measurement timing,
The reference signal side zero cross signal is frequency-divided by the reference side frequency divider so that the error is constant regardless of the measurement timing,
The phase signal generation unit generates a phase signal by taking an exclusive OR of the frequency-divided input signal side zero-cross signal and the frequency-divided reference signal side zero-cross signal to the phase calculation unit. Output,
The amplitude detector detects the amplitude of the input signal sampled at the predetermined interval and outputs the amplitude signal to the phase calculator,
The phase calculation unit performs a predetermined calculation process on the phase signal and the amplitude signal, and outputs the phase and amplitude of the input signal as a digital signal.
[0018]
[Action]
Since the digital detection device of the present invention is configured as described above, high-frequency phase detection can be achieved and high accuracy can be realized without depending on the frequency characteristics and accuracy of the element as in the case of an analog detection device. Further, since the phase and amplitude are detected independently, the configuration of each detection unit can be optimized according to the detection target, and detection accuracy can be improved.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, although the present invention is explained based on an embodiment, referring to an accompanying drawing, the present invention is not limited only to this embodiment.
[0020]
Embodiment 1
FIG. 1 shows a schematic configuration of a digital detector (hereinafter simply referred to as a detector) according to Embodiment 1 of the present invention. This detector A receives, for example, a flaw detection signal including a flaw signal and noise in eddy current flaw detection. It is assumed that detection is performed, that is, the phase and amplitude of the input signal p are measured so as to suppress the noise by using the difference in phase between the flaw signal and the noise as the signal p.
[0021]
More specifically, the detector A detects and detects the phase difference φ (see FIG. 2) between the input signal p sampled at a predetermined interval and a reference signal (control signal) q sampled at the predetermined interval. A phase detector 1 that outputs a signal r (hereinafter referred to as a phase signal) r indicating the phase difference φ, and an amplitude B (see FIG. 2) of the input signal p, and a signal (hereinafter referred to as an amplitude signal) indicating the detection result. The phase of the input signal p is calculated based on the amplitude detection unit 2 that outputs s, and the output signals r and s of the phase detection unit 1 and the amplitude detection unit 2, and the calculated phase and the amplitude detection unit 2 The phase calculation unit 3 that outputs the detected amplitude as, for example, a 12-bit digital signal is provided as a main component.
[0022]
The phase detection unit 1 detects a zero cross of the input signal p and outputs a signal t (hereinafter referred to as an input signal side zero cross signal) t representing the detection result, and a reference signal The zero cross of q is detected, and a reference signal side zero cross signal t which outputs a signal (hereinafter referred to as a reference signal side zero cross signal) u indicating the detection result, and the input signal side zero cross signal t and the reference signal side zero cross signal u And a phase signal generation unit 13 that generates a phase signal r based on the phase signal r.
[0023]
As shown in FIG. 2, each of the zero-cross detectors 11 and 12 includes a reference signal q (see FIG. 2A) that is a sine wave signal, an input signal p (see FIG. 2B), and GND (0 volts). A zero cross that converts each signal p, q into a rectangular wave by outputting a high level signal while the voltage of each signal p, q is positive and outputting a low level signal when the voltage is negative • Configured as a comparator.
[0024]
As shown in FIG. 2C, the phase signal generation unit 13 is an exclusive OR operation circuit that takes an exclusive OR when the input signal side zero cross signal t and the reference signal side zero cross signal u are high level signals. It is composed of That is, the width of each rectangular pulse r ₁ , r ₂ ,... Output from the phase signal generator 13 as the phase signal r represents the phase difference φ. Note that the frequency of the phase signal r is twice the frequency of the input signal p and the reference signal q.
[0025]
The amplitude detection unit 2 digitizes the envelope detection circuit 21 that performs envelope detection on the input signal p, and the output signal (analog signal) of the envelope detection circuit 21 and outputs it as an amplitude detection signal s. And a D converter 22.
[0026]
The phase calculation unit 3 includes, for example, an FPGA (Field Programmable Gate Array), calculates the phase of the input signal p based on the phase signal r and the amplitude signal s, and determines a predetermined value for the calculation result. An error correction process is performed and output.
[0027]
Here, the error correction processing is performed by calculating the slew rate of the input signal p using the amplitude signal s and correcting the influence on the zero cross detection due to the change in the slew rate.
[0028]
Next, with reference to FIG. 3, the sampling method in the detector A will be described. In the detection device A, the input signal p and the reference signal q are set to a predetermined value from a cycle (hereinafter referred to as a signal cycle) T ₁ (or a cycle obtained by multiplying the signal cycle T ₁ by the inverse of the sampling interval adjustment coefficient K described later). Sampling is performed at a period (hereinafter referred to as a sampling period) T ₂ that is shifted by time (hereinafter referred to as a virtual sampling time) Δt, and an equivalent result is obtained that is virtually sampled at a period of Δt.
[0029]
That is, the point W ₁ is sampled in the first sampling, the point W ₂ is sampled in the _second sampling, and the phase of the sampling point W is shifted by the virtual sampling time Δt. By doing so, it is possible to obtain the same sampling value as when the input signal p and the reference signal q are sampled at a period of Δt. However, d is _{d = T 1 / (T 1} -T 2) = f 2 / (f 2 -f 1)
It is.
[0030]
Here, f _{1 is} the frequency of the input signal p and the reference signal q (hereinafter referred to as signal frequency), and f _{2 is the} frequency at which the input signal p and the reference signal q are actually sampled (hereinafter referred to as sampling frequency).
[0031]
Therefore, by setting the division number n and the sampling interval adjustment coefficient K defined by the following formulas (1) and (2) to appropriate values, the frequencies of the input signal p and the reference signal q are high (for example, about 40 megabytes). In the case of (hertz), it is possible to sample with sufficient accuracy to obtain a sufficient phase detection resolution.
[0032]
n · Δt = 1 / f ₁ (1)
[0033]
f ₂ = {n · K / (n−1)} · f ₁ (2)
[0034]
However, the accuracy of the phase detected by this method depends on the accuracy of the signal frequency f ₁ and the sampling frequency f ₂ , and if the accuracy of about ± 1 degree is desired, the signal frequency f ₁ is 1. In the case of megahertz or so, it is necessary to have an accuracy of 10 pM, that is, about 7 digits after the decimal point. Further, since the measurement time is expressed by (Δt · n) / K, the sampling time can be shortened by increasing the sampling interval adjustment coefficient K. However, in this case, since the sampling frequency f ₂ is increased, the phase accuracy is deteriorated.
[0035]
As described above, in the detection device A of the first embodiment, the zero crosses of the input signal p and the reference signal q, which are sine wave signals, are detected by the zero cross detection units 11 and 12 including the zero cross comparators, and are excluded based on this. A phase signal r representing a phase difference φ between the signals p and q is generated by a phase signal generator 13 composed of a logical OR circuit, and the phase signal r and an amplitude signal s which is an output signal of the amplitude detector 2 Since the phase detection is performed by digital signal processing such that the phase of the input signal p is calculated on the basis of the above, it depends on the frequency characteristics and accuracy of the element as in the case of the conventional analog phase detection. High-frequency phase detection becomes possible (according to experiments by the inventors, it was possible to cope with a high frequency of about 40 megahertz) and high accuracy is facilitated. . As a result, it is not necessary to use an expensive analog element with high speed and high accuracy, and the cost can be reduced (about one-tenth of the case where an analog multiplier is used).
[0036]
As a result, when multiple printed coils are used as sensor coils for eddy current flaw detection, even when the characteristics of each coil vary greatly, it is possible to cope with less adjustment than the conventional analog method and to detect with high accuracy. Can do. For this reason, even when applied to a flaw detection apparatus that normally has a plurality of channels, it is not necessary to prepare an expensive analog multiplier for each channel, and the cost can be further reduced.
[0037]
Further, an exclusive OR of the zero cross signals t and u of the input signal p and the reference signal q is taken, and the phase difference φ between the signals p and q is detected from the width of each rectangular pulse obtained thereby. Therefore, it is possible to accurately detect the phase difference φ regardless of whether the duty ratio of the zero cross signals t and u is 50%.
[0038]
Furthermore, the amplitude of the input signal p is detected by the amplitude detector 2 including the envelope detection circuit 21 at the same time as the phase detection is performed, and the error in the phase calculation result is corrected using this, so that the detection accuracy is improved. improves. In this connection, because the phase and amplitude are detected independently by different detectors 1 and 2, the characteristics of each detector 1 and 2 can be optimized according to the detection target. The detection accuracy is improved.
[0039]
Furthermore, by sampling at a frequency f ₂ slightly shifted from the signal frequency f ₁ so that sufficient phase detection resolution can be obtained even when the frequency of the input signal p is high, for example, a high-speed A / D converter can be obtained. It is possible to sample with sufficient accuracy without using it. Further, the sampling rate can be increased by sampling at a frequency f ₂ slightly shifted from a frequency N times the signal frequency f ₁ .
[0040]
Embodiment 2
FIG. 4 shows a schematic configuration of a detection device according to the second embodiment of the present invention. This detection device A1 is a modification of the phase detection unit 1 of the detection device A of the first embodiment. The same as in the first embodiment. Only the modified part will be described below.
[0041]
That is, the phase detector 1A of the detector A1 includes the saturation circuits 14 and 15 before the zero cross detectors 11A and 12A having the same configuration as that of the first embodiment, and the zero cross detectors 11A and 12A. The frequency dividers 16 and 17 are interposed between the phase signal generator 13A having the same configuration as that of the first embodiment, and the detection accuracy is further improved.
[0042]
FIG. 5 shows a detailed configuration of the saturation circuits 14 and 15. The saturation circuits 14 and 15 suppress the influence of changes in the frequency and amplitude of the input signal p and the reference signal q on the detection timing of the zero cross, and the zero cross detection unit 11A, so that the zero cross can be reliably detected even in a signal having a small amplitude. The amplitude of the signal input to 12A is adjusted, and the amplifiers 14a and 15a, which are high-gain operational amplifiers (amplifiers) for amplifying the input signal p and the reference signal q, and the amplifiers 14a and 15a It comprises attenuators 14b and 15b for adjusting the amplitudes of the amplified input signal p and reference signal q to match the input ranges of the zero cross detectors 11A and 12A.
[0043]
That is, the high-speed comparator generally tends to oscillate when the slew rate of the input signal is low. For this reason, the hysteresis voltage E _H (see FIG. 6B) is set in the transition region to avoid oscillation. It is normal.
[0044]
However, as shown in FIG. 6, by providing this hysteresis voltage E _H , an error e occurs in the zero-cross detection timing or the amplitude is small even though the two sine wave signals W1 and W2 have the same period and phase. There arises a problem that the zero cross of the signal W3 is not detected.
[0045]
FIG. 7 shows an example of the relationship between the error e and the input signal (reference signal) in the saturation circuit.
[0046]
In view of this, the amplitudes of the signals p and q input to the zero-cross detectors 11A and 12A by the saturation circuits 14 and 15 are increased, and the error e is reduced as much as possible by adjusting so as to reduce the influence of the inclination. At the same time, zero crossing can be reliably detected even at low input voltages (for example, about 100 millivolts). In addition, this makes it possible to suppress the oscillation of the comparator output even when it is difficult to set an appropriate hysteresis voltage E _H.
[0047]
Next, the frequency dividers 16 and 17 will be described with reference to FIG. The frequency dividers 16 and 17 divide the zero-cross signals t and u and output the frequency-divided signals v and w to the phase signal generator 13A. That is, the input signal p and the reference signal q normally include an offset due to a slight imbalance such as circuit characteristics, and as a result, each zero cross signal t, u includes an error. The frequency dividers 16 and 17 divide the zero cross signals t and u so as to easily correct errors due to the offsets of the input signal p and the reference signal q, and the divided signals v and w Is output.
[0048]
For example, as shown in FIG. 8, consider a case where the input signal p has an offset of voltage ES (hereinafter referred to as an offset voltage) ES (the same applies to the case where the reference signal q has an offset). At this time, the width α of each square pulse t ₁ , t ₂ ... Constituting the zero-cross signal t of the input signal p is different from the original width β when there is no offset. It is included in the signal t. If the phase signal r is generated so as to implement an exclusive OR operation with respect to the zero-crossing signal u of the zero-crossing signal t and a reference signal q containing this error, each of the rectangular pulse r ₁ constituting the phase signal r, r ₂ ,... oscillates such that the width increases or decreases from the original width by time {(α−β) / 2} every half cycle of the input signal p. For this reason, when the measurement timing is not constant, the correction becomes difficult.
[0049]
That is, when the error is oscillating without frequency division, at least two pieces of continuous data are required to obtain the true value. That is, since it is necessary to compare which data is larger by (α−β) / 2, data that is continuous with the first time and the second time is required. When continuous data cannot be obtained, the error of the obtained value is ± (α−β) / 2 at the maximum. On the other hand, in the case of the frequency-divided signal, the error is constant (β−α) / 2 in the example shown in FIG. 8, and therefore the same value can be obtained at any timing. For example, as shown in FIG. 9, when the measurement values a and b are obtained by measurement continuously with timing 1 and timing 2, a is shifted by − (α−β) / 2 from the true value, Assuming that b is deviated by + (α−β) / 2 from the true value, if a <b, a includes an error of − (α−β) / 2, and b is + (α−β). It can be seen that an error of / 2 is included. However, when the measurement is performed repeatedly like the timing 1 and the timing 3, it is unclear which measurement value is small, so the error cannot be specified. That is, in order to specify an error, it is necessary to measure continuously like timing 1 and timing 2 or timing 2 and timing 3.
[0050]
Therefore, each of the zero cross signals t and u is frequency-divided by the frequency dividers 16 and 17, and the phase signal r is generated by taking the exclusive OR of the frequency-divided signals v and w. By making the error included in r constant regardless of the measurement timing (always-{(α−β) / 2} in the illustrated example), the error can be easily corrected.
[0051]
As described above, in the detection device A1 according to the second embodiment, the input signal p and the reference signal q whose amplitudes are adjusted by the saturation circuits 14 and 15 are input to the zero-cross detection units 11A and 12A. The detection accuracy can be improved by eliminating the influence on the outputs of the detection units 11A and 12A as much as possible. Also, detection of a low voltage signal is possible.
[0052]
Further, since the phase signal r is generated using the zero-cross signals v and w divided by the frequency dividers 16 and 17, it is easy to correct errors caused by the offsets of the input signal p and the reference signal q.
[0053]
【The invention's effect】
As described above in detail, according to the digital detection device of the present invention, high-frequency phase detection can be achieved and high accuracy can be realized without depending on the frequency characteristics and accuracy of the element as in the case of the analog detection device. Excellent effect is obtained.
[0054]
In addition, according to the digital detection device of the present invention, since the phase and amplitude are detected independently, the configuration of each detection unit can be optimized according to the detection target, and the detection accuracy can be improved. An effect is also obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a detector according to Embodiment 1 of the present invention.
FIGS. 2A and 2B are schematic diagrams illustrating a basic principle of detection by the detection device according to the first embodiment, in which FIG. 2A illustrates a reference signal input to a phase detection unit, and FIG. 2B illustrates input to a phase detection unit; (C) shows the output signal of the phase detector.
FIG. 3 is an explanatory diagram relating to a sampling method in the detection device.
FIG. 4 is a block diagram showing a schematic configuration of a detector according to Embodiment 2 of the present invention.
FIG. 5 is a block diagram showing a schematic configuration of a saturation circuit of the detection device.
6A and 6B are explanatory diagrams for explaining the operation principle of the saturation circuit, in which FIG. 6A shows various signals input to the zero-cross detection unit, and FIG. 6B shows a partially enlarged view thereof.
FIG. 7 is an example of a graph showing a relationship between an error and an input signal in a saturation circuit.
FIG. 8 is an explanatory diagram for explaining an operation principle of a frequency dividing circuit of the detector according to the second embodiment.
FIG. 9 is a graph schematically showing the relationship between measurement timing and measurement value.
FIG. 10 is a graph showing the principle of synchronous detection using a conventional switching circuit.
FIG. 11 is a block diagram showing a schematic configuration of a phase detector using a conventional analog multiplier.
[Explanation of symbols]
A detector 1 phase detector 2 amplitude detector 3 phase calculators 11 and 12 zero cross detector (zero cross comparator)
13 Phase signal generator (exclusive OR operation circuit)
14, 15 Saturation circuit 16, 17 Divider 21 Envelope detection circuit

Claims (1)

A digital detector comprising a phase detector, an amplitude detector, and a phase calculator,
An input signal-side zero-cross detector that detects a zero-cross of an input signal sampled at a predetermined interval; an input-side frequency divider disposed downstream of the input-signal-side zero-cross detector; and the predetermined detector A reference signal-side zero-cross detector that detects a zero-cross of a reference signal sampled at intervals, a reference-side frequency divider disposed downstream of the reference-signal-side zero-cross detector, and a phase signal generator ,
The division ratio of the input side divider and the reference side divider is the same,
The input signal side zero cross signal is divided by the input side divider so that the error is constant regardless of the measurement timing,
The reference signal side zero cross signal is frequency-divided by the reference side frequency divider so that the error is constant regardless of the measurement timing,
The phase signal generation unit generates a phase signal by taking an exclusive OR of the frequency-divided input signal side zero-cross signal and the frequency-divided reference signal side zero-cross signal to the phase calculation unit. Output,
The amplitude detector detects the amplitude of the input signal sampled at the predetermined interval and outputs the amplitude signal to the phase calculator;
The digital detection device, wherein the phase calculation unit performs predetermined calculation processing on the phase signal and the amplitude signal and outputs the phase and amplitude of the input signal as a digital signal.

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