JP4010091B2 - Memory device and manufacturing method thereof - Google Patents

Memory device and manufacturing method thereof Download PDF

Info

Publication number
JP4010091B2
JP4010091B2 JP2000082165A JP2000082165A JP4010091B2 JP 4010091 B2 JP4010091 B2 JP 4010091B2 JP 2000082165 A JP2000082165 A JP 2000082165A JP 2000082165 A JP2000082165 A JP 2000082165A JP 4010091 B2 JP4010091 B2 JP 4010091B2
Authority
JP
Japan
Prior art keywords
memory
electrode
memory cell
bank
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000082165A
Other languages
Japanese (ja)
Other versions
JP2001274344A (en
Inventor
達也 下田
Original Assignee
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーエプソン株式会社 filed Critical セイコーエプソン株式会社
Priority to JP2000082165A priority Critical patent/JP4010091B2/en
Publication of JP2001274344A publication Critical patent/JP2001274344A/en
Application granted granted Critical
Publication of JP4010091B2 publication Critical patent/JP4010091B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/02Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using elements whose operation depends upon chemical change
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/11213ROM only
    • H01L27/1122ROM only with source and drain on the same level, e.g. lateral transistors
    • H01L27/11226Source or drain contact programmed
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/0001Processes specially adapted for the manufacture or treatment of devices or of parts thereof
    • H01L51/0002Deposition of organic semiconductor materials on a substrate
    • H01L51/0003Deposition of organic semiconductor materials on a substrate using liquid deposition, e.g. spin coating
    • H01L51/0004Deposition of organic semiconductor materials on a substrate using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing, screen printing
    • H01L51/0005Deposition of organic semiconductor materials on a substrate using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing, screen printing ink-jet printing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/77Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory device, and more particularly to a semiconductor ROM (read only memory) which is a read only memory.
[0002]
[Prior art]
Generally, the contents of the semiconductor ROM are written as a fixed pattern that cannot be changed by the user when the memory device is produced. FIG. 11 is an example of an equivalent circuit diagram using a diode for a conventional semiconductor ROM. It has a simple matrix structure in which memory cells are formed at the intersections of the X direction linear electrode and the Y direction linear electrode, and the X direction linear electrode and the Y direction linear electrode are connected or connected by a diode. However, a binary state is stored for each memory cell.
[0003]
FIG. 12 schematically shows a cross section of the semiconductor ROM. An X-direction linear electrode 700 and a Y-direction linear electrode 701 are formed with the semiconductor layer 702 interposed therebetween, and a binary state is stored depending on the presence or absence of the insulating film 712. For example, the memory cell 710 corresponds to a location connected by a diode in FIG. 11, and the memory cell 711 corresponds to a location not connected.
[0004]
In the production process of a conventional semiconductor ROM, a photomask is manufactured according to a recording pattern (pattern to be written into the semiconductor ROM), and a photoresist layer is selectively exposed using this to selectively etch an insulating film layer. As a result, a fixed pattern was written.
[0005]
[Problems to be solved by the invention]
However, the conventional method of writing the storage pattern of the semiconductor ROM using a photomask has the following problems. One is that the manufacturing cost of a photomask is very high, from one hundred to several tens of millions of yen, and the price of a semiconductor ROM manufactured using it is very high. Second, since the mask pattern of the photomask cannot be changed once formed, it is necessary to manufacture a photomask for each memory pattern. Therefore, there is a problem that the recording pattern cannot be easily changed from the viewpoint of cost. The third point is that it takes about 2-3 weeks from the production of the photomask to the series of production steps including the etching of the insulating layer, and the production in a short period is difficult.
[0006]
The present invention was devised to solve such a conventional problem, and a memory device manufacturing technique capable of manufacturing semiconductor ROMs having various recording patterns at low cost and easily in a shorter period of time. The purpose is to provide.
[0007]
[Means for Solving the Problems]
A method of manufacturing a memory device according to the present invention is a method of manufacturing a memory device that stores a state based on the presence or absence of a coating insulating film on an electrode surface at a memory cell position, and an inkjet head is applied to the electrode surface at a predetermined memory cell position The insulating material is selectively discharged to cover the electrode surface at the predetermined memory cell position with the insulating material. Thereby, the stored content can be easily changed by changing the setting of the inkjet.
[0008]
Preferably, the method includes a step of forming a bank so as to surround the electrode surface at the memory cell position, and selectively ejects an insulating material to a region surrounded by the bank, whereby the electrode at the predetermined memory cell position is formed. Is covered with an insulating material. In such a configuration, due to the presence of the bank, the electrode of the selected memory cell can be coated with the insulating film with high accuracy.
[0009]
Preferably, the method further comprises a step of forming a region (higher contact energy) having a lower affinity for the insulating material than the electrode surface so as to surround the electrode surface at the predetermined memory cell position. The surface of the electrode at the predetermined memory cell position is covered with an insulating material by selectively discharging to a region surrounded by the region exhibiting the non-affinity. The step of forming the non-affinity region includes the step of coating the electrode surface with FAS (fluorinated alkylsilane) and the irradiation with ultraviolet rays (UV (ultra violet) light) selectively. By removing, it can be realized by a step of forming a region surrounded by the region showing incompatibility. In such a configuration, the electrode of the selected memory cell can be coated with the insulating film with high accuracy due to the presence of the non-affinity region.
[0010]
Further, the method for manufacturing a memory device according to the present invention is a method for manufacturing a memory device that stores a state based on a resistance value of a semiconductor layer, wherein the resistance value of the semiconductor layer is relative to the semiconductor layer corresponding to the memory cell position. A doping material is injected using an inkjet head so as to be included in any of a predetermined range corresponding to a state of n value (n = 2 or n> 2). Accordingly, the stored contents can be easily changed by changing the setting of the ink jet (changing the discharge amount of the doping material or the like). Furthermore, since a multi-valued memory state can be formed by the difference in resistance value of the semiconductor layer, various and large-capacity memory devices can be manufactured.
[0011]
Preferably, a bank is formed so as to surround the electrode surface at the memory cell position, and a semiconductor layer is formed at the memory cell position by discharging a semiconductor material to an area surrounded by the bank using an inkjet head. And a step of performing. In such a configuration, the resistance value of the electrode of the selected memory cell can be accurately set due to the presence of the bank.
[0012]
The memory device manufacturing method according to the present invention is a memory device manufacturing method for storing a state based on a resistance value of a semiconductor layer, and includes a step of forming a bank so as to surround an electrode surface at a memory cell position. According to the state to be memorized from n types of semiconductor materials adjusted so that the resistance value is included in a predetermined range corresponding to the n value state (n = 2 or n> 2). A resistance value of the semiconductor layer of each memory cell is determined by selecting a predetermined semiconductor material and selectively discharging the selected semiconductor material to an area surrounded by the bank using an inkjet head. Accordingly, the memory content of each memory cell can be easily set by selecting the semiconductor material to be ejected by ink jet according to the memory state to be written. In addition, a multi-value memory state can be formed by the difference in resistance value of the semiconductor material, and various and large-capacity memory devices can be manufactured. Further, due to the presence of the bank, the semiconductor material can be accurately discharged to the selected memory cell.
[0013]
The method for manufacturing a memory device according to the present invention can be a memory device having a simple matrix structure in which memory cells are formed at intersections of upper and lower linear electrodes.
[0014]
The memory device according to the present invention is a memory device that stores a state based on the presence or absence of a coating insulating film with respect to an electrode at a memory cell position, and the coating insulating film selectively discharges an insulating material using an inkjet head. It is formed by. Accordingly, it is possible to realize a memory device that can easily change the stored contents by changing the setting of the inkjet.
[0015]
Preferably, a bank is formed so as to surround the electrode surface at the memory cell position, and the covering insulating film is formed in a region surrounded by the bank. In such a configuration, since the electrodes of each memory cell are isolated from the banks of other memory cells by the bank, a stable memory state can be realized.
[0016]
Preferably, the coating insulating film is formed by selectively discharging the insulating material to a region surrounded by a region having a less affinity for the insulating material than the electrode material by using an inkjet head. It is formed. In such a configuration, since the electrodes of each memory cell are isolated from the electrodes of other memory cells by the non-affinity region, a stable memory state can be realized.
[0017]
A memory device according to the present invention is a memory device that stores a state according to a resistance value of a semiconductor layer, and the resistance value of the semiconductor layer corresponding to the memory cell position is obtained by injecting a doping material using an inkjet head, It is formed so as to be included in any of a predetermined range set in advance corresponding to an n-value state (n = 2 or n> 2). Accordingly, it is possible to realize a memory device that can easily change the stored contents by changing the setting of the ink jet (a discharge amount of the doping material). In addition, since a multi-value memory state can be formed by the difference in resistance value of the semiconductor material, various and large-capacity memory devices can be realized.
[0018]
Preferably, a bank formed so as to surround the electrode surface at the memory cell position is provided, and the semiconductor layer corresponding to the memory cell position discharges a semiconductor material to an area surrounded by the bank using an inkjet head. Is formed. In such a configuration, since the electrodes of each memory cell are isolated from the banks of other memory cells by the bank, a stable memory state can be realized.
[0019]
A memory device according to the present invention is a memory device that stores a state according to a resistance value of a semiconductor layer, and includes a bank formed so as to surround an electrode surface at a memory cell position, and the semiconductor layer corresponding to the memory cell position Is any one of the n types of semiconductor materials adjusted so that the resistance value is included in a predetermined range corresponding to the n-value state (n = 2 or n> 2), It is formed by selectively ejecting an area surrounded by the bank using an inkjet head. Accordingly, the memory content of each memory cell can be easily set by selecting the semiconductor material to be ejected by ink jet according to the memory state to be written. In addition, a multi-value memory state can be formed due to the difference in resistance value of the semiconductor material, and various and large-capacity memory devices can be realized. Further, since the electrodes of each memory cell are separated from the electrodes of other memory cells by the bank, a stable storage state can be realized.
[0020]
The memory device according to the present invention can be a memory device having a simple matrix structure.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of a memory device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.
(Configuration and operating principle of inkjet head)
First, the configuration and operating principle of an ink jet head apparatus used when manufacturing a memory device according to the present invention will be described.
[0022]
The exploded perspective view of the inkjet head 9 shown in FIG. 1 is a type in which an ink supply channel is formed in a pressurizing chamber substrate. As shown in the figure, the ink jet head 9 is mainly composed of a pressurizing chamber substrate 1, a nozzle plate 5 and a base 3.
[0023]
The pressurizing chamber substrate 1 is formed on a silicon single crystal substrate and then separated into each. The pressurizing chamber substrate 1 is provided with a plurality of strip-shaped pressurizing chambers 106 and includes a common flow path 110 for supplying ink to all the pressurizing chambers 106. The pressurizing chambers 106 are separated by side walls 107. The pressurizing chambers 106 are arranged in two rows, and 128 are formed per row, thereby realizing an ink jet head having a print density of 256 nozzles. A diaphragm film and a piezoelectric thin film element are formed on the substrate 3 side of the pressurizing chamber substrate 1. Further, the wiring from each piezoelectric thin film element is converged on the wiring substrate 4 which is a flexible cable, and is connected to an external circuit (not shown) of the base 3. A discharge timing for discharging a predetermined material to the semiconductor ROM is instructed to the external circuit, and the material is discharged.
[0024]
The nozzle plate 5 is joined to the pressurizing chamber substrate 1. A nozzle 51 for extracting an ink droplet is formed at a position corresponding to the pressurizing chamber 106 in the nozzle plate 5. The nozzle 51 can have a diameter of 28 μm, for example. In this case, the amount of material discharged at one time is about 10 pl to 20 pl. The nozzles 51 are formed in two rows at a predetermined arrangement pitch. For example, the interval between the rows and the arrangement pitch can be set to 141 μm and 75 μm, respectively.
[0025]
The base 3 is a steel body such as plastic or metal and serves as a mounting base for the pressurizing chamber substrate 1.
[0026]
In addition, as a structure of an inkjet head, the system using a piezoelectric element or the system discharged by the generation | occurrence | production of the bubble by heat may be sufficient.
[0027]
FIG. 2 is an explanatory diagram of the operation principle of the inkjet head 9. This figure shows the electrical connection relationship with the main part of the ink jet head 9. One electrode of the drive voltage source 301 is connected to the lower electrode 303 of the inkjet head via the wiring 302. The other electrode of the drive voltage source 301 is connected to the upper electrode 307 corresponding to each pressurizing chamber 106a to 106c via the wiring 304 and the switches 306a to 306c.
[0028]
In this figure, only the switch 306b of the pressurizing chamber 106b is closed, and the other switches 306a and 306c are opened. The pressurizing chambers 106a and 106c in which the switches 306a and 306c are opened indicate a standby state for ink ejection. At the time of discharging the material, for example, the switch is closed like the switch 306b, and a voltage is applied to the piezoelectric film 309. This voltage is applied in the same polarity as the polarization direction of the piezoelectric film 309 indicated by the arrow A, in other words, the same voltage as the polarity of the applied voltage during polarization. The piezoelectric film 309 expands in the thickness direction and contracts in the direction perpendicular to the thickness direction. Due to this contraction, a stress acts on the interface between the piezoelectric film 309 and the vibration plate 310, and the piezoelectric film 309 and the vibration plate 310 bend downward. This deflection reduces the volume of the pressurizing chamber 106b, and the material droplet 23 is discharged from 51b. The material droplet 23 covers the electrode corresponding to the memory cell. Thereafter, when the switch 306b is opened again, the bent piezoelectric film 309 and the vibration plate 310 are restored, and the volume of the pressurizing chamber 106b expands, so that the material is supplied from the ink supply path (not shown) to the pressurizing chamber 106b. Filled. The vibration frequency of the piezoelectric film 309 is 7.2 kHz.
[0029]
In the method of discharging by the generation of bubbles, a heating element is provided in the pressure chamber that communicates with the nozzle.The heating element generates heat, the fluid near the nozzle is boiled to generate bubbles, and the fluid is generated by volume expansion. Discharge. The method using a piezoelectric element is preferable in that there is no change in the quality of the fluid due to heating.
[0030]
FIG. 3 is a schematic diagram showing the overall configuration of the inkjet head device. In FIG. 3, the apparatus includes inkjet heads 21 to 2n (n is an arbitrary natural number), tanks 31 to 3n, a drive mechanism 7 and a control circuit 8. In this ink jet head device, a predetermined insulating film or the like is formed by attaching a droplet 1x (x is any one of 1 to n, the same applies hereinafter) such as an insulating material to the electrode surface at the memory cell position.
[0031]
The inkjet heads 21 to 2n have the same structure. Each head ejects a fluid containing an insulating material or the like by a method using a piezoelectric element.
[0032]
The tanks 31 to 3n supply fluids 11 to 1n including an insulating material for forming an insulating film to the ink jet heads 21 to 2n.
[0033]
The drive mechanism 7 includes motors 41 and 42 and a mechanical structure (not shown). The motor 41 conveys the ink jet recording head 2x in the X-axis direction (lateral direction in FIG. 3) according to the drive signal Sx, and the motor 42 moves the ink jet recording head 2x in the Y axis direction (FIG. 3) according to the drive signal Sy. In the depth direction). Note that the drive mechanism is not limited to this configuration, and may be any mechanism that can relatively change the position of the inkjet head 2x. Accordingly, a drive mechanism that moves the substrate relative to the inkjet head 2x can also be employed.
[0034]
The control circuit 8 is a computer device, for example, and includes a CPU, a memory, an interface, and the like (not shown). The control circuit 8 can cause the apparatus to manufacture the memory device according to the present invention by executing a predetermined program.
[0035]
When the liquid droplet 1x is discharged, the discharge signals Sh1 to Shn are supplied to any one of the ink jet heads 21 to 2n, and when the head is moved, the drive signals Sx and Sy are supplied to the motors 41 and 42.
[0036]
In addition, when a certain atmosphere process is required when discharging the droplet 1x from the inkjet head 2X, a solidifying device 6 may be further provided. In order to promote the crystallization of the insulating layer, the solidifying device 6 applies a physical, physicochemical, or chemical treatment to the control signal Sp supplied from the control circuit 8 on the surface serving as the base of the droplet 1x. Apply. For example, hot air spraying, laser irradiation, heating / drying processing by lamp irradiation, chemical change processing by chemical substance administration, and certain surface improvement processing for controlling the degree of adhesion of the droplet 1x to the underlying surface can be considered. .
[0037]
When the memory device according to the present invention is manufactured, an insulating material or the like can be selectively discharged to a predetermined memory cell according to the recording pattern stored in the apparatus by using the inkjet head device.
(Embodiment 1)
Embodiment 1 of the present invention relates to a memory device manufacturing technique in which an insulating material is selectively ejected using an ink jet head so that an electrode surface at a predetermined memory cell position is covered with the insulating material.
(First embodiment)
FIG. 4 shows a cross-sectional view of the manufacturing process of the first example of the present embodiment. This embodiment includes a step of forming a bank so as to surround the electrode surface at the memory cell position.
[0038]
Lower electrode formation step (FIG. 4A): A lower electrode layer is formed on the substrate 200. As a material of the substrate 200, for example, heat-resistant glass such as Si wafer, quartz glass, soda glass, Corning 7059, NEC Electric Glass OA-2, or the like can be considered. The lower electrode layer can be obtained by depositing platinum by a direct current sputtering method, an electron beam evaporation method, or the like. As a suitable electrode other than platinum, a noble metal electrode such as palladium, IrO 2 , RuO 2 , ReO 3 There are conductive compounds such as
[0039]
After the formation of the lower electrode layer, a resist (not shown) is applied, patterning is performed linearly, and dry etching is performed using this as a mask. By this process, a plurality of linear lower electrodes 201 are formed. In the figure, it is linear in the direction from the front to the back.
[0040]
Bank formation step (FIG. 4B): A bank 202 is formed on the lower electrode 201. The bank 202 is a member that functions as a partition member, and as the material thereof, for example, an insulating material such as polyimide or SiO 2 can be used. The bank 202 can be formed by selecting a lithography method, a printing method, or an arbitrary method. When the lithography method is used, an insulating material is applied in accordance with the height of the bank by a predetermined method such as spin coating, spray coating, roll coating, die coating, dip coating, and a resist layer is applied thereon. Then, a resist matching the shape of the bank is left. Finally, the material of the bank other than the mask is removed by etching. When using the printing method, the insulating material is directly applied to the bank shape by any method such as intaglio, planographic, and relief. The height of the bank 202 is set such that the insulating material does not overflow into the adjacent recess 203 due to surface tension even if the recess 203 surrounded by the bank is filled with the insulating material. For example, when the insulating film covering the electrode surface is formed with a thickness of 0.05 μm to 0.2 μm, the bank 202 is formed with a height of about 0.2 μm to 2 μm.
[0041]
FIG. 5 shows a plan view of the bank 202. The banks 202 are formed in a lattice shape in two directions, the Y direction (the same direction as the lower electrode 201) and the X direction. A region 203 surrounded by the bank 202 (corresponding to the recess 203 in FIG. 4B) corresponds to the memory cell position. That is, the bank 202 is formed so as to surround the surface of the lower electrode 201 at the memory cell position. FIG. 4B corresponds to a cross-sectional view taken along the line aa ′ in FIG.
[0042]
Inkjet ejection process (FIGS. 4C and 4D): SiO is selectively selected from the inkjet head 205 according to the recording pattern. 2 The insulating film 206 is formed by discharging an insulating material such as the like and filling the recess 203 surrounded by the bank 202 with the insulating material 204. The insulating material 204 is discharged from the inkjet head 205 to the recess 13 surrounded by the bank 12 (FIG. 4C). The discharge amount is set so that the desired thickness is obtained when the volume is reduced by the heat treatment. When the insulating material is filled, heat treatment is performed to evaporate the solvent component. As the solvent component evaporates, the volume of the insulating material 204 is reduced and the insulating film 206 is formed (FIG. 4D). The amount of the insulating material 204 to be discharged is adjusted so that the thickness of the insulating film 206 after the formation becomes, for example, about 0.1 μm to 2 μm.
[0043]
Semiconductor layer deposition step (FIG. 4E): A semiconductor layer 207 is deposited on the lower electrode 201, the bank 202, and the insulating film 206. As the semiconductor layer 207, a conventional semiconductor material can be used, and any composition can be applied.
[0044]
When forming a film by the sol-gel method, a hydrated complex of a metal component hydroxide capable of forming a semiconductor layer, that is, a semiconductor film precursor by applying, drying and degreasing the sol on the lower electrode 201 or the like The precursor is crystallized by RTA treatment to obtain a semiconductor thin film. Then, a desired number of coating / drying / degreasing processes are repeated until the final film thickness becomes 0.3 μm.
[0045]
Further, the semiconductor layer can be formed not only by the sol-gel method but also by high-frequency sputtering, MOD method (Metal Organic Decomposition Process), printing method, or the like. The printing method is a technique for obtaining a semiconductor layer by forming a film on a desired substrate using a paste or slurry containing electrostrictive ceramic particles as a main component and performing heat treatment. By using this printing method, it is easy to apply a lithography technique, a machining technique such as laser processing or slicing, and the shape of the semiconductor layer can be arbitrarily designed. In addition, since the degree of freedom in design is improved, the integration density of capacitors as memory devices can be improved.
[0046]
Upper electrode formation step (FIG. 4 (f)): The upper electrode layer is obtained by depositing platinum by a direct current sputtering method, an electron beam evaporation method or the like. In addition to platinum, other suitable electrodes include Al, Cu, Ca, Mg, Li, noble metal electrodes such as palladium, and IrO. 2 , RuO 2 , ReO 3 There are conductive compounds such as
[0047]
After the formation of the upper electrode layer, a resist (not shown) is applied, patterning is performed linearly in a direction (X direction) orthogonal to the lower electrode 201, and dry etching or the like is performed using this as a mask. With this process, a plurality of upper electrodes 208 are formed in a direction orthogonal to the lower electrode 201.
[0048]
The upper electrode 208 can be formed into a pattern by an ink jet method using a conductive polymer. In this way, the upper electrode pattern can be formed arbitrarily and appropriately as in the case of the insulating layer and the like.
[0049]
The memory device of the present invention manufactured by such a manufacturing process has a simple matrix structure in which memory cells are formed at the intersections of the upper and lower linear electrodes. Since the coating insulating film that determines the memory response of the memory cell is ejected and formed by the inkjet head, it is not necessary to use an expensive photomask, and the memory device can be manufactured and realized at low cost.
[0050]
Further, by controlling the operation of the ink jet head, the memory cell for forming the coating insulating film can be changed, so that the recording pattern of the memory device can be easily changed. As a result, memory devices having various recording patterns can be manufactured and realized.
[0051]
Furthermore, when an inkjet head is used, the coating insulating film can be formed with a small device such as that used in a home printer, so that it is difficult to provide a large device (for example, a normal office or counter). Etc.), the memory device can be manufactured on the spot. For example, in a credit card, debit card, prepaid card or the like, a form in which fixed information or the like is written to each customer by using an inkjet head with a counter such as a bank is also conceivable.
[0052]
In addition, when the insulating material is ejected by the ink jet head, each memory cell is separated from other memory cells by the bank, so that the insulating material can be ejected more selectively to the memory cell, and the recording accuracy Can be improved.
(Second embodiment)
FIG. 6 shows a cross-sectional view of the manufacturing process of the second example of the present embodiment. As in the first embodiment, the present embodiment includes a lower electrode forming step, an inkjet discharge step, a semiconductor layer forming step, and an upper electrode forming step. In addition, a step (surface treatment step) is provided for forming a region showing incompatibility with the insulating material so as to surround the electrode surface at the memory cell position.
[0053]
Since the lower electrode forming step (FIG. 6A), the semiconductor layer forming step (FIG. 6E), and the upper electrode forming step (FIG. 6F) are the same as those in the first embodiment, the description is omitted. Is omitted. The surface treatment process (FIG. 4B) is performed after the lower electrode formation process and before the inkjet discharge process.
[0054]
Surface treatment step (FIG. 6B): A non-affinity region (FAS region) 400 is formed on the lower electrode 201. Specifically, the following FAS coating process and selective FAS removal process are provided. In FIG. 7, the shaded area is an area coated with FAS.
[0055]
FAS coating process (FIG. 7A): FAS (fluorinated alkylsilane) is deposited on the surface of the lower electrode 201 by a CVD method or the like. FAS has water repellency and has the property of being easily bonded to OH groups. Usually, the surface of the lower electrode 201 is in an oxidized state and has an OH group, so that the FAS is bonded to the OH group on the surface of the lower electrode 201 by placing the lower electrode 201 in FAS vapor. As a result, a monomolecular film having a thickness of 10 to 17 mm by FAS is formed on the surface of the lower electrode 201, and the surface of the lower electrode 201 becomes water repellent. FIG. 8 shows the molecular structure of FAS in the bound state. Note that the substrate portion on which the lower electrode 201 is not formed is also coated with FAS.
[0056]
Selective FAS removal step (FIG. 7B): The surface of the lower electrode 201 coated with FAS is selectively irradiated with ultraviolet rays (UV) to remove FAS. Here, the region irradiated with ultraviolet rays is a region corresponding to a memory cell to which an insulating material is discharged in a subsequent inkjet discharge process. In the region 401 where the FAS is removed by irradiation with ultraviolet rays, the surface of the lower electrode 201 having an OH group is exposed, so that the hydrophilicity is recovered and has an affinity for the insulating material. FIG. 6B corresponds to a cross-sectional view taken along line aa ′ in FIG.
[0057]
Inkjet ejection process (FIGS. 6C and 6D): Selectively SiO2 according to the recording pattern from the inkjet head. 2 An insulating material such as (polysilicon) is discharged, and a covering insulating film is formed in a region 401 surrounded by the FAS region 400. The insulating material 204 is discharged from the inkjet head 205 to a region 401 surrounded by the FAS region 400. The insulating material 204 stays in the region 401 in a raised state because the FAS region 400 has non-affinity and the region 401 has affinity (FIG. 6C). The discharge amount of the insulating material 204 is set to an amount such that a desired thickness (about 0.1 μm to 2 μm) is obtained when the volume is reduced by heat treatment. After the coating insulating film 206 is formed at a necessary location, the FAS on the entire surface is removed by UV irradiation or the like (FIG. 6D).
[0058]
The memory device of the present invention manufactured by such a manufacturing process has the same effect as that of the first embodiment.
[0059]
In addition, when the insulating material is discharged by the ink jet head, a non-affinity region is formed instead of the bank in the first embodiment, and each memory cell is isolated from other memory cells by the non-affinity region. On the other hand, the insulating material can be discharged more selectively, and the recording accuracy can be improved.
(Embodiment 2)
In the second embodiment of the present invention, for a semiconductor layer corresponding to a memory cell position, the resistance value of the semiconductor layer is set in advance corresponding to an n-value storage state (n = 2 or n> 2). The present invention relates to a method for manufacturing a memory device that realizes a multivalued storage state by injecting a doping material using an inkjet head so as to be included in any of the ranges.
[0060]
FIG. 9 shows a cross-sectional view of the manufacturing process of the present embodiment. As in the first embodiment, the present embodiment includes a lower electrode forming process, a semiconductor layer forming process, an inkjet discharge process, and an upper electrode forming process. However, the present embodiment is different from the first embodiment in that the semiconductor layer film forming step is performed after the lower electrode forming step, and the ink jet discharging step is subsequently performed.
[0061]
In the present embodiment, a step of forming a bank so as to surround the electrode surface at the memory cell position, or a step of forming a region showing non-affinity with the insulating material so as to surround the electrode surface at the memory cell position (surface (Processing step) may be provided. When the bank forming step is provided, it can be realized in the same manner as the first example of the first embodiment, and when the surface forming step is provided, it can be realized in the same manner as the second example of the first embodiment.
[0062]
Since the lower electrode forming step (FIG. 9A), the semiconductor layer forming step (FIG. 9B), and the upper electrode forming step (FIG. 9E) are the same as those in the first embodiment, the description is omitted. Is omitted.
[0063]
Inkjet ejection process (FIGS. 9C and 9D): The doping material 500 is selectively ejected from the inkjet head according to the recording pattern, and the doping material is injected into the semiconductor layer at the memory cell position corresponding to the recording pattern. As the doping material, boron (B) or the like is possible when the semiconductor layer is P-type, and phosphorus (P), arsenic (As), antimony (Sb), or the like is conceivable when the semiconductor layer is N-type.
[0064]
Since the conductivity (resistance value) of the semiconductor layer varies depending on the amount (concentration) of the doping material contained, the conductivity of the semiconductor layer can be controlled for each memory cell by controlling the amount and concentration of the doping material to be injected. Can be different.
[0065]
Therefore, the conductivity range is divided into n sections (n = 2 or n> 2), and different storage states are associated with each. Then, the amount or concentration of the doping material injected into the semiconductor layer at each memory cell position is adjusted so that the conductivity of the semiconductor layer is included in the section corresponding to the storage state to be recorded for each memory cell. In this way, each memory cell can record an n-value storage state.
[0066]
Here, theoretically, it is possible to realize any number of memory devices by finely dividing the conductivity. However, in reality, it is desirable to set the degree of classification reasonably from the viewpoint of the stability of the read operation. As a method of such a reasonable division, it is conceivable that the conductivity having the same order is set as one division, and different storage states are associated with this.
[0067]
For example, the order of conductivity of a semiconductor layer in which the doping material is almost zero is 10 6 Assuming that the order of conductivity is 10 by injecting the doping material. 5 10 4 10 3 10 2 10 1 It can be. In this case, the order of conductivity is 10 6 10 5 10 4 10 3 10 2 10 1 By associating six recording states with each other, six states can be recorded per memory cell. In this example, six values are used, but what value is used can be determined according to the design.
[0068]
The memory device of the present invention manufactured by such a manufacturing process has a simple matrix structure in which memory cells are formed at the intersections of the upper and lower linear electrodes. Since the conductivity of the semiconductor layer that determines the memory response of the memory cell can be determined by discharging a doping material from the inkjet head, it is not necessary to use an expensive photomask, and the memory device can be manufactured and realized at low cost. it can.
[0069]
In addition, by controlling the operation of the ink jet head, that is, the amount and concentration of the doping material to be ejected, it is possible to easily change the recording pattern and realize a multi-value storage state for each memory cell. As a result, various and large-capacity memory devices can be manufactured and realized.
[0070]
Further, when an inkjet head is used, the doping material can be discharged by a small device used in a home printer, so that it is difficult to provide a large device (for example, a normal office or a counter) ), The memory device can be manufactured on the spot. For example, in a credit card, debit card, prepaid card or the like, a form in which fixed information or the like is written to each customer by using an inkjet head with a counter such as a bank is also conceivable.
(Embodiment 3)
Embodiment 3 of the present invention is based on n types of semiconductor materials adjusted so that the resistance value is included in a predetermined range corresponding to an n-value state (n = 2 or n> 2). A semiconductor layer of each memory cell is selected by selecting a predetermined semiconductor material according to a state to be stored and selectively discharging the selected semiconductor material to a region surrounded by the bank using an inkjet head. The resistance value of the memory device is determined.
[0071]
FIG. 10 shows a cross-sectional view of the manufacturing process of this embodiment. The present embodiment includes a lower electrode forming process, a bank forming process, an inkjet discharge process, and an upper electrode forming process.
[0072]
Instead of the bank formation step, a step (surface treatment step) for forming a region showing non-affinity with the insulating material so as to surround the electrode surface at the memory cell position may be provided. When the surface treatment step is provided, it can be realized in the same manner as the second example of the first embodiment.
[0073]
The lower electrode formation step (FIG. 10A), bank formation step (FIG. 10B), and upper electrode formation step (FIG. 10E) are the same as in the first example of the first embodiment. The description is omitted.
[0074]
Inkjet ejection process (FIGS. 10C and 10D): A memory cell position is selected according to a recording pattern, a semiconductor material 600 is selected based on a state to be recorded in the selected memory cell, and the selected semiconductor material is selected. A semiconductor layer 601 is formed by discharging from an inkjet head to the recess 203 surrounded by the bank 202 at the selected memory cell position.
[0075]
Here, the semiconductor material is selected from a plurality of semiconductor materials adjusted so that the amount (concentration) of the doping material contained in advance is different. In such a plurality of semiconductor materials, the amount of the doping material is adjusted so that the order of the conductivity of the formed semiconductor layer is different.
[0076]
Therefore, by selecting a semiconductor material according to the storage state for each memory cell, the order of conductivity of the semiconductor layer formed for each memory cell can be made to correspond to the storage state. The relationship between the order of conductivity, the range of conductivity, and the storage state can be determined in the same manner as in the second embodiment, for example.
[0077]
The memory device of the present invention manufactured by such a manufacturing process has a simple matrix structure in which memory cells are formed at the intersections of the upper and lower linear electrodes. Since the conductivity of the semiconductor layer that determines the memory response of the memory cell can be determined by the type of semiconductor material ejected from the inkjet head, it is not necessary to use an expensive photomask, and the memory device can be manufactured and realized at low cost Can do.
[0078]
Further, by changing the operation of the inkjet head, that is, the selection pattern of the semiconductor material to be ejected, it is possible to easily change the recording pattern and realize a multi-value storage state for each memory cell. As a result, various and large-capacity memory devices can be manufactured and realized.
[0079]
Furthermore, when an inkjet head is used, the semiconductor material can be discharged by a small device such as that used in a home printer, so that it is difficult to provide a large device (for example, a normal office or a counter) ), The memory device can be manufactured on the spot. For example, in a credit card, debit card, prepaid card or the like, a form in which fixed information or the like is written to each customer by using an inkjet head with a counter such as a bank is also conceivable.
(Modification)
The memory device manufactured according to the present invention can be used for all information processing devices including a memory, for example, an internal storage device of a computer, a memory stick, and a memory card.
[0080]
Note that the present invention is not limited to the above-described embodiments, and can be variously modified and applied. For example, a memory having a larger capacity can be configured by forming the memory device of the present invention in a stacked structure.
[0081]
In Embodiments 1 and 2, the case where a semiconductor layer is formed by a sol-gel method or the like has been described, but the semiconductor layer is also formed by discharging a semiconductor material from an inkjet head. Also good.
[0082]
【The invention's effect】
According to the present invention, since the storage contents of the semiconductor ROM can be set by discharging an insulating material, a doping material, a semiconductor material, and the like by the ink jet head, the semiconductor ROM having various storage patterns can be made inexpensively and easily in a shorter period of time. Can be manufactured.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view of an inkjet head used in the present invention.
FIG. 2 is a diagram for explaining an operation principle of an ink jet head used in the present invention.
FIG. 3 is a diagram for explaining an overall configuration of an inkjet head device used in the present invention.
4 is a diagram showing manufacturing steps of the first example of the embodiment 1. FIG.
FIG. 5 is a diagram for explaining a bank formed in the first embodiment;
6 is a diagram showing manufacturing steps in the second example of Embodiment 1. FIG.
7 is a diagram for explaining a non-affinity region formed in Embodiment 1. FIG.
FIG. 8 is a diagram for explaining the structure of an FAS;
9 is a diagram showing manufacturing steps of Embodiment 2. FIG.
10 is a diagram showing manufacturing steps of Embodiment 4. FIG.
FIG. 11 is an equivalent circuit diagram using a diode for a conventional semiconductor ROM.
FIG. 12 is a cross-sectional view of a conventional semiconductor ROM.
[Explanation of symbols]
201 Lower electrode
202 banks
205 Inkjet head
206 Insulating film
207, 601 Semiconductor layer
208 Upper electrode
400 non-affinity region
500 Doping material
600 Semiconductor materials

Claims (12)

  1. A method of manufacturing a memory device that stores a state according to the presence or absence of a coating insulating film on an electrode surface at a memory cell position,
    Manufacturing of a memory device, wherein an insulating material is selectively ejected to an electrode surface at a predetermined memory cell position using an ink jet head, thereby covering the electrode surface at the predetermined memory cell position with the insulating material Method.
  2. Forming a bank so as to surround the electrode surface at the memory cell position;
    2. The method of manufacturing a memory device according to claim 1, wherein an insulating material is selectively ejected to a region surrounded by the bank, thereby covering the electrode at the predetermined memory cell position with the insulating material. .
  3. Forming a region having a lower affinity for the insulating material than the electrode surface so as to surround the electrode surface at the predetermined memory cell position;
    2. The electrode surface of the predetermined memory cell position is covered with an insulating material by selectively discharging an insulating material to a region surrounded by the region exhibiting non-affinity. Memory device manufacturing method.
  4. The step of forming the non-affinity region comprises
    Coating the electrode surface and surrounding area with FAS (fluoroalkylsilane);
    4. A memory device according to claim 3, further comprising the step of forming a region surrounded by the region exhibiting non-affinity by selectively performing ultraviolet irradiation to remove the FAS on the electrode surface. Manufacturing method.
  5. A method of manufacturing a memory device that stores a state according to a resistance value of a semiconductor layer,
    For the semiconductor layer corresponding to the memory cell position, the resistance value of the semiconductor layer is included in any of a predetermined range set in advance corresponding to the n-value state (n = 2 or n> 2). A method of manufacturing a memory device, wherein a doping material is injected using an inkjet head.
  6. Forming a bank so as to surround the electrode surface at the memory cell position;
    6. A method of manufacturing a memory device according to claim 5, further comprising: forming a semiconductor layer at a memory cell position by discharging a semiconductor material to a region surrounded by the bank using an ink jet head. .
  7. A method of manufacturing a memory device that stores a state according to a resistance value of a semiconductor layer,
    Forming a bank so as to surround the electrode surface at the memory cell position;
    According to the state to be memorized from n types of semiconductor materials adjusted so that the resistance value is included in a predetermined range corresponding to the n value state (n = 2 or n> 2). Determining a resistance value of a semiconductor layer of each memory cell by selecting a predetermined semiconductor material and selectively discharging the selected semiconductor material to an area surrounded by the bank using an inkjet head; A method for manufacturing a memory device.
  8.   8. The method of manufacturing a memory device according to claim 1, wherein the memory device is a memory device having a simple matrix structure in which memory cells are formed at intersections of upper and lower linear electrodes. 9. .
  9. A memory device that stores a state according to a resistance value of a semiconductor layer,
    The resistance value of the semiconductor layer corresponding to the memory cell position is set in a predetermined range corresponding to an n-value state (n = 2 or n> 2) by injecting a doping material using an inkjet head. A memory device characterized by being included in any of the above.
  10. A bank formed so as to surround the electrode surface of the memory cell position;
    10. The memory device according to claim 9 , wherein the semiconductor layer corresponding to the memory cell position is formed by ejecting a semiconductor material to an area surrounded by the bank using an inkjet head.
  11. A memory device that stores a state according to a resistance value of a semiconductor layer, comprising a bank formed so as to surround an electrode surface at a memory cell position,
    The semiconductor layer corresponding to the memory cell position has n types adjusted so that the resistance value is included in a predetermined range corresponding to an n-value state (n = 2 or n> 2). A memory device, wherein any one of semiconductor materials is selectively ejected to a region surrounded by the bank using an ink jet head.
  12. 12. The memory device according to claim 9 , wherein the memory device is a memory device having a simple matrix structure.
JP2000082165A 2000-03-23 2000-03-23 Memory device and manufacturing method thereof Expired - Fee Related JP4010091B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000082165A JP4010091B2 (en) 2000-03-23 2000-03-23 Memory device and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000082165A JP4010091B2 (en) 2000-03-23 2000-03-23 Memory device and manufacturing method thereof
US09/814,794 US6864123B2 (en) 2000-03-23 2001-03-23 Memory device and manufacturing method therefor

Publications (2)

Publication Number Publication Date
JP2001274344A JP2001274344A (en) 2001-10-05
JP4010091B2 true JP4010091B2 (en) 2007-11-21

Family

ID=18599002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000082165A Expired - Fee Related JP4010091B2 (en) 2000-03-23 2000-03-23 Memory device and manufacturing method thereof

Country Status (2)

Country Link
US (1) US6864123B2 (en)
JP (1) JP4010091B2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW490997B (en) * 2000-03-31 2002-06-11 Seiko Epson Corp Method of manufacturing organic EL element, and organic EL element
FI116422B (en) * 2002-07-30 2005-11-15 Hidex Oy More Process Instruments
DE10308323B4 (en) * 2003-02-26 2007-10-11 Infineon Technologies Ag Semiconductor chip arrangement with ROM
JP2005072319A (en) 2003-08-26 2005-03-17 Mitsubishi Electric Corp Method and device for evaluating and preparing microwave integrated circuit
JP4158755B2 (en) 2004-09-30 2008-10-01 セイコーエプソン株式会社 Method for producing functional film, method for producing thin film transistor
US7675123B2 (en) * 2004-10-29 2010-03-09 Agfa-Gevaert Nv Printable non-volatile passive memory element and method of making thereof
US20060098485A1 (en) * 2004-10-29 2006-05-11 Agfa-Gevaert Printable non-volatile passive memory element and method of making thereof
KR20070083852A (en) * 2004-10-29 2007-08-24 아그파-게바에르트 Printable organic non-volatile passive memory element and method of making thereof
US20070057311A1 (en) * 2004-10-29 2007-03-15 Agfa-Gevaert Conventionally printable non-volatile passive memory element and method of making thereof
WO2006085634A1 (en) * 2005-02-10 2006-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
CN100546034C (en) 2005-02-10 2009-09-30 株式会社半导体能源研究所 Semiconductor device and manufacture method thereof
JP4884791B2 (en) * 2005-02-10 2012-02-29 株式会社半導体エネルギー研究所 Memory element and manufacturing method thereof
US7462513B2 (en) * 2005-08-22 2008-12-09 Lexmark International, Inc. Methods for making printed fuse devices
US20070138462A1 (en) * 2005-12-21 2007-06-21 Palo Alto Research Center Incorporated Electronic device with unique encoding
US20090116275A1 (en) * 2006-04-28 2009-05-07 Leenders Luc Conventionally printable non-volatile passive memory element and method of making thereof
GB2543528B (en) * 2015-10-20 2020-01-15 Advanced Risc Mach Ltd Memory circuit
CN107818069A (en) * 2016-09-12 2018-03-20 阿里巴巴集团控股有限公司 Data processing method and system

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2022918C3 (en) * 1970-05-11 1979-02-22 Siemens Ag, 1000 Berlin Und 8000 Muenchen
US4233671A (en) * 1979-01-05 1980-11-11 Stanford University Read only memory and integrated circuit and method of programming by laser means
US4419741A (en) * 1980-01-28 1983-12-06 Rca Corporation Read only memory (ROM) having high density memory array with on pitch decoder circuitry
US4646266A (en) * 1984-09-28 1987-02-24 Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
US5266222A (en) * 1990-05-23 1993-11-30 California Institute Of Technology Durable low surface-energy surfaces
GB9113795D0 (en) * 1991-06-26 1991-08-14 Philips Electronic Associated Thin-film rom devices and their manufacture
US5389497A (en) * 1992-06-03 1995-02-14 Nippon Paint Co., Ltd. Method for forming patterned solder mask
US5441907A (en) * 1994-06-27 1995-08-15 Taiwan Semiconductor Manufacturing Company Process for manufacturing a plug-diode mask ROM
TW312851B (en) * 1997-02-03 1997-08-11 United Microelectronics Corp Manufacturing method of read only memory by silicon on insulator process
NO973993L (en) * 1997-09-01 1999-03-02 Opticom As Read only memory and read-only memory devices
AT434259T (en) * 1997-10-14 2009-07-15 Patterning Technologies Ltd Method for the production of an electric condenser

Also Published As

Publication number Publication date
US20010039124A1 (en) 2001-11-08
US6864123B2 (en) 2005-03-08
JP2001274344A (en) 2001-10-05

Similar Documents

Publication Publication Date Title
EP0210848B1 (en) Thermal ink jet printhead
KR100425328B1 (en) Ink jet print head and manufacturing method thereof
US7275308B2 (en) Method for manufacturing a monolithic ink-jet printhead
TWI407828B (en) Method of manufacturing a display device
US6715871B2 (en) Method of forming film pattern, device for forming film pattern, conductive film wiring, electro-optical device, electronic device, and non-contact card medium
CN101121319B (en) Printhead
JP6068982B2 (en) Layer deposition methods and equipment
US6921148B2 (en) Liquid drop discharge head, discharge method and discharge device; electro optical device, method of manufacture thereof, and device for manufacture thereof; color filter, method of manufacture thereof, and device for manufacture thereof; and device incorporating backing, method of manufacture thereof, and device for manufacture thereof
US5691752A (en) Perovskite thin-film ink jet transducer
EP0629502B1 (en) Inkjet recording apparatus
JP4325343B2 (en) Film forming method and device manufacturing method
KR100595081B1 (en) Single-side fabrication process for forming inkjet monolithic printing element array on a substrate
US6727536B2 (en) Ferroelectric memory device
US7479297B2 (en) Method of manufacturing a multi-layered wiring board
US20130106930A1 (en) Printhead assembly including memory elements
US6984843B2 (en) Board for electronic device, electronic device, ferroelectric memory, electronic apparatus, ink-jet recording head, and ink-jet printer
JP3362733B2 (en) Ink jet recording device
EP1216837B1 (en) Method for manufacturing ink-jet printhead having hemispherical ink chamber
JP3956134B2 (en) Piezoelectric element manufacturing method and liquid discharge head manufacturing method
KR100818032B1 (en) Fluid-jet printhead and method of fabricating a fluid-jet printhead
DE60316857T2 (en) Manufacturing method of a piezoelectric device and a liquid jet head
KR100397604B1 (en) Bubble-jet type ink-jet printhead and manufacturing method thereof
US7351649B2 (en) Recording head unit and method of producing the same
EP1630882B1 (en) Nanometric structure and corresponding manufacturing method
US7992971B2 (en) Liquid delivering apparatus and method of producing the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040527

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050221

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070621

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070724

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070814

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070827

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100914

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100914

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110914

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120914

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130914

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees