JP3971196B2 - Semiconductor nonvolatile memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit configuration for writing, erasing and reading data in a nonvolatile memory in a semiconductor nonvolatile memory device including a nonvolatile memory and a transistor.
[0002]
[Prior art]
[Description of background art]
In recent years, a demand for a nonvolatile memory represented by a flash memory (floating gate type electrically erasable programmable read only memory (EEPROM)) has increased due to the development and explosive penetration of portable devices.
An important problem of this nonvolatile memory is an increase in capacity. There are two methods for increasing the capacity: a method in which elements are made smaller and highly integrated, and a method in which data is held in several different storage states in one element. Further, when a semiconductor nonvolatile memory device is mounted on a portable device, further reduction in power consumption is an issue.
[0003]
Most portable devices are powered by batteries. Therefore, it is important to operate the apparatus while consuming as little power as possible from the battery.
At present, development is actively carried out, including the extension of battery life and the reduction of power consumption of semiconductor integrated circuit devices (ICs) to be mounted. Nonvolatile memories are also frequently accessed for data writing, erasing, and reading, and consume power.
[0004]
What is important in writing, erasing, and reading data in the nonvolatile memory is how to perform these writing, erasing, and reading operations with low power consumption. In writing and erasing, when writing or erasing is not performed normally, it is necessary to rewrite or erasing, and this rewriting or erasing consumes power wastefully. It is.
In reading, it is important to extract data while consuming as little power as possible.
[0005]
For this reason, it is necessary to supply the nonvolatile memory with a necessary and sufficient voltage at the time of writing and erasing so that rewriting and erasing are not performed. In reading, it is necessary to reduce power consumption as much as possible.
[0006]
The semiconductor nonvolatile memory device according to the present invention has been made paying attention to this problem. A conventional semiconductor nonvolatile memory device will be described below.
[0007]
[Description of Structure and Operation of Conventional Semiconductor Nonvolatile Memory Device: FIG. 2]
First, the structure of a conventional semiconductor nonvolatile memory device will be described with reference to the circuit diagram of FIG.
The semiconductor nonvolatile device includes a nonvolatile memory 18 for storing data, and a transistor 74 for selecting the nonvolatile memory 18. Between the source terminal 74S that is the ground potential of the transistor 74 and the drain terminal 18D for applying the program voltage of the nonvolatile memory 18, the bit selection transistor 74 and the nonvolatile memory 18 that stores data are arranged. . The transistor 74 and the nonvolatile memory 18 are connected in series, and a connection point between the transistor 74 and the nonvolatile memory 18 is used as the output terminal 6.
[0008]
A selection signal is input to the gate terminal 74G of the transistor 74. By inputting a selection signal to the gate terminal 74G of the transistor 74, the transistor 74 is turned on or off, and a voltage necessary for writing, erasing, and reading to the nonvolatile memory 18 can be controlled. It becomes.
A selection signal is also input to the gate terminal 18G of the nonvolatile memory 18. By inputting a selection signal to the gate terminal 18G of the nonvolatile memory 18, the nonvolatile memory 18 becomes conductive or non-conductive, and writing, erasing, and reading can be performed.
As described above, in the conventional semiconductor nonvolatile memory device, one bit selection transistor 74 performs writing, erasing, and reading operations.
[0009]
Next, the operation of the conventional semiconductor nonvolatile memory device shown in FIG. 2 will be described. First, the write operation will be described.
A selection signal is input to the gate terminal 74G of the transistor 74 and the gate terminal 18G of the nonvolatile memory 18, and the transistor 74 and the nonvolatile memory 18 are turned on.
When a program voltage is applied to the drain terminal 18D of the nonvolatile memory 18 in this conductive state, the source terminal 74S of the transistor 74 is at the ground potential, so that the drain terminal 18D of the nonvolatile memory 18 is connected to the source terminal 74S of the transistor 74. A current flows toward it. At this time, charges are accumulated in the nonvolatile memory 18 by the voltage applied to the gate terminal 18G of the nonvolatile memory 18, and a writing state is established. Here, if the program voltage applied to the drain terminal 18D of the nonvolatile memory 18 is a positive voltage, the accumulated charge is an electron, and if the program voltage applied to the drain terminal 18D of the nonvolatile memory 18 is a negative voltage, the charge is accumulated. The charge to be done is a hole.
[0010]
Here, the selection signal will be described. When the transistor 74 is an N-type MOS transistor and the nonvolatile memory 18 is an N-type nonvolatile memory, the selection signal at the time of writing is a program voltage. The selection signal at the time of reading is a read voltage (positive voltage).
The non-selection signal is a ground potential at the time of writing, erasing, and reading.
Here, the magnitude relationship between the program voltage and the read voltage is that the program voltage is larger than the read voltage.
[0011]
Next, the reading operation will be described. A selection signal is input to the gate terminal 74G of the transistor 74 and the gate terminal 18G of the nonvolatile memory 18, and the transistor 74 and the nonvolatile memory 18 are turned on.
When a read voltage is applied to the drain terminal 18D of the nonvolatile memory 18 in this conductive state, the source terminal 74S of the transistor 74 is at the ground potential, so that the drain terminal 18D of the nonvolatile memory 18 is connected to the source terminal 74S of the transistor 74. A current flows toward it. At this time, the storage state of the nonvolatile memory 18 can be determined by measuring the voltage of the output terminal 6.
In other words, if the nonvolatile memory 18 is in a writing state, even if a selection signal is input to the gate terminal 18G of the nonvolatile memory 18, the charge is accumulated, so that the nonvolatile memory 18 becomes non-conducting rather than conducting. Little current flows from the drain terminal 18D of the memory 18 toward the source terminal 74S of the transistor 74. Accordingly, the voltage at the output terminal 6 is about the same as the ground potential.
[0012]
If the nonvolatile memory 18 is not written, when a read voltage is applied from the drain terminal 18D of the nonvolatile memory 18, the source terminal 74S of the transistor 74 is at the ground potential. A current flows from the drain terminal 18D toward the source terminal 74S of the transistor 74.
The voltage at the output terminal 6 at this time is a value obtained by resistance-dividing the read voltage by a resistance when the transistor 74 and the non-volatile memory 18 are in a conductive state (hereinafter referred to as an on-resistance).
[0013]
Next, the erase operation will be described. A selection signal is input to the gate terminal 74G of the transistor 74, and a non-selection signal is input to the gate terminal 18G of the nonvolatile memory 18. As a result, the transistor 74 is turned on, and the nonvolatile memory 18 is turned off.
At this time, by applying an erasing voltage (a voltage equal to or slightly higher than the program voltage) to the drain terminal 18D of the non-volatile memory 18, the charge accumulated in the non-volatile memory 18 is extracted and erasing is performed.
[0014]
[Problems to be solved by the invention]
Problems of the conventional semiconductor nonvolatile memory device shown in FIG. 2 will be described with reference to the graphs of FIGS. In the graph of FIG. 3, the vertical axis represents the threshold voltage after writing in the nonvolatile memory 18, and the horizontal axis represents the on-resistance of the transistor 74 when the channel width and channel length are changed according to the pattern layout.
[0015]
As is clear from FIG. 3, when the on-resistance of the transistor 74 is small, the voltage drop in the transistor 74 is reduced, and the voltage necessary for writing is supplied to the nonvolatile memory 18 and the supplied voltage is Large current flows because it is large. For this reason, when the on-resistance of the transistor 74 is 100Ω, the threshold voltage after writing in the nonvolatile memory 18 is shifted to about 7.0V.
On the other hand, when the on-resistance of the transistor 74 is large, the voltage drop in the transistor 74 is large, the voltage necessary for writing is not supplied to the nonvolatile memory 18, and only a small current flows because the supplied voltage is small. . For this reason, when the on-resistance of the transistor 74 is 10 kΩ, the threshold voltage after writing in the nonvolatile memory 18 is shifted only to about 1.0V.
In the case of writing that requires voltage and current in this way, the size (channel width and channel length) of the transistor 74 is optimized to reduce the on-resistance, and the voltage and current required for writing to the nonvolatile memory 18. Need to be designed to supply.
[0016]
In the graph of FIG. 4, the vertical axis indicates the current value that flows through the nonvolatile memory 18 at the time of reading, and the horizontal axis indicates the on-resistance of the transistor 74 when the channel width and the channel length are changed according to the pattern layout.
[0017]
As can be seen from FIG. 4, when the on-resistance of the transistor 74 is large, the current that can be passed by the transistor 74 is limited. For this reason, when the on-resistance of the transistor 74 is 10 kΩ, the current flowing in the nonvolatile memory 18 at the time of reading is about 10 nA, and the reading operation can be performed with less power consumption.
Conversely, when the on-resistance of the transistor 74 is 100Ω, the current flowing through the nonvolatile memory 18 at the time of reading is as large as about 10 μA, and the power consumption is large. When it is desired to perform a read operation with low power consumption, it is necessary to optimize the size (channel width and channel length) of the transistor 74 and increase the on-resistance so that no current flows as much as possible. is there.
[0018]
As described with reference to FIGS. 3 and 4, if the on-resistance of the transistor 74 is reduced, the threshold voltage after writing in the nonvolatile memory 18 is greatly shifted and writing is performed, but power consumption during reading is increased. If the on-resistance of the transistor 74 is increased, the power consumption at the time of reading decreases, but the shift of the threshold voltage after writing in the nonvolatile memory 18 is small and normal writing cannot be performed.
[0019]
In this way, the characteristics required for the transistor 74 at the time of writing and reading are completely reversed. Therefore, in the conventional semiconductor nonvolatile memory device, it is impossible to achieve both of the characteristics of supplying a voltage and a current necessary for writing and reducing power consumption as much as possible during reading.
[0020]
(Object of invention)
SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the conventional semiconductor nonvolatile memory device as described above, there is no problem of rewriting the nonvolatile memory, and the semiconductor nonvolatile memory that can operate with as little power consumption as possible during reading. It is to provide a sex memory device.
[0021]
[Means for Solving the Problems]
In order to achieve the above object, the following means are employed in the semiconductor nonvolatile memory device of the present invention.
[0022]
  The semiconductor nonvolatile memory device of the present invention includes a nonvolatile memory for storing data,BadSeries connection to volatile memoryUnsatisfactoryA transistor for selecting a volatile memory, NoVolatile memoryAndA semiconductor non-volatile memory device having a connection point with a transistor as an output terminal,
  GThe transistor is composed of a first transistor and a second transistor connected in parallel.,
First1 transistor becomes conductive when data is written or erasedThe second2 transistor becomes conductive when reading dataThe on-resistance when the first transistor becomes conductive is smaller than the on-resistance when the second transistor becomes conductive.Specially
It is a sign.
[0023]
  In the semiconductor nonvolatile memory device of the present invention,The second1 transistor channel widthThe secondLarger than the channel width of two transistorsAs a result, the on-resistance when the first transistor becomes conductive becomes smaller than the on-resistance when the second transistor becomes conductive.It is characterized by that.
[0024]
  In the semiconductor nonvolatile memory device of the present invention,The second1 transistor channel lengthThe secondSmaller than the channel length of 2 transistorsAs a result, the on-resistance when the first transistor becomes conductive becomes smaller than the on-resistance when the second transistor becomes conductive.It is characterized by that.
[0025]
[Action]
The semiconductor nonvolatile memory device of the present invention has a configuration in which two transistors connected in parallel are connected in series with a nonvolatile memory. The two transistors are divided into roles for writing and erasing and for reading.
The transistor for writing and erasing optimizes the channel width and the channel length so that a voltage and current necessary for writing can be sufficiently supplied to the nonvolatile memory so as not to be rewritten. The transistor for reading optimizes the channel width and the channel length so that power consumption becomes as small as possible during reading.
[0026]
By using these two transistors connected in parallel for writing and erasing and for reading, the semiconductor nonvolatile memory device can perform writing without causing rewriting, and can reduce power consumption during reading. It becomes possible to make it extremely small.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments for implementing a semiconductor nonvolatile memory device of the invention will be described with reference to the drawings.
[0028]
[Description of structure: Fig. 1]
First, the structure of the semiconductor nonvolatile memory device according to the embodiment of the present invention will be described with reference to the circuit diagram of FIG.
A nonvolatile memory 18 for storing data and two transistors 14 and 16 connected in series to the nonvolatile memory 18 for selection of the nonvolatile memory 18, and the first transistor 14 and the second transistor 16 are Connect in parallel. A first transistor 14 for bit selection used at the time of writing and erasing, between a source terminal 14S serving as a ground potential of the first transistor 14 and a drain terminal 18D for applying a program voltage of the nonvolatile memory 18; A second transistor 16 for bit selection used at the time of reading and a nonvolatile memory 18 for storing data are arranged. A connection point between the first transistor 14 and the second transistor 16 connected in parallel and the nonvolatile memory 18 connected in series with the first transistor 14 and the second transistor 16 is defined as an output terminal 6.
A write / erase selection signal is input to the gate terminal 14G of the first transistor 14. A read selection signal is input to the gate terminal 16G of the second transistor 16. A write / read selection signal is input to the gate terminal 18G of the nonvolatile memory 18.
[0029]
[Description of operation]
Next, the operation of the semiconductor nonvolatile memory device according to the embodiment of the present invention shown in FIG. 1 will be described. First, the write operation will be described.
When writing is performed, a write selection signal is input to the gate terminal 14G of the first transistor 14, and a non-selection signal is input to the gate terminal 16G of the second transistor 16. When a write selection signal is input to the gate terminal 14G, the first transistor 14 is turned on, while the second transistor 16 having a non-selection signal input to the gate terminal 16G is turned off.
The first transistor 14 is conductive and the second transistor 16 is non-conductive
Thus, writing is enabled by inputting a selection signal to the gate terminal 18G of the nonvolatile memory 18, and when a program voltage is applied to the drain terminal 18D of the nonvolatile memory 18, charges are injected into the charge stack of the nonvolatile memory 18. Then, the charge is accumulated in the charge stack and writing is performed.
[0030]
Next, the reading operation will be described. When reading is performed, a non-selection signal is input to the gate terminal 14G of the first transistor 14, and a read selection signal is input to the gate terminal 16G of the second transistor 16. The first transistor 14 to which the non-selection signal is input to the gate terminal 14G is turned off, and the second transistor 16 to which the read selection signal is input to the gate terminal 16G is turned on.
When the first transistor 14 is non-conductive and the second transistor 16 is conductive, reading can be performed by inputting a selection signal to the gate terminal 18G of the nonvolatile memory 18, and the drain terminal 18D of the nonvolatile memory 18 can be read. When the read voltage is applied, data is read from the nonvolatile memory 18.
[0031]
The write and non-write storage states of the nonvolatile memory 18 are obtained by applying a non-selection signal to the gate terminal 14G of the first transistor 14 and a selection signal to the gate terminal 16G of the second transistor 16, respectively. Obtained by measuring voltage.
When the nonvolatile memory 18 is in a write state, the threshold voltage of the nonvolatile memory 18 is high, so that a voltage value close to the ground potential can be obtained from the output terminal 6.
[0032]
Further, when the nonvolatile memory 18 is not written, the threshold voltage of the nonvolatile memory 18 is equal to or lower than the read voltage, so that a current flows between the drain terminal 18D and the source terminal 14S of the nonvolatile memory 18. . Therefore, a value obtained by dividing the read voltage by the on-resistance of the second transistor 16 and the on-resistance of the nonvolatile memory 18 is obtained from the output terminal 6.
When the on-resistance of the second transistor 16 is higher than the on-resistance of the nonvolatile memory 18, a voltage value close to the read voltage can be obtained from the output terminal 6.
[0033]
Next, the erase operation will be described. When erasing is performed, a selection signal is input to the gate terminal 14G of the first transistor 14, a non-selection signal is input to the gate terminal 16G of the second transistor 16, and a gate terminal 18G of the nonvolatile memory 18 is input. Input a non-selection signal. As a result, the first transistor 14 is turned on, the second transistor 16 is turned off, and the nonvolatile memory 18 is turned off.
At this time, by applying an erasing voltage (the voltage is the same as the program voltage and having the same or slightly higher voltage) from the drain terminal 18D of the nonvolatile memory 18, it is stored in the charge storage layer of the nonvolatile memory 18. Erasing is performed by extracting the charge.
[0034]
Here, writing to and reading from a nonvolatile memory represented by a flash memory (floating gate EEPROM) according to the present invention will be described in detail with reference to cross-sectional views of FIGS. First, the difference in the storage state depending on the charge storage state of the nonvolatile memory will be described with reference to FIG.
[0035]
The nonvolatile memory 18 has an N-channel transistor structure. The accumulated charge 36 at the time of writing is an electron.
On the surface of the P-type semiconductor substrate 32, a first insulating film 35, a charge storage layer 34, a second insulating film 37, and an N-type gate electrode 26 are sequentially formed. The first insulating film 35 is made of a silicon oxide film having a thickness of about 10 nm, the charge storage layer 34 is made of a polycrystalline silicon film having a thickness of 300 to 500 nm, and the second insulating film 37 has a total thickness of 10 nm. It is composed of a laminated film of a silicon oxide film and a silicon nitride film.
An N-type source electrode 28 and an N-type drain electrode 30 are provided on the surface of the P-type semiconductor substrate 32 in a region aligned with the N-type gate electrode 26.
[0036]
If there is an accumulated charge 36 made of electrons in the charge storage layer 34, the nonvolatile memory 18 is in a written state, and if there is no accumulated charge 36 in the charge storage layer 34, the nonvolatile memory 18 is written. It is not in a state.
[0037]
Next, the writing operation of the nonvolatile memory 18 will be described with reference to FIG. In FIG. 6, the same parts as those in FIG.
In writing to the nonvolatile memory 18, 0V is applied to the N-type source electrode 28, 12V to the N-type gate electrode 26, 10V to the N-type drain electrode 30, and 0V to the P-type semiconductor substrate 32, respectively. In this voltage application state, when the threshold voltage of the nonvolatile memory 18 is 1.0 V, the nonvolatile memory 18 becomes conductive and current flows between the N-type source electrode 28 and the N-type drain electrode 30.
[0038]
When a current flows between the N-type source region 28 and the N-type drain electrode 30, electrons having energy that can exceed the potential barrier of the first insulating film 35 are generated in the N-type channel 38 indicated by a broken line. At this time, holes are generated simultaneously with electrons.
The electrons generated in the N-type channel 38 are attracted by the electric field of the N-type gate electrode 26 and captured in the charge storage layer 34. Data is written by the storage charge 36 made of electrons being captured in the charge storage layer 34.
[0039]
Next, the read operation of the nonvolatile memory 18 will be described using the cross-sectional view of FIG. 7 and the graph of FIG. Also in FIG. 7, the same parts as those in FIG. The read voltage is 3V.
For reading from the nonvolatile memory 18, 0 V is applied to the N-type source electrode 28, 3 V to the N-type gate electrode 26, 3 V to the N-type drain electrode 30, and 0 V to the P-type semiconductor substrate 32.
When the writing described with reference to FIG. 6 is performed, the charge storage layer 34 is negatively charged because the stored charge 36 of electrons is stored, and the threshold voltage of the nonvolatile memory 18 is increased.
[0040]
The threshold voltage of the nonvolatile memory 18 before and after writing will be described with reference to FIG. The graph of FIG. 8 shows a single characteristic of the nonvolatile memory 18 shown in FIG. In the graph of FIG. 8, the vertical axis indicates the current (Ids) flowing between the N-type source electrode 28 and the N-type drain electrode 30 of the nonvolatile memory 18, and the horizontal axis indicates the voltage (Vgs) applied to the N-type gate electrode 26. ). The characteristics of the voltage applied to the N-type gate electrode 26 and the current flowing between the N-type source electrode 28 and the N-type drain electrode 30 are referred to as Vgs-Ids characteristics. The graph of FIG. 8 shows a Vgs-Ids characteristic 44 (threshold voltage 1.0 V) before writing and a Vgs-Ids characteristic 46 (threshold voltage 7.0 V) after writing in the nonvolatile memory 18.
At the time of reading, a read voltage (3 V) is applied to the N-type gate electrode 26 and the current Ids flowing between the N-type source electrode 28 and the N-type drain electrode 30 is evaluated.
[0041]
From the graph of FIG. 8, in the Vgs-Ids characteristic 46 after writing, when a voltage of 3 V (Vgs) is applied to the N-type gate electrode 26, the current flowing between the N-type source electrode 28 and the N-type drain electrode 30 The current value of (Ids) is 10^-12Less than A and almost no current flows.
In addition, in the Vgs-Ids characteristic 44 before writing, the current value of the current (Ids) flowing between the N-type source electrode 28 and the N-type drain electrode 30 when a voltage (Vgs) of 3 V is applied to the N-type gate electrode 26. 10^-3A or more, and the nonvolatile memory 18 is in a conductive state.
[0042]
When the read voltage is read at 3 V, the difference in current (Ids) after writing and before writing is about 10⁹Since it is nearly double, the current difference between the case where data is written and the case where data is not written is large, and it becomes easy to judge the storage state.
If the difference between the threshold voltages of the nonvolatile memory 18 before writing and after writing is small, the difference in current (Ids) also becomes small. In a state where the current difference is small before and after writing, it becomes difficult to determine the storage state of the nonvolatile memory 18 and it becomes necessary to rewrite data.
[0043]
【Example】
Next, a more specific embodiment of the present invention will be described below in which the first transistor and the second transistor are N-type MOS transistors, and the nonvolatile memory is an N-type floating gate nonvolatile memory.
First, the structure and operation of the semiconductor nonvolatile memory device of the present invention will be described with reference to FIGS.
[0044]
As shown in FIG. 9, the first N-type MOS transistor 20 and the second N-type MOS transistor 24 are connected in parallel, and the first N-type MOS transistor 20 and the second N-type MOS transistor 24 connected in parallel are connected. N-type floating gate nonvolatile memory 22 is connected in series. A connection point where the first N-type MOS transistor 20 and the second N-type MOS transistor 24 connected in parallel and the N-type floating gate nonvolatile memory 22 are connected in series is defined as an output terminal 6.
[0045]
The source of the first N-type MOS transistor 20 and the source of the second N-type MOS transistor 24 are connected to form a source terminal 20S, and the source terminal 20S is set to the ground potential. As described above, the source of the second N-type MOS transistor 24 is common to the source of the first N-type MOS transistor 20, and therefore, the source terminal 20S is illustrated in FIG.
The drain terminal 22D of the N-type floating gate nonvolatile memory 22 is applied with a program voltage (Vprog) at the time of writing and a read voltage (Vdd) at the time of reading.
[0046]
A selection signal is inputted to the gate terminal 20G of the first N-type MOS transistor 20 at the time of writing and erasing, so that the first N-type MOS transistor 20 is turned on. At the time of reading, a non-selection signal is input to the gate terminal 20G to make the first N-type MOS transistor 20 nonconductive.
A selection signal is input to the gate terminal 24G of the second N-type MOS transistor 24 at the time of reading, and the second N-type MOS transistor 24 is turned on. At the time of writing and erasing, a non-selection signal is input to the gate terminal 24G, and the second N-type MOS transistor 24 is turned off.
A selection signal is input to the gate terminal 22G of the N-type floating gate nonvolatile memory 22 during writing and reading, and a non-selection signal is input during erasing.
[0047]
At the time of writing and erasing, the first N-type MOS transistor 20 is turned on, the second N-type MOS transistor 24 is turned off, writing is performed to the N-type floating gate nonvolatile memory 22, and at the time of reading, the second N-type MOS transistor 24 is turned on. The storage state of the N-type floating gate nonvolatile memory 22 is read by setting the N-type MOS transistor 24 in a conductive state and the first N-type MOS transistor 20 in a non-conductive state.
[0048]
Next, the structure of the first N-type MOS transistor 20 and the second N-type MOS transistor 22 will be described.
The channel width of the first N-type MOS transistor 20 is W1, and the channel length is L1. The channel width of the second N-type MOS transistor 24 is W2, and the channel length is L2.
[0049]
Since the first N-type MOS transistor 20 is used at the time of writing and erasing, the channel length and the channel width are designed so as to reduce the on-resistance of the transistor. Since the second N-type MOS transistor 24 is used at the time of reading, the channel length and the channel width are designed so as to increase the on-resistance of the transistor.
That is, the first N-type MOS transistor 20 and the second N-type MOS transistor 24 are designed so that the channel width is W1> W2 and the channel length is L1 <L2. That is, the channel width W1 of the first N-type MOS transistor 20 is larger than the channel width W2 of the second N-type MOS transistor 24, and the channel length L1 of the first N-type MOS transistor 20 is the second N-type MOS transistor. It is made smaller than the channel length L2 of the transistor 24.
[0050]
Specific examples of the channel length and channel width are shown as follows: W1 = 50 μm, W2 = 2 μm, L1 = 0.6 μm, L2 = 20 μm.
When the channel length and channel width are as described above, the on-resistance when a voltage of 12 V is applied to the gate terminal 20G and drain of the first N-type MOS transistor 20 is 120Ω, and the second N-type MOS transistor 24 When a voltage of 3 V is applied to the gate terminal 24G and the drain of the transistor, the on-resistance is 3 MΩ.
[0051]
FIG. 9 shows how the voltage appearing between the source and drain of the N-type floating gate nonvolatile memory 22 changes by setting the channel width and channel length of the first N-type MOS transistor 20 to the above-described numerical values. This will be described with reference to FIGS. 10 and 13. First, the graph of FIG. 10 will be described. In the graph of FIG. 10, the vertical axis represents the potential difference (Vprog−Vout) between the program voltage (Vprog) and the voltage (Vout) at the output terminal 6 during writing, and the horizontal axis represents the channel of the first N-type MOS transistor 20. The width is shown.
The potential difference of Vprog−Vout is a voltage actually applied between the source and drain of the N-type floating gate nonvolatile memory 22.
[0052]
As is apparent from the graph of FIG. 10, the potential difference (Vprog−Vout) increases as the channel width of the first N-type MOS transistor 20 increases. This is because when the channel width W1 of the first N-type MOS transistor 20 is increased, the voltage drop between the source and the drain is reduced, the voltage drop of the program voltage is reduced, and a voltage close to the program voltage is applied to the N-type floating gate nonvolatile memory. Thus, the voltage can be applied between the source and drain of 22.
[0053]
Next, the graph of FIG. 13 will be described. In FIG. 13, the vertical axis represents the potential difference (Vprog−Vout) between the program voltage (Vprog) at the time of writing and the voltage (Vout) of the output terminal 6, and the horizontal axis represents the channel length of the first N-type MOS transistor 20. Show.
The potential difference of Vprog−Vout is a voltage actually applied between the source and drain of the N-type floating gate nonvolatile memory 22.
[0054]
As is apparent from the graph of FIG. 13, the potential difference (Vprog−Vout) increases as the channel length of the first N-type MOS transistor 20 decreases. This is because when the channel length L1 of the first N-type MOS transistor 20 is increased, the voltage drop between the source and the drain is reduced, the voltage drop of the program voltage is small, and the voltage close to the program voltage is N-type floating gate non-volatile. It can be applied between the source and drain of the memory 22.
[0055]
The structure of the N-type floating gate nonvolatile memory 22 will be described with reference to the cross-sectional view of FIG.
A tunnel oxide film 52, an N-type floating gate 50, an inter-polysilicon insulating film 54, and an N-type control gate 48 are sequentially provided on the surface of the P-type semiconductor substrate 32. An N-type source electrode 28 and an N-type drain electrode 30 are provided on the surface of the P-type semiconductor substrate 32 in a region aligned with the N-type control gate 48.
[0056]
The tunnel oxide film 52 has a role of passing a charge at the time of writing and serving as a potential barrier against the charge accumulated in the N-type floating gate 50.
The tunnel oxide film 52 is a silicon oxide film having a thickness of about 6 to 10 nm.
[0057]
The inter-polysilicon insulating film 54 increases the electrostatic coupling ratio between the N-type floating gate 50 and the N-type control gate 48 so that the voltage applied to the N-type control gate 48 is not attenuated as much as possible. It has a role of transmitting to the floating gate 50.
For this reason, the inter-polysilicon insulating film 54 is a three-layered film in which a silicon oxide film having a relative dielectric constant larger than that of the silicon oxide film is sandwiched between the silicon oxide films.
[0058]
The N-type floating gate 50 is made of a polycrystalline silicon film having a thickness of 300 to 500 nm, and the N-type floating gate nonvolatile memory 22 is in a writing state as long as charges are accumulated in the N-type floating gate 50. If no charge is accumulated in the N-type floating gate 50, the N-type floating gate nonvolatile memory 22 is not written.
[0059]
Next, the write operation of the N-type floating gate nonvolatile memory 22 will be described with reference to FIGS. The program voltage is 12V.
By inputting a write selection signal (12V) to the gate terminal 20G of the first N-type MOS transistor 20, the first N-type MOS transistor 20 becomes conductive, and the gate terminal 24G of the second N-type MOS transistor 24 is turned on. Unselected signal
By inputting (0 V), the second N-type MOS transistor 24 is turned off.
[0060]
When the selection signal (12V) is input to the gate terminal 22G of the N-type floating gate nonvolatile memory 22 with the first N-type MOS transistor 20 in the conductive state and the second N-type MOS transistor 24 in the non-conductive state, The type floating gate nonvolatile memory 22 can be written, and when a program voltage (12 V) is applied to the drain terminal 22D of the N type floating gate nonvolatile memory 22, the N type floating gate nonvolatile memory 22 is written.
In order to apply a program voltage to the gate terminal 20G of the first N-type MOS transistor 20 and the gate terminal 22G of the N-type floating gate nonvolatile memory 22, a read voltage (3V) is applied to the gate terminal 24G and the gate terminal 22G. Compared to the case, the channel region of the first N-type MOS transistor 20 and the channel region of the N-type floating gate nonvolatile memory 22 are in a strong inversion state. Therefore, the on-resistances of the first N-type MOS transistor 20 and the N-type floating gate nonvolatile memory 22 are very small compared to the conduction state when the read voltage is applied.
[0061]
At this time, a program current 40 flows from the drain terminal 22D of the N-type floating gate nonvolatile memory 22 toward the source terminal 20S of the first N-type MOS transistor 20. As described above, the difference in structure between the first N-type MOS transistor 20 and the second N-type MOS transistor 24 is as follows. The channel width of the first N-type MOS transistor 20 is as large as 50 μm and the channel length is 0. It is designed as small as 6 μm. The second N-type MOS transistor 24 has a channel width of 2 μm and a channel length of 20 μm.
In addition to the pattern shape for reducing the on-resistance in this way, since the program voltage is applied to the gate terminal 20G of the first N-type MOS transistor 20, the first N-type MOS transistor 20 is applied. The on-resistance is further reduced.
[0062]
That is, the voltage drop between the source and the drain in the first N-type MOS transistor 20 is reduced, a sufficient potential difference is generated between the source and the drain of the N-type floating gate nonvolatile memory 22, and the N-type floating gate nonvolatile memory 22. The electrons flowing in the channels can be sufficiently accelerated.
Charges (electrons) that are sufficiently accelerated and have energy exceeding the potential barrier of the tunnel oxide film 52 are attracted to the electric field generated by the program voltage (12 V) applied to the gate terminal 22G of the N-type floating gate nonvolatile memory 22. As a result, it is injected into the N-type floating gate 50 of the N-type floating gate nonvolatile memory 22 for writing.
Although the threshold voltage before writing of the N-type floating gate nonvolatile memory 22 is 1.0 V, the threshold voltage is greatly shifted to 7.0 V after writing, and normal writing is performed.
[0063]
Next, the read operation will be described with reference to FIG. 8, FIG. 11, and FIG. In FIG. 11, the same parts as those in FIG. The read voltage (Vdd) is 3V.
The potential difference (Vdd−Vout) between the read voltage (Vdd) and the voltage (Vout) of the output terminal 6 in FIG. 11 represents the actual voltage applied between the source and drain of the N-type floating gate nonvolatile memory 22.
[0064]
By inputting a non-selection signal (0 V) to the gate terminal 20 G of the first N-type MOS transistor 20, the first N-type MOS transistor 20 becomes non-conductive, and the gate terminal 24 G of the second N-type MOS transistor 24. When the selection signal (3V) is input to the second N-type MOS transistor 24, the second N-type MOS transistor 24 becomes conductive.
[0065]
When a selection signal (3V) is input to the gate terminal 22G of the N-type floating gate nonvolatile memory 22 with the first N-type MOS transistor 20 in a non-conductive state and the second N-type MOS transistor 24 in a conductive state, the N-type The floating gate nonvolatile memory 22 can be read, and when a read voltage (3 V) is applied to the drain terminal 22D of the N type floating gate nonvolatile memory 22, the N type floating gate nonvolatile memory 22 is read.
[0066]
In the write and non-write storage states of the N-type floating gate nonvolatile memory 22, the first N-type MOS transistor 20 is in a non-conductive state, the second N-type MOS transistor 24 is in a conductive state, and the voltage at the output terminal 6 is set. It is obtained by measuring.
When the N-type floating gate nonvolatile memory 22 is in a writing state, electrons are accumulated as charges 36 in the floating gate 50 shown in FIG. 12, and therefore the threshold voltage of the N-type floating gate nonvolatile memory 22 becomes high. Therefore, as shown by a curve 46 in FIG.^-12A value close to A and a value close to the ground potential can be obtained from the output terminal 6.
[0067]
When the N-type floating gate nonvolatile memory 22 is not written, the threshold voltage of the N-type floating gate nonvolatile memory 22 is 1.0 V that is equal to or lower than the read voltage (3.0 V). The read current 42 is 10 toward the source terminal 20S from the drain terminal 22D of the memory 22^-6Flows about A.
This is because the current flowing only in the N-type floating gate nonvolatile memory 22 is 10^-3Although it is about A, since the second N-type MOS transistor 24 is connected in series to the N-type floating gate nonvolatile memory 22, the current value is 10 as described above.^-6Decrease to about A.
[0068]
As described above, since the second N-type MOS transistor 24 has a channel width of 2 μm and a channel length of 20 μm, the on-resistance of the second N-type MOS transistor 24 is increased and consumption during reading is increased. Power can be reduced
The
Therefore, a value obtained by dividing the read voltage by the on-resistance of the second N-type MOS transistor 24 and the on-resistance of the N-type floating gate nonvolatile memory 22 is obtained from the output terminal 6. In other words, the current value that flows at the time of reading can be determined by the on-resistance of the second N-type MOS transistor 24. At the time of reading from the N-type floating gate nonvolatile memory 22, the current flowing through the N-type floating gate nonvolatile memory 22 was as extremely low as about 1 nA.
[0069]
The output of the output terminal 6 is a voltage obtained by subtracting the voltage drop, which is obtained by multiplying the ON resistance of the N-type floating gate nonvolatile memory 22 by the current value flowing at the time of reading, from the reading voltage. The output voltage value of the output terminal 6 is substantially equal to the read voltage when the N-type floating gate nonvolatile memory 22 is not written.
[0070]
In the erase operation, a selection signal is input to the gate terminal 20G of the first N-type MOS transistor 20, a non-selection signal is input to the gate terminal 24G of the second N-type MOS transistor 24, and an N-type floating gate is input. A non-selection signal is input to the gate terminal 22G of the nonvolatile memory 22.
[0071]
As a result, the first N-type MOS transistor 20 becomes conductive, the second N-type MOS transistor 24 becomes non-conductive, and the N-type floating gate nonvolatile memory 22 becomes non-conductive. At this time, by applying an erasing voltage (the same voltage as the program voltage and the same or slightly higher voltage) from the drain terminal 22D of the N-type floating gate nonvolatile memory 22, the N-type floating gate nonvolatile memory 22 is applied. The stored charge 36 of the N-type floating gate 50 is extracted to perform erasing.
[0072]
According to the semiconductor nonvolatile memory device of the present invention, the write / erase transistor and the read transistor are connected in parallel, and the nonvolatile memory is connected in series to the two transistors connected in parallel. . By using two transistors separately for writing and erasing, the potential difference and current necessary for writing and erasing can be applied between the source and drain of the nonvolatile memory during writing and erasing, and power consumption is reduced during reading. Thus, the stored charge output of the nonvolatile memory can be read out.
[0073]
In the above description, the floating gate type nonvolatile memory is used as the nonvolatile memory. However, the nonvolatile memory is not limited to the MNOS type nonvolatile memory that holds charges in the trap of the silicon nitride film. Even if used, the same effects as described above can be obtained.
[0074]
Here, the MNOS type nonvolatile memory will be described. In the following description, the structure of the N-type MNOS nonvolatile memory 56 having an N-type gate will be described with reference to the cross-sectional view of FIG.
A tunnel oxide film 35, a memory nitride film 58, and an N-type gate 26 are sequentially formed on the surface of the P-type semiconductor substrate 32. An N-type source electrode 28 and an N-type drain electrode 30 are provided on the surface of the P-type semiconductor substrate 32 in a region aligned with the N-type gate 26.
[0075]
The tunnel oxide film 35 has a role of passing a charge at the time of writing and serving as a potential barrier against the charge accumulated in the memory nitride film 58.
As the tunnel oxide film 35, a silicon oxide film of about 3 to 5 nm is used.
[0076]
The memory nitride film 58 has a role of trapping charges, and enters a write state by trapping charges at the trap level by writing.
The memory nitride film 58 is made of a silicon nitride film, and the silicon nitride film has a film quality of about 9 to 14 nm with a silicon stoichiometric ratio that changes the stoichiometric ratio by increasing the amount of silicon relative to nitrogen. A membrane is used. As the number of silicon dangling bonds increases, the amount of charge that can be accumulated in the memory nitride film 58 can be increased. Since the tunnel oxide film 35 of the MNOS nonvolatile memory is as thin as about 3 to 5 nm as compared with the tunnel oxide film of the floating gate nonvolatile memory, writing can be performed at a low voltage.
[0077]
If the charge is stored in the memory nitride film 58, the N-type MNOS nonvolatile memory 56 is in the write state, and if the charge is not stored in the memory nitride film 58, the N-type MNOS nonvolatile is used. The memory 56 is not written.
[0078]
Although not shown in FIG. 14, a silicon oxide film having a thickness of 3 to 5 nm is provided between the memory nitride film 58 of the N-type MNOS nonvolatile memory 56 and the N-type gate 26, and the memory nitride film Even in the semiconductor nonvolatile memory device structure with improved charge retention characteristics of 58, if the structure of the present invention in which a nonvolatile memory is connected in series to two transistors connected in parallel, the same effect as described above can be obtained. It is done.
[0079]
In the above description, an example in which N-type MOS transistors are used as the first transistor 14 and the second transistor 16 has been described. However, the present invention is not limited to the N-type MOS transistor. The same effect can be obtained even if the second transistor is formed of a P-type MOS transistor.
Further, in the semiconductor nonvolatile memory device of the present invention, the same effect can be obtained even if both the N-type MOS transistor and the P-type MOS transistor are used as the first transistor 14 and the second transistor 16.
[0080]
The case where the first N-type MOS transistor 20 and the second N-type MOS transistor 24 are P-type MOS transistors and the N-type floating gate nonvolatile memory 22 is used will be described below. First, the write operation will be described with reference to the circuit diagram of FIG.
The program voltage (Vprog) is -12V and the read voltage is -3V.
The
[0081]
By inputting a write selection signal (−12V) to the gate terminal 60G of the first P-type MOS transistor 60, the first P-type MOS transistor 60 becomes conductive, and the gate of the second P-type MOS transistor 62 is turned on. Non-selection signal at terminal 62G
By inputting (0V), the second P-type MOS transistor 62 is turned off.
When the first P-type MOS transistor 60 is in a conductive state and the second P-type MOS transistor 62 is in a non-conductive state, a selection signal (0 V) is input to the gate terminal 22G of the N-type floating gate nonvolatile memory 22. Thus, the N-type floating gate nonvolatile memory 22 can be written, and when the program voltage (−12 V) is applied to the drain terminal 22D of the N-type floating gate nonvolatile memory 22, the N-type floating gate nonvolatile memory 22 can be written. Done.
[0082]
Since a program voltage (−12V) is applied to the gate terminal 60G of the first P-type MOS transistor 60 and the gate terminal 22G of the N-type floating gate nonvolatile memory 22 is at the ground potential, the gate terminal 62G and the gate terminal 22G The channel region of the first P-type MOS transistor 60 and the channel region of the N-type floating gate nonvolatile memory 22 are more strongly inverted than when a read voltage (−3 V) is applied to the first P-type MOS transistor 60.
Therefore, the on-resistances of the first P-type MOS transistor 60 and the N-type floating gate nonvolatile memory 22 are very small compared to the conduction state when the read voltage is applied.
[0083]
At this time, a program current 40 flows from the source terminal 60S of the first P-type MOS transistor 60 toward the drain terminal 22D of the N-type floating gate nonvolatile memory 22.
The channel length and channel width of the first P-type MOS transistor 60 and the second P-type MOS transistor 62 are the same as described above, W1 = 50 μm, W2 = 2 μm, L1 = 0.6 μm, L2 = 20 μm. The channel length (L1) of the first P-type MOS transistor 60 is smaller than the channel length (L2) of the second P-type MOS transistor 62, and the channel width (W1) of the first P-type MOS transistor 60 is Is larger than the channel width (W2) of the second P-type MOS transistor 62.
[0084]
The first P-type MOS transistor 60 has a channel width as large as 50 μm and a channel length as small as 0.6 μm. Therefore, in addition to reducing the on-resistance, since the program voltage (−12V) is applied to the gate terminal 60G of the first P-type MOS transistor 60, the first P-type MOS transistor 60 On-resistance is further reduced.
[0085]
That is, the voltage drop between the source and the drain in the first P-type MOS transistor 60 is reduced, a sufficient potential difference is generated between the source and the drain of the N-type floating gate nonvolatile memory 22, and the N-type floating gate nonvolatile memory 22. Electrons flowing through the channels can be sufficiently accelerated.
As shown in FIG. 12, charges 36 (electrons) that are sufficiently accelerated and have energy exceeding the potential barrier of the tunnel oxide film 52 are injected into the N-type floating gate 50 of the N-type floating gate nonvolatile memory 22. Is written.
[0086]
In the above description, an example in which both the channel length and the channel width are changed as means for making the on-resistances of the two transistors for selection different is described. However, if only the channel lengths of the two transistors are changed, Alternatively, the on-resistance may be varied by changing only the channel widths of the two transistors.
[0087]
Further, in the above description, the example has been described in which the threshold voltage of the nonvolatile memory is shifted to the enhancement side to obtain the write state. Conversely, the threshold voltage of the nonvolatile memory is shifted to the depletion side. It may be in a writing state. Further, although the example of performing erasing by extracting the charge from the charge storage layer has been described, it may be performed by injecting the charge into the charge storage layer.
[0088]
【The invention's effect】
As apparent from the above description, the semiconductor nonvolatile memory device according to the present invention has a configuration in which two transistors connected in parallel are connected in series with a nonvolatile memory. The two transistors are divided into roles for writing and erasing and for reading.
The transistor for writing and erasing optimizes the channel width and the channel length so that a voltage and current necessary for writing can be sufficiently supplied to the nonvolatile memory so as not to be rewritten. The transistor for reading optimizes the channel width and the channel length so that power consumption becomes as small as possible during reading.
[0089]
By using these two transistors connected in parallel for writing and erasing and for reading, the semiconductor nonvolatile memory device can perform writing without causing rewriting, and can reduce power consumption during reading. The semiconductor nonvolatile memory device of the present invention has an effect that can be made extremely small.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor nonvolatile memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a conventional semiconductor nonvolatile memory device.
FIG. 3 is a graph showing a relationship between on-resistance of a transistor for selection and a threshold voltage after writing in a nonvolatile memory.
FIG. 4 is a graph showing a relationship between an on-resistance of a selection transistor and a current value at the time of reading from a nonvolatile memory.
FIG. 5 is a cross-sectional view for explaining a charge accumulation state in the nonvolatile memory according to the embodiment of the present invention.
FIG. 6 is a cross-sectional view for explaining writing in the nonvolatile memory according to the embodiment of the present invention.
FIG. 7 is a cross-sectional view for explaining reading in the nonvolatile memory according to the embodiment of the present invention.
FIG. 8 is a graph of Vgs-Ids characteristics showing a threshold voltage change before and after writing in the nonvolatile memory according to the embodiment of the present invention;
FIG. 9 is a circuit diagram for explaining writing in the semiconductor nonvolatile memory device in the embodiment of the present invention;
FIG. 10 is a graph showing the relationship between the channel width of a selection transistor of the semiconductor nonvolatile memory device and the potential difference generated between the source and drain of the nonvolatile memory in the embodiment of the present invention.
FIG. 11 is a circuit diagram for explaining reading of the semiconductor nonvolatile memory device in the embodiment of the present invention;
FIG. 12 is a cross-sectional view for explaining the structure of an N-type floating gate nonvolatile memory of the semiconductor nonvolatile memory device according to the embodiment of the present invention.
FIG. 13 is a graph showing the relationship between the channel length of a selection transistor of the semiconductor nonvolatile memory device and the potential difference generated between the source and drain of the nonvolatile memory in the embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a nonvolatile memory having a different structure of the semiconductor nonvolatile memory device according to the embodiment of the present invention.
FIG. 15 is a circuit diagram for explaining writing in a semiconductor nonvolatile memory device having a different structure of the semiconductor nonvolatile memory device in the embodiment of the present invention;
[Explanation of symbols]
6: output terminal 14: first transistor 14S: source terminal
14G: Gate terminal 16: Second transistor
16G: Gate terminal 18: Non-volatile memory 18G: Gate terminal
18D: Drain terminal 20: First N-type MOS transistor
21: N-type MOS transistor 22: N-type floating gate nonvolatile memory
24: Second N-type MOS transistor 26: N-type gate electrode
28: N-type source electrode 30: N-type drain electrode
32: P-type semiconductor substrate 34: Charge storage layer 35: First insulating film
36: Accumulated charge 37: Second insulating film 38: N-type channel
48: N-type control gate 50: N-type floating gate
52: Tunnel oxide film 54: Insulating film between polysilicon
56: N-type MNOS nonvolatile memory 58: Memory nitride film
60: First P-type MOS transistor
62: Second P-type MOS transistor

Claims (3)

Semiconductor non-volatile memory device comprising: a non-volatile memory for storing data; and a transistor connected in series to the non-volatile memory to select the non-volatile memory, and having a connection point between the non-volatile memory and the transistor as an output terminal Because
The transistor comprises a first transistor and a second transistor connected in parallel,
The first transistor becomes conductive when data is written and erased,
The second transistor becomes conductive when reading data ,
2. The semiconductor nonvolatile memory device according to claim 1, wherein an on-resistance when the first transistor is turned on is smaller than an on-resistance when the second transistor is turned on . The channel width of the first transistor, by size Kusuru than the channel width of the second transistor, the first on-resistance and the second transistor when the transistor is turned and the conducting state The semiconductor nonvolatile memory device according to claim 1, wherein the semiconductor nonvolatile memory device is smaller than an on-resistance when The channel length of the first transistor, by Kusuru be smaller than the channel length of the second transistor, the first on-resistance and the second transistor when the transistor is turned and the conducting state The semiconductor nonvolatile memory device according to claim 1, wherein the semiconductor nonvolatile memory device is smaller than an on-resistance when

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