JP3956828B2 - OFDM receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an OFDM (orthogonal frequency division multiplexing) receiver, and more specifically, reduces the influence of interference waves from a synchronously demodulated data carrier output from an FFT (fast fourier transform) unit. Related to technology.
[0002]
[Prior art]
FIG. 4 is a circuit diagram showing a part of an example of a conventional OFDM receiver. In FIG. 4, 1 is a receiving antenna, 2 is a tuner, 3 is an A / D conversion unit, 4 is a synchronization unit, 5 is an FFT unit, and 6 is a demodulation unit, and is received by the receiving antenna 1 and selected by the tuner 2. The OFDM signal thus converted is converted into a digital signal by the A / D conversion unit 3, synchronization is established by the synchronization unit 4, fast Fourier transform is performed by the FFT unit 5, and demodulated by the demodulation unit 6.
[0003]
FIG. 5 is a diagram showing an insertion position of an SP (scattered pilot) signal in ISDB-T (integrated services digital broadcasting system for terrestrial), which is a transmission system of Japanese terrestrial digital broadcasting. In ISDB-T, on the transmitting side, a carrier for sending an SP signal so that a ratio of 1/12 in the frequency direction of the OFDM symbol, a ratio of 1/4 in the time direction, and 3 carriers are shifted every time one symbol is advanced. (SP carrier) is inserted.
[0004]
Here, since the SP signal is a fixed value, the receiving side can know how the data carrier in the vicinity of the SP carrier is affected during transmission by looking at the level of the received SP carrier. In addition, if processing (equalization processing) such that the SP carrier is at the same level as that at the time of transmission is performed on a nearby data carrier, the level of the data carrier at the time of transmission can be restored.
[0005]
However, if the interference frequency matches the frequency of the SP carrier in a situation where interference waves such as spurious and the same channel are received, the level of the SP carrier will fluctuate due to factors other than the transmission path characteristics. The data carrier cannot be restored by the equalization process.
[0006]
In order to cope with this, an SP carrier greatly deviating from the average value of SP carriers is detected using the average and dispersion values of SP carriers, and data carriers in the vicinity of this SP carrier are disturbed. And a method of using it for improving the performance of error correction processing at a later stage has been proposed (for example, Patent Document 1) .
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-252040
[Problems to be solved by the invention]
However, the above method aims at improving the error correction performance based on the information as to whether or not the SP carrier is disturbed, and does not reduce the influence of the disturbing wave from the data carrier. In order to further improve reception performance, it is necessary to perform equalization processing while reducing the influence of interference waves from the data carrier that is output from the FFT unit 5 and is subjected to synchronous demodulation .
[0009]
In view of the above, the present invention provides an OFDM receiver capable of performing equalization processing on a synchronously demodulated data carrier in which the influence of an interference wave is reduced and improving reception performance. The purpose is to do.
[0010]
[Means for Solving the Problems]
The OFDM receiving apparatus of the present invention includes an interference reduction unit that reduces the influence of interference waves from the data carrier that is synchronously demodulated and output from the FFT unit.
[0011]
According to the present invention, since the interference reduction unit that reduces the influence of the interference wave from the data carrier that is synchronously demodulated output from the FFT unit is provided, the equalization processing is performed on the data carrier that is synchronously demodulated with the influence of the interference wave reduced. It can be performed.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram showing a part of an embodiment of the present invention. In FIG. 1, 7 is a receiving antenna, 8 is a tuner, 9 is an A / D conversion unit, 10 is a synchronization unit, 11 is an FFT unit, and 12 is a demodulation unit.
[0013]
In the demodulation unit 12, reference numeral 13 denotes a data carrier for differential demodulation of the carrier output from the FFT unit 11, a data carrier for synchronous demodulation demodulated by QPSK, 16QAM or 64QAM, and an SP carrier. It is a carrier selection part to sort into.
[0014]
14 is a differential demodulator that performs differential demodulation on the data carrier that is differentially demodulated output from the carrier selector 13, and 15 is an SP that is output from the carrier selector 13 to perform interpolation processing and average value calculation processing. Reference numeral 16 denotes an SP carrier processing unit that performs interference vector calculation processing and interference detection signal generation processing, and 16 is a synchronous demodulation unit that performs synchronous demodulation on the data carrier that is output from the carrier selection unit 13 and that is subjected to synchronous demodulation .
[0015]
In the SP carrier processing unit 15, 17 is a memory for storing SP carriers for 4 symbols to obtain one SP carrier for every 3 carriers, and 18 is a data carrier that performs interpolation processing on the output of the memory 17. The interpolation processing unit obtains the SP carrier.
[0016]
Reference numeral 19 inputs the output of the interpolation processing unit 18 and calculates the average value of the SP carrier formed by the interpolation processing, the calculation processing of the magnitude (interference vector) of the interference caused by the interference wave received by the SP carrier, and the interference vector It is a disturbance detection part which performs the preparation process of the disturbance detection signal which shows whether an absolute value exceeds the allowable value.
[0017]
In the synchronous demodulator 16, reference numeral 20 denotes a delay unit for delaying the data carrier to be synchronously demodulated output from the carrier selector 13, and has a delay time equal to the processing delay time in the SP carrier processor 15.
[0018]
An interference reduction unit 21 reduces the influence of interference waves from the data carrier to be synchronously demodulated output from the delay unit 20 and the data carrier to be synchronously demodulated by inputting the interference vector transmitted from the interference detection unit 19.
[0019]
22 is a selector which is controlled by the interference detection signal and selects a data carrier to be synchronously demodulated output from the delay unit 20 or a data carrier to be synchronously demodulated output from the interference reduction unit 21, and an interference whose SP carrier exceeds an allowable value. when not receiving, select the data carrier to be synchronously demodulated output from the delay unit 20, when receiving the interference SP carrier exceeds the allowable value, synchronously demodulated output from interference reduction section 21 data The carrier is to be selected.
[0020]
Reference numeral 23 denotes a selector which is controlled by the interference detection signal and selects an average value of SP carriers output from the interference detection unit 19 or an interpolated SP carrier output from the interpolation processing unit 18, and the SP carrier has an allowable value. When the interference exceeds the allowable value, the SP carrier selected by the interpolation processing unit 18 is selected. When the SP carrier receives the interference exceeding the allowable value, the interference detection unit 19 outputs the interference. The average value of the SP carrier is selected.
[0021]
24, when the SP carrier is not subjected to interference exceeding the allowable value, the data carrier to be synchronously demodulated output from the delay unit 20 is equalized with reference to the interpolated SP carrier , and the SP carrier is allowed. When receiving interference exceeding the value, the equalization processing unit performs equalization processing on the data carrier to be synchronously demodulated output from the interference reduction unit 21 with the average value of the SP carriers as a reference.
[0022]
FIG. 2 is a circuit diagram showing a configuration of the disturbance detection unit 19. In FIG. 2, 25 is an n-stage shift register (where n is an odd number), 26 is an adder that adds the parallel output values of the n-stage shift register 25, and 27 is the output value of the adder 26 of the n-stage shift register 25. It is a divider that divides by the number of stages n and calculates an average value of SP carriers that are interpolated.
[0023]
Reference numeral 28 denotes a subtractor for calculating an interference vector by subtracting the output value of the [(n + 1) / 2] -stage register 25A of the n-stage shift register 25 from the output value of the divider 27, and 29 is output from the subtractor 28. The absolute value calculation circuit 30 calculates the absolute value of the interference vector, and the absolute value 30 of the interference vector output from the absolute value calculation circuit 29 is compared with an allowable value (threshold) to prevent the SP carrier from exceeding the allowable value. It is a comparator that creates a tampering detection signal indicating whether or not it is received.
[0024]
In this embodiment, the OFDM signal received by the receiving antenna 7 and selected by the tuner 8 is converted into a digital signal by the A / D converter 9, synchronization is established by the synchronizer 10, and high speed is obtained by the FFT unit 11. It is Fourier transformed, demodulated by the demodulator 12, and transmitted to the frequency / time deinterleaver of the error corrector.
[0025]
In the demodulator 12, the output of the FFT unit 11 is classified into a data carrier that is differentially demodulated by the carrier selector 13, a data carrier that is synchronously demodulated, and an SP carrier. The differential demodulation unit 14 performs differential demodulation on the data carrier to be differentially demodulated output from the carrier selection unit 13.
[0026]
The SP carriers output from the carrier selection unit 13 are stored in the memory 17, and one SP carrier is obtained for every three carriers. The interpolation processing unit 18 performs interpolation processing between SP carriers, and is interpolated. The SP carrier is transmitted to the interference detection unit 19.
[0027]
In the interference detection unit 19, the output of the interpolation processing unit 18 is input to the n-stage shift register 25, the past n SP carriers are stored, and the adder 26 adds the parallel output value of the n-stage shift register 25, The divider 27 divides the output value of the adder 26 by the number n of stages of the n-stage shift register 25, and calculates the average value of the SP carriers interpolated.
[0028]
Further, the subtractor 28 subtracts the output value of the register 25A at the center of the n-stage shift register 25 from the output value of the divider 27 to calculate the interference vector. Further, the absolute value calculation circuit 29 outputs the interference vector from the subtractor 28. The absolute value of the interference vector is calculated, and the comparator 30 compares the absolute value of the interference vector output from the absolute value calculation circuit 29 with the threshold value to generate an interference detection signal.
[0029]
In the synchronous demodulator 16, the delay carrier 20 delays the data carrier output from the carrier selector 13 to be demodulated by a delay time equal to the processing delay time of the SP carrier processor 15. In the interference reduction unit 21, the interference vector output from the interference detection unit 19 is subtracted from the data carrier output from the delay unit 20 for synchronous demodulation .
[0030]
Here, when the SP carrier is not subjected to interference exceeding the allowable value, the selector 22 selects a data carrier to be synchronously demodulated that has not been subjected to interference reduction processing and is output from the delay unit 20, and the selector 23 The interpolated SP carrier output from the interpolation processing unit 18 is selected.
[0031]
Therefore, in this case, the equalization processing unit 24 performs synchronous demodulation on which the interference reduction processing output from the delay unit 20 is not performed with reference to the interpolated SP carrier output from the interpolation processing unit 18. An equalization process is performed on the data carrier .
[0032]
On the other hand, when the SP carrier is subjected to interference exceeding the allowable value, the selector 22 selects the data carrier to be synchronously demodulated, which has been subjected to the interference reduction processing, output from the interference reduction unit 21, and the selector 23 Selects the average value of the SP carriers output from the interference detector 19 .
[0033]
Therefore, in this case, the equalization processing unit 24 uses the average value of the SP carriers output from the interference detection unit 19 as a reference and performs synchronous demodulation data on which the interference reduction processing output from the interference reduction unit 21 has been performed. The equalization process is performed on the carrier .
[0034]
FIG. 3 is a diagram for explaining a process of reducing the influence of an interference wave from a data carrier to be synchronously demodulated, which is performed in the present embodiment. In FIG. 3A, 31 is the value of the received SP carrier (the value of the SP carrier stored in the register 25A of the n-stage shift register 25), and 32 is the estimated value of the SP carrier that is not disturbed by the disturbing wave (divider). In the subtractor 28, the calculation [(received SP carrier value 31) − (estimated value 32 of the SP carrier not disturbed by the jamming wave)] is performed. Is calculated.
[0035]
In Figure 3B, 34 is the value of the data carrier A demodulating synchronized received (the value of the data carrier to be synchronously demodulated output from the delay unit 20), the interference reduction unit 21 demodulates sync and [(received data (Carrier value 34) + (vector 35 whose direction is opposite to that of interference vector 33)] = [(received data carrier value 34 for synchronous demodulation ) − (interference vector 33)] An estimated value 36 of the data carrier to be synchronously demodulated without interference (the value of the data carrier to be synchronously demodulated with the influence of the interference wave reduced) 36 is calculated.
[0036]
As described above, according to the present embodiment, the demodulation unit 12 includes the carrier selection unit 13, the SP carrier processing unit 15, and the synchronous demodulation unit 16, and the SP carrier processing unit 15 includes the memory 17, the interpolation processing unit 18, and the interference detection. 19, and the synchronous demodulator 16 includes a delay unit 20, an interference reduction unit 21, selectors 22 and 23, and an equalization processing unit 24, thereby preventing interference from the data carrier that is synchronously demodulated and output from the FFT unit 11. Equalization processing can be performed on a data carrier that is synchronously demodulated with reduced wave effects. Therefore, reception performance can be improved.
[0037]
In this embodiment, the interference detection signal is used as a selection control signal for the selectors 22 and 23, and is also sent to the frequency / time deinterleaving unit and used as decoding information.
[0038]
【The invention's effect】
As described above, according to the present invention, by including the interference reduction unit that reduces the influence of the interference wave from the synchronous modulation data carrier output from the FFT unit, the data to be synchronously demodulated with the influence of the interference wave reduced. Since equalization processing can be performed on the carrier , reception performance can be improved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a part of an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a disturbance detection unit provided in an embodiment of the present invention.
FIG. 3 is a diagram for explaining a process of reducing the influence of an interfering wave from a data carrier to be synchronously demodulated performed in an embodiment of the present invention.
FIG. 4 is a circuit diagram showing a part of an example of a conventional OFDM receiver.
FIG. 5 is a diagram illustrating an insertion position of an SP signal in ISDB-T.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Reception antenna 2 ... Tuner 3 ... A / D conversion part 4 ... Synchronization part 5 ... FFT part 6 ... Demodulation part 7 ... Reception antenna 8 ... Tuner 9 ... A / D conversion part 10 ... Synchronization part 11 ... FFT part 12 ... Demodulator 13 ... Carrier selector 14 ... Differential demodulator 15 ... SP carrier processor 16 ... Synchronous demodulator 17 ... Memory 18 ... Interpolator 19 ... Interference detector 20 ... Delay unit 21 ... Interference reducer 22, 23 ... Selector 24 ... Equalization processing section 25 ... n-stage shift register 26 ... Adder 27 ... Divider 28 ... Subtractor 29 ... Absolute value calculation circuit 30 ... Comparator

Claims (10)

An OFDM receiver comprising:
An SP carrier processing unit;
A delay unit;
Including an interference reduction department,
The SP carrier processing unit includes an SP carrier that is interpolated including an SP carrier based on a signal received by the OFDM receiver and an SP carrier other than the SP carrier obtained by interpolation of the SP carrier based on the received signal. An interpolation processing unit to generate,
An interference detector that calculates an average value of the interpolated SP carrier, and detects an interference amount at the predetermined time from the average value and an SP carrier at a predetermined time in the interpolated SP carrier; With
The delay unit delays a data carrier to be synchronously demodulated based on a signal received by the OFDM receiver, and delays a processing time of the SP carrier processing unit,
The OFDM receiver according to claim 1, wherein the interference reduction unit reduces the amount of interference from a data carrier to be synchronously demodulated output from the delay unit . A first selection circuit to which a data carrier to be synchronously demodulated output from the delay unit and a data carrier to be synchronously demodulated output from the interference reduction unit are input;
2. The OFDM receiver according to claim 1, wherein the output of the first selection circuit is switched based on a comparison between the interference amount and a threshold value. When the amount of interference does not exceed the threshold, the output of the first selection circuit selects a data carrier to be synchronously demodulated output from the delay unit, and when the amount of interference exceeds the threshold, the interference 3. The OFDM receiver according to claim 2, wherein a data carrier to be synchronously demodulated output from the reduction unit is selected. A second selection circuit;
And an equalization processing unit,
The second selection circuit switches between the interpolated SP carrier and the average value of the interpolated SP carrier based on the comparison between the interference amount and the threshold and outputs the switched SP carrier to the equalization processing unit. And
4. The OFDM receiver according to claim 2, wherein the equalization processing unit equalizes the output of the first selection circuit according to the output of the second selection circuit. 5. The output of the second selection circuit is that the interpolated SP carrier is selected when the amount of interference does not exceed the threshold, and the interpolated SP carrier when the amount of interference exceeds the threshold. The OFDM receiver according to claim 4, wherein an average value is selected. An OFDM receiver comprising:
An SP carrier processing unit;
An interference reduction department;
And an equalization processing unit,
The SP carrier processing unit includes an SP carrier that is interpolated including an SP carrier based on a signal received by the OFDM receiver and an SP carrier other than the SP carrier obtained by interpolation of the SP carrier based on the received signal. An interpolation processing unit to generate,
The average value of the interpolated SP carrier is calculated, and the average value is interpolated with the average value. An interference detection unit for detecting an interference amount at the predetermined time point from an SP carrier at a predetermined time point in the SP carrier;
The interference reduction unit reduces the amount of interference at the predetermined time from a data carrier that is synchronously demodulated based on a signal received by the OFDM receiver,
The OFDM reception apparatus, wherein the equalization processing unit performs equalization processing on the data carrier to be synchronously demodulated output from the interference reduction unit. A first selection circuit to which a data carrier for synchronous demodulation based on a signal received by the OFDM receiver and a data carrier for synchronous demodulation output from the interference reduction unit are input;
7. The OFDM receiver according to claim 6, wherein the output of the first selection circuit is switched based on a comparison between the amount of interference and a threshold value. When the amount of interference does not exceed the threshold, the output of the first selection circuit selects a data carrier to be synchronously demodulated based on the signal received by the OFDM receiver, and when the amount of interference exceeds the threshold 8. The OFDM receiver according to claim 7, wherein a data carrier to be synchronously demodulated output from the interference reduction unit is selected. A second selection circuit that switches between the interpolated SP carrier and the average value of the interpolated SP carrier based on the comparison between the interference amount and the threshold value, and outputs the second selection circuit to the equalization processing unit; 9. The OFDM receiver according to claim 7 or 8, characterized in that the OFDM receiver is included. The output of the second selection circuit is that the interpolated SP carrier is selected when the amount of interference does not exceed the threshold, and the interpolated SP carrier when the amount of interference exceeds the threshold. 10. The OFDM receiver according to claim 9, wherein an average value is selected.

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