JP3952260B2 - Bonding pads for integrated circuits - Google Patents

Bonding pads for integrated circuits Download PDF

Info

Publication number
JP3952260B2
JP3952260B2 JP2001339918A JP2001339918A JP3952260B2 JP 3952260 B2 JP3952260 B2 JP 3952260B2 JP 2001339918 A JP2001339918 A JP 2001339918A JP 2001339918 A JP2001339918 A JP 2001339918A JP 3952260 B2 JP3952260 B2 JP 3952260B2
Authority
JP
Japan
Prior art keywords
conductive film
island
bonding pad
insulators
predetermined distance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001339918A
Other languages
Japanese (ja)
Other versions
JP2002208610A (en
Inventor
受 哲 李
鐘 現 安
京 睦 孫
武 鎮 丁
善 鐘 王
在 哲 柳
憲 宗 申
恵 令 李
栄 泌 金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/745,241 external-priority patent/US6552438B2/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2002208610A publication Critical patent/JP2002208610A/en
Application granted granted Critical
Publication of JP3952260B2 publication Critical patent/JP3952260B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05085Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089Disposition of the additional element
    • H01L2224/05093Disposition of the additional element of a plurality of vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05085Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089Disposition of the additional element
    • H01L2224/05093Disposition of the additional element of a plurality of vias
    • H01L2224/05095Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05085Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089Disposition of the additional element
    • H01L2224/05093Disposition of the additional element of a plurality of vias
    • H01L2224/05096Uniform arrangement, i.e. array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Description

【0001】
【発明の属する技術分野】
本発明は集積回路及びその形成方法に係り、特に、集積回路のためのボンディングパッド及びその製造方法に関する。
【0002】
【従来の技術】
“チップ”と呼ばれる集積回路は、民生用及び業務用電子製品に広く使用されている。当業者によく知られたように、集積回路は、一般に、半導体基板などの基板及びその基板上のボンディングパッド配列を含む。前記ボンディングパッドは、集積回路の外部を集積回路の内部のマイクロ電子回路と電気的に接続させる。
【0003】
図1は、複数のボンディングパッドを含む集積回路パッケージの概略図である。図1に示されたように、集積回路100、例えば、メモリセルアレイ部110及び周辺回路部115を含むメモリ集積回路は、複数のボンディングパッド200を含む。ボンディングパッド200は、集積回路100の回路端子に対するゲートの役目をし、周辺回路部115内の入出力I/Oバッファ回路に内部的に接続される。図1に示されたように、集積回路100は、リードフレーム300に接合される。ワイヤボンディングまたは他の従来の技術が各々のワイヤ320をボンディングパッド200及びリードフレーム300の内部リードチップ310に接続するのに用いられる。
【0004】
図2は、図1のボンディングパッド200の拡大平面図である。図3は、図2に示されたボンディングパッドの斜視図である。図4は、図2のIV-IV'線に沿って切り取ったボンディングパッドの断面図である。図5は、図2のV-V'線に沿って切り取ったボンディングパッドの断面図である。
【0005】
図2ないし図5に示されたように、従来のボンディングパッドの構造において、独立的な導電性プラグ245、例えば、タングステンプラグが配線間の絶縁膜250内の複数個のビアホール240を充填している。導電性プラグ245は、下部アルミニウム配線230及び上部アルミニウム配線260を電気的に接続する。参照符号210は集積回路基板を、220は層間絶縁膜を、270はワイヤボンディング領域を各々示す。
【0006】
【発明が解決しようとする課題】
図2ないし図5に示されているパッドの構造は、下記のような問題点を有している。例えば、ウェハから良好な集積回路100を分離するソーティング(sorting)時に、ワイヤボンディング領域270上に置かれる検査器のプローブピン(図示せず)により加わる力により配線間絶縁膜250に亀裂が生じる。亀裂330はまた、ワイヤボンディング領域270にワイヤ320をボンディングする間に加わる機械的な衝撃及び圧力により生じるストレスによっても配線間絶縁膜250内に生じる。
【0007】
亀裂は、相対的に軟性である上部アルミニウム配線260及び下部アルミニウム配線230がソーティングまたはワイヤボンディング時に加わるストレスにより変形されて生じる。しかし、相対的に硬い配線間絶縁膜250は容易に変形されない。このため、一定値以上のストレスが加わると、不安定なタングステンプラグ245が抜けてしまうか、或いは配線間絶縁膜250に亀裂が生じる。このような亀裂は、図5に示されたように、タングステンプラグ245を覆っている絶縁膜250の内部に伝播される。
【0008】
配線間絶縁膜250に生じた亀裂は、上部及び下部アルミニウム配線260,230が剥がれてしまう配線オープンの問題を引き起こす。あるいは、ワイヤ320と上部アルミニウム配線260との間の接触が不良となって、ワイヤ320が上部アルミニウム配線260から剥がれるパッドオープンの問題が生じる。
【0009】
図6は、配線間絶縁膜の亀裂を低減させ、しかも、配線膜またはワイヤが剥がれることを低減させるためにタングステンプラグ245を中央のワイヤボンディング領域の外部の周辺領域に限って形成した従来の他のボンディングパッド構造の平面図である。図7は、図6のVII-VII'線に沿って切り取ったボンディングパッド構造の断面図である。このようなボンディングパッドの構造は、米国特許第5,248,903及び第5,502,337号に開示されている。
【0010】
図6及び図7と前記二つの特許によるボンディングパッドの構造は、配線間絶縁膜250の亀裂をある程度低減できる。しかし、タングステンプラグ245の数が減少するため、タングステンプラグ245と上部アルミニウム配線膜260との間の付着力が弱い。その結果、ワイヤボンディング時に上部アルミニウム配線膜260が割れる配線オープン現象が頻繁に生じる。また、プラグの数が減少するため、上部アルミニウム配線膜260との接触面積が縮まり、その結果、抵抗Rsが増え、電流が減少する。このため、十分な量の電流を集積回路内のスイッチング素子に供給できず、これは、素子の動作を劣化させる原因となる。
【0011】
本発明は上記事情に鑑みてなされたものであり、その目的は、チップ分類及びワイヤボンディング時に配線間絶縁膜内の亀裂を最小化しつつ十分な量の電流をチップ内に供給でき、しかも写真食刻工程時に回折される光の量を低減できるほか、検査プローブによる反復的な接触により上部配線が上部導電性プラグから剥がれる現象を低減できることから、集積回路の信頼性を向上させることができる集積回路のためのボンディングパッド構造を提供することにある。
【0012】
本発明の他の目的は、配線間絶縁膜内の亀裂を最小化しつつ十分な量の電流をチップ内に供給でき、しかも写真食刻工程時に回折される光の量を低減できるほか、検査プローブによる反復的な接触により上部配線が上部導電性プラグから剥がれる現象を低減できることから、集積回路の信頼性を向上させることができるボンディングパッド構造を製造するのに好適な方法を提供することにある。
【0013】
【課題を解決するための手段】
本発明による集積回路のためのボンディングパッドは、所定距離離隔された第1導電膜及び第2導電膜と、前記所定距離離隔された第1導電膜及び第2導電膜間に存在し、前記所定距離離隔された第1導電膜及び第2導電膜に電気的に接続された連続的な第3導電膜と、前記連続的な第3導電膜内に存在し、前記連続的な第3導電膜を貫通するように延びてその側壁が前記連続的な第3導電膜により覆われた非整列で、かつ所定距離離隔された島状絶縁体の配列とを含む。
【0014】
前記配列は非整列で、かつ所定距離離隔された島状絶縁体の横配列及び非整列で、かつ所定距離離隔された縦配列を含みうる。前記非整列で、かつ所定距離離隔された島状絶縁体の配列は、第1方向の第1エッジを有する第1島状絶縁体と、前記第1方向の第1島状絶縁体に隣接し、第1エッジと非整列とされた第1方向の第2エッジを有する第2島状絶縁体とを含みうる。
【0015】
前記ボンディングパッドは、前記連続的な第3導電膜及び前記第2導電膜間に存在し、前記連続的な第3導電膜及び前記第2導電膜に電気的に接続された連続的な第4導電膜をさらに含みうる。所定距離離隔された島状絶縁体の第2配列は前記連続的な第4導電膜内に存在し、前記連続的な第4導電膜を貫通するように延びて前記島状絶縁体の側壁が前記第4導電膜により覆われており、前記所定距離離隔された島状絶縁体の第2配列は前記非整列で、かつ所定距離離隔された島状絶縁体の第1配列と非整列とされている。
【0016】
前記ボンディングパッドは、前記第1導電膜上の金属バンパ層及びワイヤとボンディングするために形成された前記金属バンパ層上の上部ボンディングパッド層をさらに含みうる。前記金属バンパ層は、タングステンでありうる。前記金属バンパ層は、約4,000Åの厚さを有しうる。前記金属バンパ層及び前記上部ボンディングパッド層は、約12,000Åないし14,000Åの範囲の厚さを有する単一層よりなりうる。前記上部ボンディングパッド層は、前記金属バンパ層の真上にありうる。
【0017】
前記金属バンパ層は、該金属バンパ層の外部エッジ側に位置した島状絶縁体を含みうる。前記金属バンパ層の内部領域には、島状絶縁体がない。
【0018】
本発明によるボンディングパッドの構造は、所定距離離隔された第1導電膜及び第2導電膜と、前記所定距離離隔された第1導電膜及び第2導電膜間に存在し、前記所定距離離隔された第1導電膜及び第2導電膜に電気的に接続された連続的な第3導電膜とを含みうる。前記ボンディングパッドの構造は、前記連続的な第3導電膜内にジグザグ状に配列され、前記連続的な第3導電膜を貫通するように延びてその側壁が前記連続的な第3導電膜により覆われた所定距離離隔された島状絶縁体の配列をさらに含みうる。
【0019】
本発明による集積回路のためのボンディングパッドの製造方法は、先ず、集積回路基板上に下部導電膜を形成する。次に、前記下部導電膜上に前記下部導電膜に電気的に接続される連続的な導電膜を形成する。前記連続的な導電膜は、その内部に前記連続的な導電膜を貫通するように延びて島状絶縁体の側壁が前記連続的な導電膜により覆われている非整列の所定距離離隔された島状絶縁体の配列を含む。次に、前記連続的な導電膜上に前記連続的な導電膜に電気的に接続される上部導電膜を形成する。
【0020】
前記連続的な導電膜を形成する段階は、非整列の所定距離離隔された島状絶縁体の横配列を含む連続的な導電膜を形成する段階を含みうる。前記連続的な導電膜を形成する段階は、非整列の所定距離離隔された島状絶縁体の横配列及び非整列の所定距離離隔された島状絶縁体の縦配列を含む連続的な導電膜を形成する段階を含みうる。
【0021】
前記連続的な導電膜を形成する段階は、前記連続的な導電膜内に第1方向の第1エッジを有する第1島状絶縁体を形成する段階と、前記第1方向の前記第1島状絶縁体に隣接し、第1エッジと非整列とされた第1方向の第2エッジを有する第2島状絶縁体を前記連続的な導電膜内に形成する段階とを含みうる。
【0022】
【発明の実施の形態】
以下、添付した図面に基づき、本発明の望ましい実施形態を説明することにより本発明を詳細に説明する。しかし、本発明は以下に開示される実施形態に限定されることなく、相異なる各種の形態に具現できる。本実施形態は単に本発明の開示を完全たるものにし、かつ通常の知識を有した者に本発明の範ちゅうを完全に知らせるために提供される。添付した図面において、各種の膜及び領域の厚さは明瞭性のために強調されている。また、ある膜が他の膜または基板上に存在すると記載されるとき、ある膜が他の膜または基板の真上にあることもあれば、それらの間に層間膜が存在することもある。図中、同一の参照符号は、同一の要素を表わす。
【0023】
図8は、本発明の第1実施形態によるボンディングパッド構造の平面図であり、図9は、図8に示されたボンディングパッド構造の斜視図であり、図10は、図8のX-X'線に沿って切り取ったボンディングパッド構造の断面図であり、図11は、図8のXI-XI'線に沿って切り取ったボンディングパッド構造の断面図である。
【0024】
図8において、参照番号920は下部配線を、925Iは下部島状絶縁体を、930は下部一体型導電性プラグを、940は中間配線を各々表わす。参照番号945Iは上部島状絶縁体を、950は上部一体型導電性プラグを、960は最上部配線を、970はワイヤボンディング領域を各々表わす。参照番号925及び945は下部及び上部一体型導電性プラグパターンの外壁を覆っている層間絶縁膜を各々表わす。一体型導電性プラグはまた、連続的な導電膜と呼ばれうる。配線は導電膜と呼ばれ、島状絶縁体は絶縁島と呼ばれる。“上部”/“下部”及び“上”/“下”などの用語は絶対的な方向を表わすのではなく、集積回路基板から隣接しているか、或いは離れているかの相対的な関係を表わすものである。
【0025】
図9、図10及び図11を参照すれば、集積回路基板900上に層間絶縁膜910が形成されており、層間絶縁膜910上に下部配線920、中間配線940及び最上部配線960を含む3層配線を有するボンディングパッド構造が形成されている。最上部配線960は、ワイヤ990がボンディングされるワイヤボンディング領域970を備える。ワイヤ990は、周辺回路を構成する入出力バッファ回路(図1の115参考)などと接続された回路端子のゲートの役目を果たしうる。
【0026】
最上部配線960の下面と中間配線940の上面との間に上部一体型導電性プラグ950が配されて、最上部配線960と中間配線940とを電気的に接続させている。上部一体型導電性プラグ950内には一体型導電性プラグによりその側壁が完全に覆われ、最上部配線960及び中間配線940により上面及び下面が覆われている少なくとも一つ以上の上部島状絶縁体945Iが形成されている。図示されたような上部島状絶縁体945Iのアレイが望ましい例として形成される。
【0027】
上部島状絶縁体945Iの数及び/又は大きさは上部一体型導電性プラグ950と最上部配線960とが接触する面積を最上部配線960の面積の10%以上にできる範囲内で決定する。接触面積を10%以上にすることにより、一定値以上の電流をボンディングパッド部に流しうる。望ましくは、離隔された島状絶縁体の配列とも呼ばれる複数個の島状絶縁体945Iは島状絶縁体945Iの幅を縮める。すなわち、最上部配線960と中間配線940との間に挟まれる絶縁膜は、上部一体型導電性プラグ950内に複数個の島状絶縁体945Iに区画される。このため、もし、一つの島状絶縁体945Iに亀裂が生じたとしても、残りの島状絶縁体945Iは亀裂されない。一般に、ボンディングパッドとして機能する最上部配線960は四角形であり、100μm×100μmの大きさを有する。上部島状絶縁体945I間の間隔は、望ましくは、約0.3μmないし10μmにする。特に、複数個の島状絶縁体945Iは上部一体型導電性プラグ950が篩状に形成され、このため、島状絶縁体945Iが所定値以上のストレス下でも亀裂されないようにマトリックス状に配される。
【0028】
中間配線940と下部配線920との間の接続構造も、中間配線940と最上部配線960との間の接続構造と同一に構成する。すなわち、少なくとも一つ以上の下部島状絶縁体925Iを内在した下部一体型導電性プラグ930により中間配線940及び下部配線920を電気的に接続させる。
【0029】
前述したボンディングパッドの構造は、本発明の第1実施形態による3層配線である。しかし、前記ボンディングパッドの構造は最上部配線960及び中間配線940を含む2層配線または多層配線でありうる。
【0030】
本発明の第1実施形態によるボンディングパッドの構造の効果を最上部配線960及び中間配線940を接続させる構造を参照して述べる。本発明によるボンディングパッドの構造は、最上部配線(図3の260参照)及び最下部配線(図3の230参照)が一体型絶縁膜(図3の250参照)により絶縁され、絶縁膜250内の独立的な複数個の導電性プラグ(図3の245参照)が最上部配線260及び最下部配線230を接続させる従来のボンディングパッド構造とは完全に逆の構造を採用している。すなわち、本発明によれば、最上部配線960及び中間配線940を接続させる導電性プラグ950は連続的な導電性プラグよりなっており、最上部配線960と中間配線940との間に挟まれる絶縁膜のほとんどが一体型導電性プラグ950内に少なくとも一つ以上の島状絶縁体945Iに区画される。
【0031】
島状絶縁体945Iは、一体型導電性プラグ950により側壁が完全に覆われており、配線960,940により上面及び下面が覆われているので、極めて安定した構造を有している。このため、チップ分類及び/又はワイヤボンディング時に一定の機械的なストレスが加わるとしても、島状絶縁体945Iには亀裂が生じない。また、島状絶縁体945Iに亀裂が生じるとしても、亀裂が隣接した島状絶縁体945Iには伝播されない。
【0032】
図12は、本発明の第2実施形態によるボンディングパッド構造の平面図であり、図13は、図12に示されたボンディングパッド構造の斜視図であり、図14は、図12のXIV-XIV'線に沿って切り取ったボンディングパッド構造の断面図であり、図15は、図12のXV-XV'線に沿って切り取ったボンディングパッド構造の断面図である。
【0033】
図12ないし図15を参照すれば、第2実施形態において、中間配線940'は連続的な板状に形成されるのではなく、上部及び下部一体型導電性プラグ950,930のように島状絶縁体935Iを含む。このため、中間配線内の島状絶縁体は上部及び下部一体型導電性プラグ950,930内の島状絶縁体と重複される。望ましくは、上部一体型導電性プラグ950内の島状絶縁体945I及び下部一体型導電性プラグ930内の島状絶縁体925Iが中間配線940'内の島状絶縁体935Iに接続されて一つの島状絶縁体Iを構成する。上部及び下部一体型導電性プラグ950,930内の島状絶縁体945I,925I及び中間配線940'内に内在した島状絶縁体935Iが接続されて一つの島状絶縁体Iを構成する場合、島状絶縁体Iの厚さが3つの絶縁体925I,935I,945Iの厚さの合計となるので、ストレスに対する耐性が大きくなる。
【0034】
図16は、本発明の第3実施形態によるボンディングパッド構造の平面図である。
図16を参照すれば、第3実施形態において、複数個の島状絶縁体925I,945Iはジグザグ状の配列であって、交互に形成される。
【0035】
図17は、本発明の第4実施形態によるボンディングパッド構造の平面図である。
図17を参照すれば、第4実施形態において、島状絶縁体945I',925I'は円柱状である。また、島状絶縁体は三角柱または五角柱のように、各種の多角柱状に形成できる。
【0036】
図18は、本発明の第5実施形態によるボンディングパッド構造の平面図である。
図18を参照すれば、第5実施形態において、一体型導電性プラグ930',950'は最上部配線のワイヤボンディング領域970により覆われた領域の外部の周辺領域の下部に限って形成され、絶縁体929,949は中央のワイヤボンディング領域970の下部に形成される。この第5実施形態によれば、ワイヤボンディング領域970の下部には亀裂の発生地として機能するプラグが形成されていないため、絶縁体929,949に亀裂が生ぜず、ワイヤボンディング領域の周りの領域の下部に形成された一体型導電性プラグ930',950'により最上部配線960との所定の接触面積が確保される。
【0037】
図19は、本発明の第6実施形態によるボンディングパッド構造の平面図である。
図19を参照すれば、第6実施形態において、一体型導電性プラグ930',950'の内部に形成される島状絶縁体925I',945I'は帯状である。
【0038】
図20を参照して、本発明の第1実施形態によるボンディングパッド構造(図9参照)を形成する方法について述べる。
先ず、中間配線940及び最上部配線960を形成する段階を述べる。下地層910,920,930が形成されている集積回路基板900上に中間配線940を形成する(ステップ2000)。次に、中間配線940上に配線間絶縁膜945を形成する(ステップ2010)。配線間絶縁膜945は中間配線940上に絶縁物を堆積した後、これをエッチバック及び/又は化学機械的研磨工程により平坦化して形成する。
【0039】
次に、上部一体型導電性プラグが形成される領域を限定するマスクを使って配線間絶縁膜945をパターニングする(ステップ2020)。これにより、中間配線940が部分的に露出され、少なくとも一つ以上の島状絶縁体945Iを限定する連続的なトレンチが形成される。
【0040】
複数個の島状絶縁体945Iは、望ましくは、マトリックス状にまたはジグザグ状に配列されるようにパターニングする。島状絶縁体945I間の間隔、すなわち、トレンチの幅は約0.3μmないし10μmとする。0.3μmまたはそれ以上の間隔に形成する理由は、一つの島状絶縁体945Iで生じた亀裂が他の島状絶縁体945Iに伝播されないようにするためである。また、10μmまたはそれ以下の間隔に形成する理由は、島状絶縁体間のトレンチを導電性プラグにより十分に充填するためである。
【0041】
次に、導電物質、例えば、タングステン、銅またはアルミニウムなどを使ってトレンチを充填する導電膜を形成する(ステップ2030)。続いて、トレンチを充填する導電膜をエッチバック及び/又は化学機械的研磨工程により平坦化して島状絶縁体945Iの側壁を覆う上部一体型導電性プラグ950を完成させる(ステップ2040)。上部一体型導電性プラグ950の上面の総面積は、望ましくは、形成される最上部配線960の面積の10%以上にする。
【0042】
また、他の方法としては、まず下部の導電膜と電気的に接続される固体導電膜を前記下部の導電膜上に形成する。次に、前記固体導電膜をエッチングして、固体導電膜を貫通し、互いに所定距離離隔された複数個のビアを形成する。次に、絶縁膜を前記固体導電膜上に、そして前記ビア内に形成する。最後に、前記絶縁膜をエッチバック及び/又は化学機械的研磨により前記固体導電膜上から除去し、前記絶縁膜をビア内に残留させる。
【0043】
図20の説明を続ければ、上部一体型導電性プラグ950の上面にボンディングパッドとして機能する最上部配線960を形成する(ステップ2050)。次に、最上部配線960上を含む全面にパッシベーション膜980を形成する(ステップ2060)。このパッシベーション膜980は、望ましくは、水分を浸透させず、ストレスに耐性があり、段差塗布性が大きく、さらに、均一に形成できる膜から形成する。続いて、パッシベーション膜980をパターニングして最上部配線960のワイヤボンディング領域970を露出させる(ステップ2070)。
【0044】
中間配線940の下部層、すなわち、下部配線920及び下部一体型導電性プラグ930を形成する方法は、ステップ2000(配線形成段階)ないしステップ2040(一体型導電性プラグ及び島状絶縁体の形成段階)の工程と同様にして、中間配線940の形成段階前に行われる。下部層状構造を形成する段階を繰り返し行うことにより、多層配線構造のボンディングパッドの構造を形成できるのは言うまでもない。
【0045】
第2実施形態によるボンディングパッド構造(図13及び図14参照)の製造方法の場合、中間配線940'は上部及び下部一体型導電性プラグ950,930と同一の形態に形成する。すなわち、ステップ2000ないし2040を通じて下部島状絶縁体925Iを内在した下部一体型導電性プラグ930を形成した後、ステップ2010ないしステップ2040を同一に行い、下部一体型の導電性プラグ930と部分的に重複する中間島状絶縁体935Iを内在した一体型の中間配線940'を形成する。上部一体型導電性プラグ950及び最上部配線960の形成段階は、第1実施形態の方法と同様にして行う。望ましくは、下部、中間及び上部島状絶縁体925I,935I,945Iが一つに接続されるように形成する。
【0046】
本発明は下記の実験例を参考としてより詳細に説明されるが、この実験例が本発明を制限することはない。
<実験例1>
本発明によるボンディングパッド構造を有する第1試料を用意した。すなわち、基板上に4層のアルミニウム配線を形成し、約3.4μm間隔に離隔された島状絶縁体が内在した一体型タングステンプラグを各配線間に形成し、各配線を電気的に接続させた。最上部配線上にパッシベーション膜を形成した後、これをパターニングしてワイヤボンディング領域を露出させた。次に、ウェッジ方法によりワイヤをボンディングして試料を用意した。
【0047】
ボンディングパッド構造を完成した後、ワイヤ引き強度測定装置を用い、ワイヤ引き強度を測定した。
本発明によるボンディングパッド構造を有する第1試料の数は170である。また、図3に示されているような従来のボンディングパッドを有する第1対照試料197個及び図7に示されたような従来のボンディングパッド構造を有する第2対照試料170個を各々用意した。対照試料に対しても同一の方法によりワイヤ引き強度を測定した。
【0048】
測定結果を下記表1及び図21に示す。図21において、-○-にてプロットされたグラフは本発明によるボンディングパッド(第1試料)のワイヤ引き強度を、-△-にてプロットされたグラフは従来のボンディングパッド(第1対照試料)のワイヤ引き強度を、-□-にてプロットされたグラフは他の従来のボンディングパッド(第2対照試料)のワイヤ引き強度を各々表わす。累積分布(%)は引張り力を0g重から10g重まで増やしつつ、ワイヤが剥がれる試料の数を百分率にて示した値である。表1において、累積分布は引き強度6g重以下の値でワイヤが分離された試料の数を百分率にて示した値である。
【0049】
【表1】

Figure 0003952260
表1及び図21の結果から、本発明によるパッドが従来のパッドよりもワイヤ引き強度が大きいということが分かる。
【0050】
<実験例2>
実験例1の方法と同様にして形成した第1試料と第1及び第2対照試料を対象として、ワイヤと、ボンディングパッドとして機能するアルミニウム配線間の接触が不良なためにワイヤが剥がれるパッドオープン現象及びボンディング時に配線膜が剥がれる配線オープン現象を各々測定した。さらに、パッドオープン及び配線オープンを測定した後、第1試料158個、第1対照試料140個及び第2対照試料142個に対して最上部アルミニウム配線下部の島状絶縁体または配線間絶縁膜で生じる亀裂の数を測定した。亀裂の数は各試料のパッシベーション膜及び最上部アルミニウム配線を適切なエッチング液を使って除去した後、走査電子顕微鏡を使って測定した。その結果を下記表2及び図22に示す。
【0051】
【表2】
Figure 0003952260
【0052】
表2及び図22を参照すれば、従来のパッド構造を採用した第1対照試料及び第2対照試料では亀裂が多数生じたのに対し、本発明によるパッド構造を採用した第1試料では亀裂が全く生じなかった。また、亀裂が生じなかったため、第1試料では配線オープン現象も見られず、パッドオープン現象の頻度も従来のパッド構造に比べて著しく減った。
【0053】
本発明のボンディングパッド構造によれば、最上部配線及び最上部配線下部の配線が連続的な導電性プラグにより連結されるため、所定大きさ以上の接触面積を確保できる。このため、十分な量の電流をボンディングパッド構造内に伝達できる。
【0054】
また、最上部配線と下部配線との間の絶縁膜が一体型導電性プラグ内に閉じ込められた島状絶縁体から形成される。このため、チップ分類のためにプローブピンが置かれるとき、またはワイヤがボンディングされるときに加わる物理的なストレスにより絶縁体内に亀裂が生じることが減る。しかも、絶縁体が島状に形成されるので、周りの他の絶縁体に亀裂が伝播されることが防止される。
【0055】
図8ないし図11を参照すれば、本発明による各種の実施形態において、複数の島状絶縁体945Iが一列に配列され、上部一体型導電性プラグ950が篩パターンとなっている。この上部一体型導電性プラグ950の篩配列は、上部一体型導電性プラグ950及び島状絶縁体945Iの間にストレスがあっても、不安定な上部一体型導電性プラグ950がずれる可能性を低める。したがって、所定値以上のストレス下でも島状絶縁体945Iに亀裂が生じない。あるいは、亀裂が生じても、他の島状絶縁体945Iに亀裂が伝播されない。
【0056】
図8に示される島状絶縁体945I間の間隔D1は他の島状絶縁体945Iへの亀裂の伝播有無及び製造工程条件を考慮して決定される。すなわち、島状絶縁体945I間の間隔D1は一つの島状絶縁体945Iで生じた亀裂が他の島状絶縁体945Iに伝播されないように十分に大きい必要がある。また、島状絶縁体945Iを先に形成し、これらの間及び上部にタングステンなどの導電物質を形成した後、この導電物質を平坦化して上部一体型導電性プラグ950を形成する本発明による実施形態において、島状絶縁体945Iが前記導電物質により完全に取り囲まれるように島状絶縁体945I間の最大の間隔は製造工程中に形成される導電物質の厚さの2倍以下となることが望ましい。
【0057】
上部島状絶縁体945I間の間隔D1は0.3μmないし10μm程度にすることが望ましい。上部一体型導電性プラグ950を形成するために使用される導電物質が0.4μmないし1μm程度の厚さを有する本発明による実施形態において、上部島状絶縁体945I間の間隔は0.3μmないし2μm程度にすることが望ましい。一般に、最上部配線960はボンディングパッドとして機能し、四角形で約100μm×100μmの大きさである。
【0058】
図23ないし図26は本発明のさらに他の実施形態として、非整列の所定距離離隔された島状絶縁体の配列を示した平面図である。図23及び図24に示された実施形態では、横配列の島状絶縁体が互いに非整列とされているか、またはオフセットされている。このため、島状絶縁体の頂点の部分が2つずつだけ互いに隣接されている。互いに隣接した島状絶縁体の頂点の部分またはエッジ数を減らすことにより、写真エッチング工程時に回折される光の量を減らしうる。
【0059】
本発明による他の実施形態として、縦配列の島状絶縁体が互いに非整列とされているか、またはオフセットされている場合がある。さらに、横及び縦配列両方の島状絶縁体が非整列とされている場合もある。隣接する横配列及び/又は縦配列は例えば半距離だけ互いにオフセットされている。1つおきに横配列及び/又は縦配列は整列されており、隣接する横配列及び/又は縦配列はその間が半距離だけ非整列であるか、或いはオフセットされている。他の間隔を使用できることもちろんである。
【0060】
本発明によるさらに他の実施形態として、島状絶縁体のエッジが例えば図25に示されたように非整列とされている場合がある。図25に示されたように、非整列配列の横方向のエッジ2501〜2506は隣接するエッジ同士が非整列となっている。非整列のエッジ2501〜2506は写真エッチング工程中に回折される光の量を一層低減できる。縦方向のエッジが非整列とされている場合もある。
【0061】
図26に示されたように、横方向及び縦方向両方のエッジ2601〜2609が互いに非整列とされている場合がある。特に、非整列配列の横方向のエッジ2601〜2605は互いに対して非整列であり、非整列配列の縦方向のエッジ2606〜2609も互いに対して非整列である。横及び縦方向共に非整列であるエッジは写真エッチング工程中に回折される光の量をより一層低減できる。
【0062】
本発明の図25及び図26による実施形態と違って、図8において例として説明した島状絶縁体の横配列及び縦配列は整列されている。このように整列された配列においては、島状絶縁体の4つの頂点が互いに隣接している。したがって、写真エッチング工程において、島状絶縁体の各頂点で生じる回折が重複されて頂点に当たるパターン部を丸めて島状絶縁体の臨界値を変える。したがって、島状絶縁体を取り囲む導電膜の厚さは、島状絶縁体を導電膜により完全に取り囲むために厚い必要がある。要するに、図8の配列においては、4つの頂点が互いに隣接されているため、一層多くの回折が引き起こされ、これは不明確なエッジを作る。
【0063】
上部島状絶縁体945I及び下部島状絶縁体925Iは相互で非整列とされている場合がある。例えば、上部島状絶縁体945Iは図23に示されたように非整列で配列され、下部島状絶縁体925Iは例えば図8に示されたように整列配列される。
【0064】
再び図24を参照すれば、検査器のプローブピンがワイヤボンディング領域970に横方向に置かれる場合、検査器のプローブピンにより加わる力は下部及び上部一体型導電性プラグ930,950に沿って連続的に伝播され、上部及び下部島状絶縁体945I,925Iにより遮断される。したがって、プローブピンの力(すなわち、せん断力)に対する抵抗が例えば、図8に示された整列された配列の抵抗に比べて増える。望ましくは、島状絶縁体間の間隔D2は一つの島状絶縁体で生じた亀裂が他の島状絶縁体に伝播できない程度に十分大きくする。島状絶縁体間の最大の間隔は、望ましくは、下部及び上部一体型導電性プラグを形成するための導電物質の厚さの2倍以下にする。
【0065】
この実施形態において、固体中間配線940を図10に示すように板状に形成でき、または図14に示すように、島状絶縁体が内在するようにも形成できる。したがって、固体中間配線940は上部及び下部一体型導電性プラグ950,930と重複され、さらに図14の固体中間配線940'である場合は上部及び下部一体型導電性プラグ950,930と一致する。
【0066】
本発明によるさらに他の実施形態として、ボンディングパッドは図27に示されたように金属バンパ層2700を含みうる。金属バンパ層2700は絶縁物質2745により取り囲まれた導電性プラグ2750上に形成された上部配線2760上にある。上部ボンディングパッド層2705は金属バンパ層2700上に形成される。上部ボンディングパッド層2705は金属バンパ層2700の真上にある。
【0067】
製造時に、検査プローブは集積回路の部分が検査可能のように上部ボンディングパッド層2705と繰り返し接触する。その後、ワイヤが例えば、図10に示されたように、上部ボンディングパッド層2705にボンディングされる。金属バンパ層2700は検査プローブの反復的な接触が上部導電性プラグ2750と上部配線2760との間の機械的な結合を減少させる可能性を減らす。したがって、この実施形態は検査プローブによる反復的な接触の結果として上部配線2760が上部導電性プラグ2750から剥がれる可能性を減らすことにより、集積回路の信頼性を向上できる。
【0068】
従来のボンディングパッド構造において、検査プローブは上部導電性プラグ及び絶縁物質の部分が露出されるように上部配線に食い込む。したがって、ボンディングパッドにワイヤをボンディングするのに使用されるソルダは十分なボンディング接着力を与えない露出された絶縁物質と接触し、上部配線は上部導電性プラグから剥がれる。
【0069】
本発明によるボンディングパッド構造は、第1絶縁膜2710上に下部配線2740を形成することにより製造できる。下部配線2740はアルミニウムまたは銅などの金属でありうる。もちろん、他の金属も使用できる。下部配線2740がパターニングされ、酸化膜などの第2絶縁膜2745がその上部に形成される。第2絶縁膜2745はその内部にビアを形成するためにパターニングされる。上部導電性プラグ2750はエッチバック工程または化学機械的研磨(CMP)を利用してビア内に形成される。上部導電性プラグ2750はタングステン(W)、アルミニウム(Al)、銅(Cu)などの導電物質でありうる。もちろん、他の導電物質も使用できる。TiまたはTiNなどのバリア層(図示せず)を下部配線2740と第2絶縁膜2745との間に蒸着することもできる。
【0070】
第2配線2760は第2絶縁膜2745及び上部導電性プラグ2750上に形成される。金属バンパ層2700は、図27に示されたように、エッチバック工程、または図28に示されたように、化学機械的研磨(CMP)を利用して第2配線2760上に形成される。金属バンパ層2700は400Å程度の厚さでありうる。金属バンパ層2700は集積回路の内部領域のプラグと同時に形成できる。上部ボンディングパッド層2705は8,000Åないし10,000Å程度の厚さで金属バンパ層2700上に形成できる。金属バンパ層2700及び上部ボンディングパッド層2705の結合厚さは12,000Åないし14,000Å程度の範囲にある。図28に示されたように、金属バンパ層2700及び上部ボンディングパッド層2705の厚さはエッチバック工程または化学機械的研磨(CMP)を補償するように調節できる。
【0071】
金属バンパ層2700はタングステンを含む。もちろん、他の金属も使用できる。金属バンパ層2700はまた、図8ないし図22及び図23ないし図26を参照して説明した本発明による所定距離離隔された島状絶縁体及び一体型導電性プラグを含むボンディングパッド構造として形成できる。
【0072】
図29は、本発明による島状絶縁体2905が内在された金属バンパ層2900を有するボンディングパッド構造の実施形態を説明する断面図である。図29に示されたように、島状絶縁体2905は金属バンパ層2900内に位置され、外部エッジ側に位置する。したがって、金属バンパ層2900の内部領域は外部エッジ側に位置する島状絶縁体2905よりも少数の島状絶縁体2905を有する。ある具体例においては、金属バンパ層2900の内部領域には島状絶縁体2905がない。したがって、本発明による実施形態は金属バンパ層2900の内部領域に加わったストレスにより敏感ではなく、このため、接着が緩む可能性はほとんどない。
【0073】
図30は、本発明による金属バンパ層3000を有するボンディングパッド構造の他の実施形態を説明する断面図である。図30に示されたように、第2導電膜3010及び上部導電性プラグ3020はダマシン工程を利用して形成される。また、金属バンパ層3000及び上部ボンディングパッド層3005は12,000Åないし14,000Å程度の範囲の厚さを有する単一層で形成される。
【0074】
【発明の効果】
以上述べたように、本発明のボンディングパッド構造によれば、最上部配線と最上部配線下部の配線が連続的な導電性プラグにより連結されるため、所定大きさ以上の接触面積を確保できる。このため、十分な量の電流をボンディングパッド構造内に伝達できる。
【0075】
また、最上部配線と下部配線との間の絶縁膜は一体型導電性プラグ内に閉じ込められた島状絶縁体から形成される。したがって、チップ分類のためにプローブピンが置かれるとき、またはワイヤがボンディングされるときに加わる物理的なストレスにより絶縁体内に亀裂が生じることが減る。しかも、絶縁体が島状に形成されるため、周りの他の絶縁体に亀裂が伝播されることも防止される。
【0076】
上部一体型導電性プラグは一具体例では複数個の島状絶縁体が一列に配列され、篩の形となっている。したがって、上部一体型導電性プラグと島状絶縁体との間にストレスがあっても、上部一体型導電性プラグの篩配列は不安定な上部一体型導電性プラグが剥がれる可能性を減らす。このため、所定値以上のストレス下でも島状絶縁体に亀裂が生じない。あるいは、亀裂が生じても、他の島状絶縁体に亀裂が伝播されない。
【0077】
一方、横配列及び/又は縦配列の島状絶縁体は一具体例では互いに非整列とされているか、或いはオフセットされており、このとき、島状絶縁体の頂点の部分が2つずつだけ互いに隣接されている。したがって、互いに隣接した島状絶縁体の頂点の部分またはエッジの数を減らすことにより、写真エッチング工程時に回折される光の量を低減できる。
【0078】
ボンディングパッドは金属バンパ層を含みうるが、金属バンパ層は検査プローブの反復的な接触によって上部導電性プラグと上部配線との間の機械的な結合が低減することを減らす。このため、本発明は検査プローブによる反復的な接触の結果として上部配線が上部導電性プラグから剥がれることを減らすことにより、集積回路の信頼性を向上できる。
【0079】
また、本発明は島状絶縁体が内在された金属バンパ層を有するボンディングパッド構造でありうるが、島状絶縁体が内在された金属バンパ層を有するボンディングパッド構造は金属バンパ層の内部領域に加わったストレスにより敏感ではなく、このため、接着が緩む可能性はほとんどない。
【図面の簡単な説明】
【図1】リードフレームに接合された集積回路の概略図である。
【図2】図1に示された従来のボンディングパッド構造の拡大平面図である。
【図3】図2に示されたボンディングパッド構造の斜視図である。
【図4】図2のIV-IV'線に沿って切り取ったボンディングパッド構造の断面図である。
【図5】図2のV-V'線に沿って切り取ったボンディングパッド構造の断面図である。
【図6】従来の他のボンディングパッド構造の平面図である。
【図7】図6のVII-VII'線に沿って切り取ったボンディングパッド構造の断面図である。
【図8】本発明の第1実施形態によるボンディングパッド構造の平面図である。
【図9】図8に示されたボンディングパッド構造の斜視図である。
【図10】図8のX-X'線に沿って切り取ったボンディングパッド構造の断面図である。
【図11】図8のXI-XI'線に沿って切り取ったボンディングパッド構造の断面図である。
【図12】本発明の第2実施形態によるボンディングパッド構造の平面図である。
【図13】図12に示されたボンディングパッド構造の斜視図である。
【図14】図12のXIV-XIV'線に沿って切り取ったボンディングパッド構造の断面図である。
【図15】図12のXV-XV'線に沿って切り取ったボンディングパッド構造の断面図である。
【図16】本発明の第3実施形態によるボンディングパッド構造の平面図である。
【図17】本発明の第4実施形態によるボンディングパッド構造の平面図である。
【図18】本発明の第5実施形態によるボンディングパッド構造の平面図である。
【図19】本発明の第6実施形態によるボンディングパッド構造の平面図である。
【図20】本発明によるボンディングパッド構造の製造方法を示すブロック図である。
【図21】本発明によるボンディングパッド構造にボンディングされたワイヤの引き強度を従来のボンディングパッドと比較して示した特性図である。
【図22】本発明によるボンディングパッド構造におけるパッドオープン及び配線オープンを従来のボンディングパッド構造と比較して示した特性図である。
【図23】本発明による非整列の所定距離離隔された島状絶縁体の配列を含むボンディングパッド構造の実施形態を説明する平面図である。
【図24】本発明による非整列の所定距離離隔された島状絶縁体の配列を含むボンディングパッド構造の実施形態を説明する平面図である。
【図25】本発明による非整列の所定距離離隔された島状絶縁体の配列を含むボンディングパッド構造の実施形態を説明する平面図である。
【図26】本発明による非整列の所定距離離隔された島状絶縁体の配列を含むボンディングパッド構造の実施形態を説明する平面図である。
【図27】本発明による金属バンパ層を含むボンディングパッド構造の実施形態を説明する断面図である。
【図28】本発明による金属バンパ層を含むボンディングパッド構造の実施形態を説明する断面図である。
【図29】本発明による金属バンパ層を含むボンディングパッド構造の実施形態を説明する断面図である。
【図30】本発明による金属バンパ層を含むボンディングパッド構造の実施形態を説明する断面図である。
【符号の説明】
920 下部配線
930 下部一体型導電性プラグ
940 中間配線
950 上部一体型導電性プラグ
960 最上部配線
925I 下部島状絶縁体
945I 上部島状絶縁体
925,945 層間絶縁膜
970 ワイヤボンディング領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit and a method of forming the integrated circuit, and more particularly to a bonding pad for an integrated circuit and a method of manufacturing the same.
[0002]
[Prior art]
Integrated circuits called “chips” are widely used in consumer and commercial electronic products. As is well known to those skilled in the art, an integrated circuit generally includes a substrate, such as a semiconductor substrate, and a bonding pad array on the substrate. The bonding pad electrically connects the outside of the integrated circuit to the microelectronic circuit inside the integrated circuit.
[0003]
FIG. 1 is a schematic diagram of an integrated circuit package including a plurality of bonding pads. As shown in FIG. 1, the integrated circuit 100, for example, a memory integrated circuit including the memory cell array unit 110 and the peripheral circuit unit 115 includes a plurality of bonding pads 200. The bonding pad 200 serves as a gate for the circuit terminal of the integrated circuit 100 and is internally connected to the input / output I / O buffer circuit in the peripheral circuit unit 115. As shown in FIG. 1, the integrated circuit 100 is bonded to the lead frame 300. Wire bonding or other conventional techniques are used to connect each wire 320 to the bonding pad 200 and the internal lead chip 310 of the lead frame 300.
[0004]
FIG. 2 is an enlarged plan view of the bonding pad 200 of FIG. FIG. 3 is a perspective view of the bonding pad shown in FIG. 4 is a cross-sectional view of the bonding pad taken along line IV-IV ′ of FIG. FIG. 5 is a sectional view of the bonding pad taken along the line VV ′ of FIG.
[0005]
2 to 5, in the conventional bonding pad structure, independent conductive plugs 245, for example, tungsten plugs, fill the plurality of via holes 240 in the insulating film 250 between the wirings. Yes. The conductive plug 245 electrically connects the lower aluminum wiring 230 and the upper aluminum wiring 260. Reference numeral 210 denotes an integrated circuit substrate, 220 denotes an interlayer insulating film, and 270 denotes a wire bonding region.
[0006]
[Problems to be solved by the invention]
The pad structure shown in FIGS. 2 to 5 has the following problems. For example, when the good integrated circuit 100 is separated from the wafer, a crack is generated in the inter-wiring insulating film 250 by a force applied by a probe pin (not shown) of an inspection device placed on the wire bonding region 270. The crack 330 is also generated in the inter-wiring insulating film 250 by a stress caused by a mechanical impact and pressure applied during bonding of the wire 320 to the wire bonding region 270.
[0007]
The crack is caused by deformation of the relatively soft upper aluminum wiring 260 and lower aluminum wiring 230 due to stress applied during sorting or wire bonding. However, the relatively hard inter-wiring insulating film 250 is not easily deformed. For this reason, when a stress of a certain value or more is applied, the unstable tungsten plug 245 is removed or a crack occurs in the inter-wiring insulating film 250. Such cracks are propagated inside the insulating film 250 covering the tungsten plug 245, as shown in FIG.
[0008]
The crack generated in the inter-wiring insulating film 250 causes a wiring open problem in which the upper and lower aluminum wirings 260 and 230 are peeled off. Alternatively, the contact between the wire 320 and the upper aluminum wiring 260 becomes poor, and a problem of pad opening in which the wire 320 is peeled off from the upper aluminum wiring 260 occurs.
[0009]
FIG. 6 shows another conventional example in which the tungsten plug 245 is formed only in a peripheral region outside the central wire bonding region in order to reduce cracks in the inter-wiring insulating film and reduce the peeling of the wiring film or the wire. It is a top view of the bonding pad structure. 7 is a cross-sectional view of the bonding pad structure taken along the line VII-VII ′ of FIG. Such bonding pad structures are disclosed in US Pat. Nos. 5,248,903 and 5,502,337.
[0010]
The bonding pad structure according to FIGS. 6 and 7 and the two patents can reduce cracks in the inter-wiring insulating film 250 to some extent. However, since the number of tungsten plugs 245 is reduced, the adhesion between the tungsten plug 245 and the upper aluminum wiring film 260 is weak. As a result, a wiring open phenomenon that the upper aluminum wiring film 260 breaks during wire bonding frequently occurs. Further, since the number of plugs is reduced, the contact area with the upper aluminum wiring film 260 is reduced. As a result, the resistance Rs is increased and the current is reduced. For this reason, a sufficient amount of current cannot be supplied to the switching element in the integrated circuit, which causes the operation of the element to deteriorate.
[0011]
The present invention has been made in view of the above circumstances, and an object of the present invention is to supply a sufficient amount of current into the chip while minimizing cracks in the inter-wiring insulating film during chip classification and wire bonding, and to achieve a photographic process. In addition to reducing the amount of light diffracted during the engraving process, the integrated circuit can improve the reliability of the integrated circuit because it can reduce the phenomenon that the upper wiring is peeled off from the upper conductive plug by repeated contact with the inspection probe The present invention provides a bonding pad structure.
[0012]
Another object of the present invention is to supply a sufficient amount of current into the chip while minimizing cracks in the inter-wiring insulating film, and to reduce the amount of light diffracted during the photolithography process, as well as an inspection probe. Therefore, it is possible to reduce a phenomenon in which the upper wiring is peeled off from the upper conductive plug by repetitive contact. Therefore, it is desirable to provide a method suitable for manufacturing a bonding pad structure capable of improving the reliability of an integrated circuit.
[0013]
[Means for Solving the Problems]
The bonding pad for the integrated circuit according to the present invention exists between the first conductive film and the second conductive film separated by a predetermined distance, and the first conductive film and the second conductive film separated by the predetermined distance, A continuous third conductive film electrically connected to the first conductive film and the second conductive film separated from each other by a distance, and the continuous third conductive film present in the continuous third conductive film And an array of island-like insulators that are non-aligned and separated by a predetermined distance, the side walls of which are covered with the continuous third conductive film.
[0014]
The array may include a lateral arrangement of island insulators that are non-aligned and spaced apart by a predetermined distance and a vertical array that is non-aligned and spaced apart by a predetermined distance. The array of island-like insulators that are non-aligned and spaced apart by a predetermined distance is adjacent to a first island-like insulator having a first edge in a first direction and a first island-like insulator in the first direction. , And a second island-like insulator having a second edge in a first direction that is not aligned with the first edge.
[0015]
The bonding pad is present between the continuous third conductive film and the second conductive film, and is connected to the continuous third conductive film and the second conductive film. A conductive film may be further included. A second array of island-shaped insulators separated by a predetermined distance exists in the continuous fourth conductive film, and extends so as to penetrate the continuous fourth conductive film, so that the sidewalls of the island-shaped insulator are formed. The second array of island-shaped insulators covered with the fourth conductive film and spaced apart by a predetermined distance is non-aligned and non-aligned with the first array of island-shaped insulators spaced by a predetermined distance. ing.
[0016]
The bonding pad may further include a metal bumper layer on the first conductive layer and an upper bonding pad layer on the metal bumper layer formed for bonding with the wire. The metal bumper layer may be tungsten. The metal bumper layer may have a thickness of about 4,000 mm. The metal bumper layer and the upper bonding pad layer may be a single layer having a thickness in the range of about 12,000 to 14,000 inches. The upper bonding pad layer may be directly above the metal bumper layer.
[0017]
The metal bumper layer may include an island-shaped insulator located on the outer edge side of the metal bumper layer. There are no island insulators in the internal region of the metal bumper layer.
[0018]
The structure of the bonding pad according to the present invention is present between the first conductive film and the second conductive film separated by a predetermined distance and the first conductive film and the second conductive film separated by the predetermined distance, and separated by the predetermined distance. And a continuous third conductive film electrically connected to the first conductive film and the second conductive film. The bonding pad structure is arranged in a zigzag manner in the continuous third conductive film, extends so as to penetrate the continuous third conductive film, and has a sidewall formed by the continuous third conductive film. It may further include an array of covered island insulators spaced a predetermined distance apart.
[0019]
In a method for manufacturing a bonding pad for an integrated circuit according to the present invention, a lower conductive film is first formed on an integrated circuit substrate. Next, a continuous conductive film electrically connected to the lower conductive film is formed on the lower conductive film. The continuous conductive film extends through the continuous conductive film and is spaced apart by a predetermined distance in which the sidewall of the island-like insulator is covered with the continuous conductive film. Includes an array of island insulators. Next, an upper conductive film electrically connected to the continuous conductive film is formed on the continuous conductive film.
[0020]
The step of forming the continuous conductive layer may include forming a continuous conductive layer including a lateral arrangement of island-like insulators spaced apart from each other by a predetermined distance. The step of forming the continuous conductive film includes a lateral arrangement of non-aligned island-like insulators spaced apart by a predetermined distance and a continuous film of non-aligned island-like insulators spaced apart by a predetermined distance. Can be included.
[0021]
The step of forming the continuous conductive film includes forming a first island-shaped insulator having a first edge in a first direction in the continuous conductive film, and forming the first island in the first direction. Forming a second island-like insulator in the continuous conductive film adjacent to the insulator and having a second edge in a first direction that is not aligned with the first edge.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various different forms. This embodiment is provided merely to complete the disclosure of the present invention and to fully inform those skilled in the art of the scope of the present invention. In the accompanying drawings, the thickness of various membranes and regions are emphasized for clarity. Also, when it is described that a certain film exists on another film or substrate, a certain film may be directly above the other film or substrate, or an interlayer film may exist between them. In the drawings, the same reference numerals represent the same elements.
[0023]
8 is a plan view of the bonding pad structure according to the first embodiment of the present invention, FIG. 9 is a perspective view of the bonding pad structure shown in FIG. 8, and FIG. 10 is an XX of FIG. FIG. 11 is a cross-sectional view of the bonding pad structure cut along the line “FIG. 11,” and FIG. 11 is a cross-sectional view of the bonding pad structure cut along the line XI-XI in FIG.
[0024]
In FIG. 8, reference numeral 920 represents a lower wiring, 925I represents a lower island-like insulator, 930 represents a lower integrated conductive plug, and 940 represents an intermediate wiring. Reference numeral 945I represents an upper island-shaped insulator, 950 represents an upper integrated conductive plug, 960 represents an uppermost wiring, and 970 represents a wire bonding region. Reference numerals 925 and 945 represent interlayer insulating films covering the outer walls of the lower and upper integrated conductive plug patterns, respectively. An integral conductive plug can also be referred to as a continuous conductive film. The wiring is called a conductive film, and the island-like insulator is called an insulating island. Terms such as “upper” / “lower” and “upper” / “lower” do not indicate absolute directions, but rather indicate relative relationships of whether they are adjacent to or away from the integrated circuit board. It is.
[0025]
Referring to FIGS. 9, 10, and 11, an interlayer insulating film 910 is formed on the integrated circuit substrate 900 and includes a lower wiring 920, an intermediate wiring 940, and an uppermost wiring 960 on the interlayer insulating film 910. A bonding pad structure having layer wiring is formed. The uppermost wiring 960 includes a wire bonding region 970 to which the wire 990 is bonded. The wire 990 can serve as a gate of a circuit terminal connected to an input / output buffer circuit (see 115 in FIG. 1) or the like constituting a peripheral circuit.
[0026]
An upper integrated conductive plug 950 is disposed between the lower surface of the uppermost wiring 960 and the upper surface of the intermediate wiring 940 to electrically connect the uppermost wiring 960 and the intermediate wiring 940. The upper integral conductive plug 950 has at least one upper island-shaped insulation whose side walls are completely covered by the integral conductive plug and whose upper and lower surfaces are covered by the uppermost wiring 960 and the intermediate wiring 940. A body 945I is formed. An array of upper island insulators 945I as shown is formed as a desirable example.
[0027]
The number and / or size of the upper island-shaped insulator 945I is determined within a range in which the area where the upper integrated conductive plug 950 and the uppermost wiring 960 are in contact with each other can be 10% or more of the area of the uppermost wiring 960. By setting the contact area to 10% or more, a current of a certain value or more can flow through the bonding pad portion. Desirably, a plurality of island insulators 945I, also referred to as an array of spaced island insulators, reduces the width of the island insulators 945I. That is, the insulating film sandwiched between the uppermost wiring 960 and the intermediate wiring 940 is partitioned into a plurality of island-shaped insulators 945I in the upper integrated conductive plug 950. For this reason, even if a crack is generated in one island-shaped insulator 945I, the remaining island-shaped insulator 945I is not cracked. In general, the uppermost wiring 960 functioning as a bonding pad is rectangular and has a size of 100 μm × 100 μm. The spacing between the upper island insulators 945I is preferably about 0.3 μm to 10 μm. In particular, the plurality of island-shaped insulators 945I are formed in a sieve shape with the upper integrated conductive plug 950. Therefore, the island-shaped insulators 945I are arranged in a matrix so that the island-shaped insulators 945I are not cracked even under a stress exceeding a predetermined value. The
[0028]
The connection structure between the intermediate wiring 940 and the lower wiring 920 is also configured the same as the connection structure between the intermediate wiring 940 and the uppermost wiring 960. That is, the intermediate wiring 940 and the lower wiring 920 are electrically connected by the lower integrated conductive plug 930 having at least one lower island-shaped insulator 925I.
[0029]
The structure of the bonding pad described above is a three-layer wiring according to the first embodiment of the present invention. However, the bonding pad structure may be a two-layer wiring or a multilayer wiring including the uppermost wiring 960 and the intermediate wiring 940.
[0030]
The effect of the structure of the bonding pad according to the first embodiment of the present invention will be described with reference to the structure in which the uppermost wiring 960 and the intermediate wiring 940 are connected. In the bonding pad structure according to the present invention, the uppermost wiring (see 260 in FIG. 3) and the lowermost wiring (see 230 in FIG. 3) are insulated by an integrated insulating film (see 250 in FIG. 3). A plurality of independent conductive plugs (see 245 in FIG. 3) adopts a structure completely opposite to the conventional bonding pad structure in which the uppermost wiring 260 and the lowermost wiring 230 are connected. That is, according to the present invention, the conductive plug 950 connecting the uppermost wiring 960 and the intermediate wiring 940 is a continuous conductive plug, and the insulation sandwiched between the uppermost wiring 960 and the intermediate wiring 940 is provided. Most of the membrane is partitioned into at least one island-like insulator 945I within the integral conductive plug 950.
[0031]
The island-shaped insulator 945I has a very stable structure because the side wall is completely covered by the integrated conductive plug 950 and the upper and lower surfaces are covered by the wirings 960 and 940. For this reason, even if a certain mechanical stress is applied during chip classification and / or wire bonding, the island-shaped insulator 945I does not crack. Further, even if a crack is generated in the island-shaped insulator 945I, the crack is not propagated to the adjacent island-shaped insulator 945I.
[0032]
12 is a plan view of a bonding pad structure according to a second embodiment of the present invention, FIG. 13 is a perspective view of the bonding pad structure shown in FIG. 12, and FIG. 14 is a XIV-XIV of FIG. FIG. 15 is a cross-sectional view of the bonding pad structure cut along the line ', and FIG. 15 is a cross-sectional view of the bonding pad structure cut along the line XV-XV ′ of FIG.
[0033]
Referring to FIGS. 12 to 15, in the second embodiment, the intermediate wiring 940 ′ is not formed in a continuous plate shape, but in an island shape like the upper and lower integrated conductive plugs 950 and 930. Insulator 935I is included. For this reason, the island-shaped insulator in the intermediate wiring overlaps with the island-shaped insulator in the upper and lower integrated conductive plugs 950 and 930. Desirably, the island-shaped insulator 945I in the upper integrated conductive plug 950 and the island-shaped insulator 925I in the lower integrated conductive plug 930 are connected to the island-shaped insulator 935I in the intermediate wiring 940 ′. An island-like insulator I is formed. When the island-shaped insulators 945I and 925I in the upper and lower integrated conductive plugs 950 and 930 and the island-shaped insulator 935I in the intermediate wiring 940 ′ are connected to form one island-shaped insulator I, Since the thickness of the island-like insulator I is the sum of the thicknesses of the three insulators 925I, 935I, and 945I, resistance to stress is increased.
[0034]
FIG. 16 is a plan view of a bonding pad structure according to a third embodiment of the present invention.
Referring to FIG. 16, in the third embodiment, the plurality of island-shaped insulators 925I and 945I are arranged in a zigzag shape and are alternately formed.
[0035]
FIG. 17 is a plan view of a bonding pad structure according to a fourth embodiment of the present invention.
Referring to FIG. 17, in the fourth embodiment, the island-shaped insulators 945I ′ and 925I ′ are cylindrical. Further, the island-shaped insulator can be formed in various polygonal column shapes such as a triangular column or a pentagonal column.
[0036]
FIG. 18 is a plan view of a bonding pad structure according to a fifth embodiment of the present invention.
Referring to FIG. 18, in the fifth embodiment, the integrated conductive plugs 930 ′ and 950 ′ are formed only in the lower part of the peripheral region outside the region covered with the wire bonding region 970 of the uppermost wiring, Insulators 929 and 949 are formed below the central wire bonding region 970. According to the fifth embodiment, since no plug functioning as a crack generation site is formed below the wire bonding region 970, no cracks are generated in the insulators 929 and 949, and the region around the wire bonding region is not generated. A predetermined contact area with the uppermost wiring 960 is ensured by the integrated conductive plugs 930 ′ and 950 ′ formed in the lower part of the wiring.
[0037]
FIG. 19 is a plan view of a bonding pad structure according to a sixth embodiment of the present invention.
Referring to FIG. 19, in the sixth embodiment, the island-shaped insulators 925I 'and 945I' formed in the integrated conductive plugs 930 'and 950' are strip-shaped.
[0038]
A method of forming the bonding pad structure (see FIG. 9) according to the first embodiment of the present invention will be described with reference to FIG.
First, the step of forming the intermediate wiring 940 and the uppermost wiring 960 will be described. Intermediate wiring 940 is formed on integrated circuit substrate 900 on which underlying layers 910, 920, 930 are formed (step 2000). Next, an inter-wiring insulating film 945 is formed on the intermediate wiring 940 (step 2010). The inter-wiring insulating film 945 is formed by depositing an insulator on the intermediate wiring 940 and then planarizing it by an etch back and / or chemical mechanical polishing process.
[0039]
Next, the inter-wiring insulating film 945 is patterned using a mask that limits the region where the upper integrated conductive plug is to be formed (step 2020). As a result, the intermediate wiring 940 is partially exposed, and a continuous trench that defines at least one island-shaped insulator 945I is formed.
[0040]
The plurality of island-shaped insulators 945I are desirably patterned to be arranged in a matrix or zigzag pattern. The distance between the island-shaped insulators 945I, that is, the width of the trench is about 0.3 μm to 10 μm. The reason why the gaps are formed at intervals of 0.3 μm or more is to prevent a crack generated in one island-shaped insulator 945I from propagating to another island-shaped insulator 945I. The reason why the gaps are formed at intervals of 10 μm or less is to sufficiently fill the trenches between the island-shaped insulators with the conductive plugs.
[0041]
Next, a conductive film filling the trench is formed using a conductive material, such as tungsten, copper, or aluminum (step 2030). Subsequently, the conductive film filling the trench is planarized by an etch back and / or chemical mechanical polishing process to complete the upper integrated conductive plug 950 that covers the side wall of the island-shaped insulator 945I (step 2040). The total area of the upper surface of the upper integrated conductive plug 950 is desirably 10% or more of the area of the uppermost wiring 960 to be formed.
[0042]
As another method, first, a solid conductive film electrically connected to the lower conductive film is formed on the lower conductive film. Next, the solid conductive film is etched to form a plurality of vias penetrating the solid conductive film and spaced apart from each other by a predetermined distance. Next, an insulating film is formed on the solid conductive film and in the via. Finally, the insulating film is removed from the solid conductive film by etch back and / or chemical mechanical polishing, and the insulating film is left in the via.
[0043]
If the explanation of FIG. 20 is continued, the uppermost wiring 960 functioning as a bonding pad is formed on the upper surface of the upper integrated conductive plug 950 (step 2050). Next, a passivation film 980 is formed on the entire surface including the uppermost wiring 960 (step 2060). The passivation film 980 is preferably formed of a film that does not permeate moisture, is resistant to stress, has high step application properties, and can be formed uniformly. Subsequently, the passivation film 980 is patterned to expose the wire bonding region 970 of the uppermost wiring 960 (step 2070).
[0044]
The method for forming the lower layer of the intermediate wiring 940, that is, the lower wiring 920 and the lower integrated conductive plug 930, includes steps 2000 (wiring forming stage) to step 2040 (forming process of the integrated conductive plug and island insulator). In the same manner as in step (2), the step is performed before the intermediate wiring 940 is formed. It goes without saying that a bonding pad structure having a multilayer wiring structure can be formed by repeatedly performing the step of forming the lower layered structure.
[0045]
In the method of manufacturing the bonding pad structure according to the second embodiment (see FIGS. 13 and 14), the intermediate wiring 940 ′ is formed in the same form as the upper and lower integrated conductive plugs 950 and 930. That is, after forming the lower integrated conductive plug 930 including the lower island-like insulator 925I through steps 2000 to 2040, the steps 2010 to 2040 are performed in the same manner, and partially with the lower integrated conductive plug 930. An integrated intermediate wiring 940 ′ having an overlapping intermediate island-shaped insulator 935I is formed. The step of forming the upper integrated conductive plug 950 and the uppermost wiring 960 is performed in the same manner as the method of the first embodiment. Preferably, the lower, middle and upper island insulators 925I, 935I and 945I are connected together.
[0046]
The present invention will be described in more detail with reference to the following experimental examples, but the experimental examples do not limit the present invention.
<Experimental example 1>
A first sample having a bonding pad structure according to the present invention was prepared. That is, four layers of aluminum wiring are formed on the substrate, and an integral tungsten plug having island-like insulators separated by about 3.4 μm is formed between the wirings, and the wirings are electrically connected. It was. After forming a passivation film on the uppermost wiring, this was patterned to expose the wire bonding region. Next, a wire was bonded by a wedge method to prepare a sample.
[0047]
After completing the bonding pad structure, the wire pulling strength was measured using a wire pulling strength measuring device.
The number of first samples having the bonding pad structure according to the present invention is 170. Also, 197 first control samples having a conventional bonding pad as shown in FIG. 3 and 170 second control samples having a conventional bonding pad structure as shown in FIG. 7 were prepared. The wire pulling strength was also measured for the control sample by the same method.
[0048]
The measurement results are shown in Table 1 below and FIG. In FIG. 21, the graph plotted with-○-indicates the wire pulling strength of the bonding pad according to the present invention (first sample), and the graph plotted with -Δ- indicates the conventional bonding pad (first control sample). A graph plotted with-□-represents the wire pull strength of another conventional bonding pad (second control sample). The cumulative distribution (%) is a value indicating the number of samples from which the wire peels in percentage while increasing the tensile force from 0 g weight to 10 g weight. In Table 1, the cumulative distribution is a value indicating the number of samples from which wires are separated with a pulling strength of 6 g weight or less as a percentage.
[0049]
[Table 1]
Figure 0003952260
From the results of Table 1 and FIG. 21, it can be seen that the pad according to the present invention has a higher wire pulling strength than the conventional pad.
[0050]
<Experimental example 2>
For the first sample and the first and second control samples formed in the same manner as in Experimental Example 1, the pad open phenomenon in which the wire is peeled off due to poor contact between the wire and the aluminum wiring functioning as a bonding pad And the wiring open phenomenon in which the wiring film peeled off during bonding was measured. Further, after measuring pad open and wiring open, 158 first samples, 140 first control samples, and 142 second control samples were measured with an island-like insulator or inter-wiring insulating film below the uppermost aluminum wiring. The number of cracks that occurred was measured. The number of cracks was measured using a scanning electron microscope after removing the passivation film and the uppermost aluminum wiring of each sample using an appropriate etching solution. The results are shown in Table 2 below and FIG.
[0051]
[Table 2]
Figure 0003952260
[0052]
Referring to Table 2 and FIG. 22, many cracks occurred in the first control sample and the second control sample employing the conventional pad structure, whereas the first sample employing the pad structure according to the present invention had cracks. It did not occur at all. Further, since no crack was generated, no wiring open phenomenon was observed in the first sample, and the frequency of the pad open phenomenon was significantly reduced as compared with the conventional pad structure.
[0053]
According to the bonding pad structure of the present invention, since the uppermost wiring and the lower wiring of the uppermost wiring are connected by the continuous conductive plug, a contact area of a predetermined size or more can be secured. For this reason, a sufficient amount of current can be transmitted into the bonding pad structure.
[0054]
In addition, an insulating film between the uppermost wiring and the lower wiring is formed from an island-shaped insulator confined in an integrated conductive plug. This reduces the occurrence of cracks in the insulator due to physical stress applied when probe pins are placed for chip classification or when wires are bonded. And since an insulator is formed in an island shape, it is prevented that a crack propagates to other surrounding insulators.
[0055]
8 to 11, in various embodiments according to the present invention, a plurality of island-shaped insulators 945I are arranged in a line, and the upper integrated conductive plug 950 has a sieve pattern. This sieving arrangement of the upper integrated conductive plug 950 may cause the unstable upper integrated conductive plug 950 to shift even if there is stress between the upper integrated conductive plug 950 and the island-shaped insulator 945I. Lower. Therefore, the island-shaped insulator 945I does not crack even under a stress greater than a predetermined value. Alternatively, even if a crack occurs, the crack is not propagated to other island-like insulators 945I.
[0056]
The distance D1 between the island-shaped insulators 945I shown in FIG. 8 is determined in consideration of the propagation of cracks to other island-shaped insulators 945I and the manufacturing process conditions. That is, the distance D1 between the island-shaped insulators 945I needs to be sufficiently large so that a crack generated in one island-shaped insulator 945I is not propagated to the other island-shaped insulator 945I. Further, after the island-shaped insulator 945I is formed first, and a conductive material such as tungsten is formed between and above these, the conductive material is planarized to form the upper integrated conductive plug 950. In embodiments, the maximum distance between the island insulators 945I may be less than twice the thickness of the conductor material formed during the manufacturing process so that the island insulators 945I are completely surrounded by the conductor material. desirable.
[0057]
The distance D1 between the upper island-shaped insulators 945I is preferably about 0.3 μm to 10 μm. In an embodiment according to the present invention in which the conductive material used to form the upper integrated conductive plug 950 has a thickness of about 0.4 μm to 1 μm, the distance between the upper island-shaped insulators 945I is 0.3 μm to It is desirable to make it about 2 μm. In general, the uppermost wiring 960 functions as a bonding pad and is square and has a size of about 100 μm × 100 μm.
[0058]
FIG. 23 to FIG. 26 are plan views showing an arrangement of island-like insulators separated by a predetermined distance as yet another embodiment of the present invention. In the embodiment shown in FIGS. 23 and 24, the laterally arranged island insulators are non-aligned or offset from each other. For this reason, only two apex portions of the island insulator are adjacent to each other. By reducing the number of vertices or edges of island insulators adjacent to each other, the amount of light diffracted during the photolithography process can be reduced.
[0059]
In other embodiments according to the invention, the vertically arranged island insulators may be misaligned or offset from each other. In addition, both horizontal and vertical island insulators may be misaligned. Adjacent horizontal and / or vertical arrays are offset from one another by, for example, a half distance. Every other horizontal and / or vertical array is aligned, and adjacent horizontal and / or vertical arrays are non-aligned or offset by a half distance therebetween. Of course, other intervals can be used.
[0060]
As yet another embodiment according to the present invention, the island-like insulator edges may be misaligned, for example, as shown in FIG. As shown in FIG. 25, adjacent edges 2501 to 2506 in the non-aligned array are not aligned. Unaligned edges 2501-2506 can further reduce the amount of light diffracted during the photolithography process. In some cases, the vertical edges are not aligned.
[0061]
As shown in FIG. 26, both lateral and longitudinal edges 2601 to 2609 may be misaligned with each other. In particular, the lateral edges 2601 to 2605 of the non-aligned array are non-aligned with respect to each other, and the vertical edges 2606 to 2609 of the unaligned array are also unaligned with respect to each other. Edges that are misaligned both horizontally and vertically can further reduce the amount of light diffracted during the photolithography process.
[0062]
Unlike the embodiment according to FIGS. 25 and 26 of the present invention, the horizontal and vertical arrangements of the island insulators described as examples in FIG. 8 are aligned. In the array arranged in this way, the four vertices of the island insulators are adjacent to each other. Therefore, in the photographic etching process, the diffraction generated at each vertex of the island-shaped insulator is overlapped, and the pattern portion hitting the vertex is rounded to change the critical value of the island-shaped insulator. Therefore, the thickness of the conductive film surrounding the island-shaped insulator needs to be thick in order to completely surround the island-shaped insulator with the conductive film. In short, in the arrangement of FIG. 8, because the four vertices are adjacent to each other, more diffraction is caused, which creates an unclear edge.
[0063]
The upper island insulator 945I and the lower island insulator 925I may be misaligned with each other. For example, the upper island insulators 945I are arranged in a non-aligned manner as shown in FIG. 23, and the lower island insulators 925I are arranged in an aligned manner as shown in FIG. 8, for example.
[0064]
Referring again to FIG. 24, when the tester probe pin is placed laterally in the wire bonding area 970, the force applied by the tester probe pin continues along the lower and upper integrated conductive plugs 930,950. And is blocked by upper and lower island insulators 945I and 925I. Thus, the resistance to probe pin force (ie, shear force) is increased relative to, for example, the resistance of the aligned array shown in FIG. Desirably, the distance D2 between the island-shaped insulators is sufficiently large so that a crack generated in one island-shaped insulator cannot propagate to the other island-shaped insulators. The maximum spacing between the island insulators is desirably less than twice the thickness of the conductive material for forming the lower and upper integrated conductive plugs.
[0065]
In this embodiment, the solid intermediate wiring 940 can be formed in a plate shape as shown in FIG. 10, or can be formed so that an island-like insulator is present as shown in FIG. Accordingly, the solid intermediate wiring 940 overlaps with the upper and lower integrated conductive plugs 950 and 930. Further, in the case of the solid intermediate wiring 940 ′ of FIG. 14, it matches the upper and lower integrated conductive plugs 950 and 930.
[0066]
As yet another embodiment according to the present invention, the bonding pad may include a metal bumper layer 2700 as shown in FIG. The metal bumper layer 2700 is on the upper wiring 2760 formed on the conductive plug 2750 surrounded by the insulating material 2745. Upper bonding pad layer 2705 is formed on metal bumper layer 2700. Upper bonding pad layer 2705 is directly over metal bumper layer 2700.
[0067]
During manufacturing, the inspection probe repeatedly contacts the upper bonding pad layer 2705 so that portions of the integrated circuit can be inspected. Thereafter, the wire is bonded to the upper bonding pad layer 2705, for example, as shown in FIG. The metal bumper layer 2700 reduces the possibility that repeated contact of the inspection probe reduces the mechanical coupling between the upper conductive plug 2750 and the upper wiring 2760. Therefore, this embodiment can improve the reliability of the integrated circuit by reducing the likelihood that the upper wiring 2760 will peel off the upper conductive plug 2750 as a result of repeated contact by the inspection probe.
[0068]
In the conventional bonding pad structure, the inspection probe bites into the upper wiring so that the upper conductive plug and the insulating material are exposed. Thus, the solder used to bond the wire to the bonding pad contacts the exposed insulating material that does not provide sufficient bonding adhesion, and the upper wiring is stripped from the upper conductive plug.
[0069]
The bonding pad structure according to the present invention can be manufactured by forming the lower wiring 2740 on the first insulating film 2710. The lower wiring 2740 may be a metal such as aluminum or copper. Of course, other metals can be used. The lower wiring 2740 is patterned, and a second insulating film 2745 such as an oxide film is formed thereon. The second insulating film 2745 is patterned to form a via therein. The upper conductive plug 2750 is formed in the via using an etch back process or chemical mechanical polishing (CMP). The upper conductive plug 2750 may be a conductive material such as tungsten (W), aluminum (Al), or copper (Cu). Of course, other conductive materials can be used. A barrier layer (not shown) such as Ti or TiN may be deposited between the lower wiring 2740 and the second insulating film 2745.
[0070]
The second wiring 2760 is formed on the second insulating film 2745 and the upper conductive plug 2750. The metal bumper layer 2700 is formed on the second wiring 2760 using an etch back process as shown in FIG. 27 or chemical mechanical polishing (CMP) as shown in FIG. The metal bumper layer 2700 may be about 400 mm thick. The metal bumper layer 2700 can be formed simultaneously with the plug in the internal region of the integrated circuit. The upper bonding pad layer 2705 may be formed on the metal bumper layer 2700 with a thickness of about 8,000 to 10,000 inches. The bonding thickness of the metal bumper layer 2700 and the upper bonding pad layer 2705 is in the range of about 12,000 to 14,000 mm. As shown in FIG. 28, the thickness of the metal bumper layer 2700 and the upper bonding pad layer 2705 can be adjusted to compensate for an etch back process or chemical mechanical polishing (CMP).
[0071]
The metal bumper layer 2700 includes tungsten. Of course, other metals can be used. The metal bumper layer 2700 may also be formed as a bonding pad structure including a predetermined distance apart island-like insulator and integral conductive plug according to the present invention described with reference to FIGS. 8 to 22 and FIGS. 23 to 26. .
[0072]
FIG. 29 is a cross-sectional view illustrating an embodiment of a bonding pad structure having a metal bumper layer 2900 having an island-like insulator 2905 embedded therein according to the present invention. As shown in FIG. 29, the island-like insulator 2905 is located in the metal bumper layer 2900 and located on the outer edge side. Therefore, the inner region of the metal bumper layer 2900 has fewer island-like insulators 2905 than the island-like insulators 2905 located on the outer edge side. In some embodiments, the interior region of the metal bumper layer 2900 is free of island insulators 2905. Thus, embodiments in accordance with the present invention are less sensitive to stress applied to the inner region of the metal bumper layer 2900, and therefore there is little possibility of loosening of the bond.
[0073]
FIG. 30 is a cross-sectional view illustrating another embodiment of a bonding pad structure having a metal bumper layer 3000 according to the present invention. As shown in FIG. 30, the second conductive film 3010 and the upper conductive plug 3020 are formed using a damascene process. The metal bumper layer 3000 and the upper bonding pad layer 3005 are formed as a single layer having a thickness in the range of about 12,000 to 14,000.
[0074]
【The invention's effect】
As described above, according to the bonding pad structure of the present invention, since the uppermost wiring and the lower wiring of the uppermost wiring are connected by the continuous conductive plug, a contact area of a predetermined size or more can be secured. For this reason, a sufficient amount of current can be transmitted into the bonding pad structure.
[0075]
Further, the insulating film between the uppermost wiring and the lower wiring is formed of an island-like insulator confined in the integrated conductive plug. Thus, the physical stress applied when probe pins are placed for chip classification or when wires are bonded is reduced in the insulation. In addition, since the insulator is formed in an island shape, it is possible to prevent cracks from being propagated to other surrounding insulators.
[0076]
In one specific example, the upper integrated conductive plug has a plurality of island-like insulators arranged in a line and has a sieve shape. Therefore, even if there is stress between the upper integrated conductive plug and the island-like insulator, the sieve arrangement of the upper integrated conductive plug reduces the possibility of the unstable upper integrated conductive plug peeling off. For this reason, the island-shaped insulator does not crack even under a stress of a predetermined value or more. Alternatively, even if a crack occurs, the crack is not propagated to other island-like insulators.
[0077]
On the other hand, in a specific example, the island-shaped insulators in the horizontal array and / or the vertical array are not aligned with each other or are offset, and at this time, only two apex portions of the island-shaped insulators are mutually connected. Adjacent. Therefore, the amount of light diffracted during the photolithography process can be reduced by reducing the number of apex portions or edges of the island-like insulators adjacent to each other.
[0078]
The bonding pad may include a metal bumper layer, which reduces the mechanical coupling between the upper conductive plug and the upper wiring due to repeated contact of the inspection probe. Therefore, the present invention can improve the reliability of the integrated circuit by reducing the upper wiring from being peeled off the upper conductive plug as a result of repeated contact by the inspection probe.
[0079]
Further, the present invention may be a bonding pad structure having a metal bumper layer in which an island-shaped insulator is embedded, but the bonding pad structure having a metal bumper layer in which an island-shaped insulator is embedded is formed in an inner region of the metal bumper layer. It is less sensitive to the applied stress and therefore has little chance of loosening.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of an integrated circuit bonded to a lead frame.
FIG. 2 is an enlarged plan view of the conventional bonding pad structure shown in FIG.
3 is a perspective view of the bonding pad structure shown in FIG. 2. FIG.
4 is a cross-sectional view of the bonding pad structure taken along line IV-IV ′ of FIG.
5 is a cross-sectional view of the bonding pad structure taken along line VV ′ of FIG.
FIG. 6 is a plan view of another conventional bonding pad structure.
7 is a cross-sectional view of the bonding pad structure taken along the line VII-VII ′ of FIG.
FIG. 8 is a plan view of a bonding pad structure according to a first embodiment of the present invention.
9 is a perspective view of the bonding pad structure shown in FIG.
10 is a cross-sectional view of the bonding pad structure taken along line XX ′ of FIG.
11 is a cross-sectional view of the bonding pad structure taken along line XI-XI ′ of FIG.
FIG. 12 is a plan view of a bonding pad structure according to a second embodiment of the present invention.
13 is a perspective view of the bonding pad structure shown in FIG. 12. FIG.
14 is a cross-sectional view of the bonding pad structure taken along line XIV-XIV ′ of FIG.
15 is a cross-sectional view of the bonding pad structure taken along line XV-XV ′ of FIG.
FIG. 16 is a plan view of a bonding pad structure according to a third embodiment of the present invention.
FIG. 17 is a plan view of a bonding pad structure according to a fourth embodiment of the present invention.
FIG. 18 is a plan view of a bonding pad structure according to a fifth embodiment of the present invention.
FIG. 19 is a plan view of a bonding pad structure according to a sixth embodiment of the present invention.
FIG. 20 is a block diagram illustrating a method of manufacturing a bonding pad structure according to the present invention.
FIG. 21 is a characteristic diagram showing the pull strength of a wire bonded to a bonding pad structure according to the present invention compared to a conventional bonding pad.
FIG. 22 is a characteristic diagram showing a pad open and a wire open in the bonding pad structure according to the present invention in comparison with a conventional bonding pad structure.
FIG. 23 is a plan view illustrating an embodiment of a bonding pad structure including an array of island-like insulators that are non-aligned and separated by a predetermined distance according to the present invention.
FIG. 24 is a plan view illustrating an embodiment of a bonding pad structure including an array of island-like insulators that are non-aligned and separated by a predetermined distance according to the present invention.
FIG. 25 is a plan view illustrating an embodiment of a bonding pad structure including an array of island-like insulators that are non-aligned and separated by a predetermined distance according to the present invention.
FIG. 26 is a plan view illustrating an embodiment of a bonding pad structure including an array of island-like insulators that are non-aligned and spaced apart by a predetermined distance according to the present invention.
FIG. 27 is a cross-sectional view illustrating an embodiment of a bonding pad structure including a metal bumper layer according to the present invention.
FIG. 28 is a cross-sectional view illustrating an embodiment of a bonding pad structure including a metal bumper layer according to the present invention.
FIG. 29 is a cross-sectional view illustrating an embodiment of a bonding pad structure including a metal bumper layer according to the present invention.
FIG. 30 is a cross-sectional view illustrating an embodiment of a bonding pad structure including a metal bumper layer according to the present invention.
[Explanation of symbols]
920 Lower wiring
930 Lower integrated conductive plug
940 Intermediate wiring
950 Top integrated conductive plug
960 Top wiring
925I Lower island insulator
945I Upper island insulator
925,945 Interlayer insulating film
970 Wire bonding area

Claims (14)

所定距離離隔された第1導電膜及び第2導電膜と、
前記所定距離離隔された第1導電膜及び第2導電膜間に存在し、前記所定距離離隔された第1導電膜及び第2導電膜に電気的に接続された連続的な第3導電膜と、
前記連続的な第3導電膜内に存在し、前記連続的な第3導電膜を貫通するように延びてその側壁が前記連続的な第3導電膜により覆われた非整列で、かつ所定距離離隔された島状絶縁体の配列と、
前記第1導電膜上の金属バンパ層と、
ワイヤとボンディングするために形成された前記金属バンパ層上の上部ボンディングパッド層とを含み、
前記金属バンパ層は、該金属バンパ層の外部エッジ側に位置した島状絶縁体を含み、金属バンパ層の内部領域には、島状絶縁体がないことを特徴とする集積回路のためのボンディングパッド。
A first conductive film and a second conductive film separated by a predetermined distance;
A continuous third conductive film that exists between the first conductive film and the second conductive film separated by a predetermined distance and is electrically connected to the first conductive film and the second conductive film separated by the predetermined distance; ,
A non-aligned and predetermined distance that is present in the continuous third conductive film, extends through the continuous third conductive film, and has a sidewall covered with the continuous third conductive film. an array of spaced islands insulator,
A metal bumper layer on the first conductive film;
An upper bonding pad layer on the metal bumper layer formed for bonding with a wire,
The metal bumper layer includes an island-shaped insulator located on the outer edge side of the metal bumper layer, and there is no island-shaped insulator in the inner region of the metal bumper layer. pad.
前記第3導電膜内に存在する前記島状絶縁体の配列は非整列で、かつ所定距離離隔された島状絶縁体の横配列を含むことを特徴とする請求項1に記載の集積回路のためのボンディングパッド。2. The integrated circuit according to claim 1, wherein the array of island-shaped insulators present in the third conductive film includes a lateral array of island-shaped insulators that are non-aligned and spaced apart by a predetermined distance. Bonding pad for. 前記第3導電膜内に存在する前記島状絶縁体の配列は非整列で、かつ所定距離離隔された島状絶縁体の横配列及び非整列で、かつ所定距離離隔された島状絶縁体の縦配列を含むことを特徴とする請求項1に記載の集積回路のためのボンディングパッド。 The arrangement of the island insulators present in the third conductive film is non-aligned, and is a lateral arrangement and non-alignment of the island insulators separated by a predetermined distance, and the island insulators separated by a predetermined distance. The bonding pad for an integrated circuit according to claim 1, comprising a vertical array. 前記第3導電膜内に存在する前記非整列で、かつ所定距離離隔された島状絶縁体の配列は、
第1方向の第1エッジを有する第1島状絶縁体と、
前記第1方向の第1島状絶縁体に隣接し、第1エッジと非整列とされた第1方向の第2エッジを有する第2島状絶縁体とを含むことを特徴とする請求項1に記載の集積回路のためのボンディングパッド。
The arrangement of the non-aligned and island-like insulators existing in the third conductive film and separated by a predetermined distance is:
A first island-like insulator having a first edge in a first direction;
2. A second island-like insulator having a second edge in a first direction adjacent to the first island-like insulator in the first direction and not aligned with the first edge. Bonding pads for integrated circuits as described in 1.
前記第3導電膜内に存在する前記非整列で、かつ所定距離離隔された島状絶縁体の配列は、非整列で、かつ所定距離離隔された島状絶縁体の第1配列であり、
前記ボンディングパッドは、
前記連続的な第3導電膜及び前記第2導電膜間に存在し、前記連続的な第3導電膜及び前記第2導電膜に電気的に接続された連続的な第4導電膜と、
前記連続的な第4導電膜内に存在し、前記連続的な第4導電膜を貫通するように延びてその側壁が前記連続的な第4導電膜により覆われた所定距離離隔された島状絶縁体の第2配列とをさらに含み、前記所定距離離隔された島状絶縁体の第2配列は、前記非整列で、かつ所定距離離隔された島状絶縁体の第1配列と非整列とされていることを特徴とする請求項1に記載の集積回路のためのボンディングパッド。
The array of island-like insulators that are non-aligned and separated by a predetermined distance in the third conductive film is a first array of island-like insulators that are non-aligned and separated by a predetermined distance,
The bonding pad is
A continuous fourth conductive film that exists between the continuous third conductive film and the second conductive film and is electrically connected to the continuous third conductive film and the second conductive film;
Island-like islands existing in the continuous fourth conductive film, extending so as to penetrate the continuous fourth conductive film, and having sidewalls covered by the continuous fourth conductive film and separated by a predetermined distance A second array of insulators, wherein the second array of island insulators separated by a predetermined distance is non-aligned and non-aligned with the first array of island insulators separated by a predetermined distance. The bonding pad for an integrated circuit according to claim 1, wherein the bonding pad is formed.
前記金属バンパ層は、タングステンを含むことを特徴とする請求項に記載の集積回路のためのボンディングパッド。The bonding pad for an integrated circuit according to claim 1 , wherein the metal bumper layer includes tungsten. 前記金属バンパ層は、約4,000Åの厚さを有することを特徴とする請求項に記載の集積回路のためのボンディングパッド。The bonding pad for an integrated circuit of claim 1 , wherein the metal bumper layer has a thickness of about 4,000 mm. 前記金属バンパ層及び前記上部ボンディングパッド層は、約12,000Åないし14,000Åの範囲の厚さを有する単一層であることを特徴とする請求項に記載の集積回路のためのボンディングパッド。The bonding pad for an integrated circuit of claim 1 , wherein the metal bumper layer and the upper bonding pad layer are a single layer having a thickness in the range of about 12,000 to 14,000. 前記上部ボンディングパッド層は、前記金属バンパ層の真上にあることを特徴とする請求項に記載の集積回路のためのボンディングパッド。The bonding pad for an integrated circuit according to claim 1 , wherein the upper bonding pad layer is directly above the metal bumper layer. 内部に貫通するように島状絶縁部を含む導電膜と、
前記導電膜及びその内部の前記島状絶縁部上の金属バンパ層と、
ワイヤとボンディングするために形成された前記金属バンパ層上の上部ボンディングパッド層とを含み、
前記金属バンパ層は、該金属バンパ層の外部エッジ側に位置した島状絶縁体を含み、金 属バンパ層の内部領域には、島状絶縁体がないことを特徴とする集積回路のためのボンディングパッド。
A conductive film including an island-shaped insulating portion so as to penetrate inside,
A metal bumper layer on the conductive film and the island-like insulating portion inside the conductive film;
An upper bonding pad layer on the metal bumper layer formed to wire bonding seen including,
The metal bumper layer comprises an island-like insulator located outside the edge side of the metal bumper layer, the inner region of the metallic bumper layer, for an integrated circuit, characterized in that there is no island-shaped insulator Bonding pad.
前記金属バンパ層は、タングステンを含むことを特徴とする請求項10に記載の集積回路のためのボンディングパッド。The bonding pad for an integrated circuit according to claim 10 , wherein the metal bumper layer includes tungsten. 前記上部ボンディングパッド層は、前記金属バンパ層の直上にあることを特徴とする請求項10に記載の集積回路のためのボンディングパッド。The bonding pad for an integrated circuit according to claim 10 , wherein the upper bonding pad layer is directly on the metal bumper layer. 前記金属バンパ層は、固体金属膜を含むことを特徴とする請求項10に記載の集積回路のためのボンディングパッド。The bonding pad for an integrated circuit according to claim 10 , wherein the metal bumper layer includes a solid metal film. 所定距離離隔された第1導電膜及び第2導電膜と、
前記所定距離離隔された第1導電膜及び第2導電膜間に存在し、前記所定距離離隔された第1導電膜及び第2導電膜に電気的に接続された連続的な第3導電膜と、
前記連続的な第3導電膜内にジグザグ状に配列され、前記連続的な第3導電膜を貫通するように延びてその側壁が前記連続的な第3導電膜により覆われた所定距離離隔された島状絶縁体の配列と、
前記第1導電膜上の金属バンパ層と、
ワイヤとボンディングするために形成された前記金属バンパ層上の上部ボンディングパッド層とを含み、
前記金属バンパ層は、該金属バンパ層の外部エッジ側に位置した島状絶縁体を含み、金属バンパ層の内部領域には、島状絶縁体がないことを特徴とする集積回路のためのボンディングパッド。
A first conductive film and a second conductive film separated by a predetermined distance;
A continuous third conductive film that exists between the first conductive film and the second conductive film separated by a predetermined distance and is electrically connected to the first conductive film and the second conductive film separated by the predetermined distance; ,
The continuous third conductive film is arranged in a zigzag pattern, extends so as to penetrate the continuous third conductive film, and has a sidewall separated by a predetermined distance covered by the continuous third conductive film. An array of island-like insulators ,
A metal bumper layer on the first conductive film;
An upper bonding pad layer on the metal bumper layer formed for bonding with a wire,
The metal bumper layer includes an island-shaped insulator located on the outer edge side of the metal bumper layer, and there is no island-shaped insulator in the inner region of the metal bumper layer. pad.
JP2001339918A 2000-12-21 2001-11-05 Bonding pads for integrated circuits Expired - Fee Related JP3952260B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/745,241 US6552438B2 (en) 1998-06-24 2000-12-21 Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same
US09/745241 2000-12-21

Publications (2)

Publication Number Publication Date
JP2002208610A JP2002208610A (en) 2002-07-26
JP3952260B2 true JP3952260B2 (en) 2007-08-01

Family

ID=24995845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001339918A Expired - Fee Related JP3952260B2 (en) 2000-12-21 2001-11-05 Bonding pads for integrated circuits

Country Status (3)

Country Link
JP (1) JP3952260B2 (en)
KR (1) KR100421043B1 (en)
TW (1) TW510015B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4579621B2 (en) * 2003-09-26 2010-11-10 パナソニック株式会社 Semiconductor device
CN1601735B (en) * 2003-09-26 2010-06-23 松下电器产业株式会社 Semiconductor device and method for fabricating the same
US6960836B2 (en) * 2003-09-30 2005-11-01 Agere Systems, Inc. Reinforced bond pad
KR100689857B1 (en) 2005-02-28 2007-03-08 삼성전자주식회사 Pad structure in semiconductor device
JP2006332533A (en) 2005-05-30 2006-12-07 Fujitsu Ltd Semiconductor device and its manufacturing method
JP5261926B2 (en) * 2006-12-08 2013-08-14 株式会社デンソー Semiconductor device and manufacturing method thereof
JP5034740B2 (en) 2007-07-23 2012-09-26 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US8053900B2 (en) * 2008-10-21 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect
JP5168265B2 (en) * 2009-11-02 2013-03-21 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
CN112687677A (en) * 2019-10-18 2021-04-20 凌通科技股份有限公司 Bonding pad for integrating electrostatic discharge circuit and integrated circuit using same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06196526A (en) * 1992-12-25 1994-07-15 Toyota Motor Corp Manufacture of semiconductor device
JPH08213422A (en) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp Semiconductor device and bonding pad structure thereof
JPH08293523A (en) * 1995-02-21 1996-11-05 Seiko Epson Corp Semiconductor device and its manufacture
KR19990048276A (en) * 1997-12-09 1999-07-05 윤종용 Semiconductor device with multi-layer pad and manufacturing method thereof
US5928088A (en) * 1998-04-15 1999-07-27 Matthews; David Paul Golf putter head
KR100319896B1 (en) * 1998-12-28 2002-01-10 윤종용 Bonding pad structure of semiconductor device and fabrication method thereof
KR20000009043A (en) * 1998-07-21 2000-02-15 윤종용 Semiconductor device having a multi-layer pad and manufacturing method thereof

Also Published As

Publication number Publication date
JP2002208610A (en) 2002-07-26
TW510015B (en) 2002-11-11
KR20020051816A (en) 2002-06-29
KR100421043B1 (en) 2004-03-04

Similar Documents

Publication Publication Date Title
US6552438B2 (en) Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same
JP5209224B2 (en) Method for manufacturing bonding pad structure of semiconductor element
KR100329407B1 (en) Electrode structure of semiconductor element
US6163074A (en) Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein
US6313537B1 (en) Semiconductor device having multi-layered pad and a manufacturing method thereof
US7312530B2 (en) Semiconductor device with multilayered metal pattern
EP1609179B1 (en) Internally reinforced bond pads
US9337090B2 (en) Semiconductor device
KR20000052334A (en) Semiconductor device
JP4297682B2 (en) Semiconductor device and manufacturing method thereof
JP3952260B2 (en) Bonding pads for integrated circuits
TWI287267B (en) Bonding pad structure of semiconductor device and method for fabricating the same
KR100284738B1 (en) Pad of semiconductor having multi metal line &amp; method for fabricating the same
US7777340B2 (en) Semiconductor device
WO2009042447A1 (en) A bonding pad structure allowing wire bonding over an active area in a semiconductor die and method of manufacturing same
JP2007214349A (en) Semiconductor device
TWI316741B (en) Method for forming an integrated cricuit, method for forming a bonding pad in an integrated circuit and an integrated circuit structure
US6921976B2 (en) Semiconductor device including an island-like dielectric member embedded in a conductive pattern
US7888802B2 (en) Bonding pad structure and manufacturing method thereof
JP2005123587A (en) Semiconductor device and its manufacturing method
KR100471171B1 (en) Bonding pad structure of a semiconductor device and a method of fabricating the same
KR20000009043A (en) Semiconductor device having a multi-layer pad and manufacturing method thereof
US8330190B2 (en) Semiconductor device
KR100505614B1 (en) Semiconductor device having multilayer pad structure and the manufacturing method thereof
JPH10154708A (en) Structure of pad of semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040830

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20061026

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061030

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070126

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070220

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070315

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070418

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100511

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100511

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110511

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120511

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130511

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees