JP3918274B2 - COMPILING DEVICE, COMPILING METHOD, AND RECORDING MEDIUM CONTAINING COMPILER PROGRAM - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention converts a source program into intermediate text, optimizes the converted intermediate text, and generates a program that effectively uses the data cache in a compiling device that generates machine language to improve runtime performance. The present invention relates to a compiling device.
[0002]
[Prior art]
The performance of computers has been dramatically improved by various technical improvements. In particular, the RISC (Reduced Instruction Set Computer) type architecture, in which the instruction execution speed is remarkably improved, is often adopted for the central CPU. On the other hand, the main memory (memory) is not so fast as compared with the CPU. In such a state, if data is loaded from the memory, it takes a long time (relative to the CPU) from the memory and is stored in the register for the operation. Results will be obtained after processing time. That is, the speeded-up CPU also has a slight improvement in overall performance because most of the processing of data in the memory waits for the load time from the memory to the register.
[0003]
In such a RISC type architecture, data used for calculation must be stored in a register, and an addressing method for specifying a memory as an operand of an operation instruction is not performed unlike a conventional general-purpose computer. . Also, when comparing the CPU time and the memory access time, if the machine cycle is τ, the operation time of the memory is tens of τ compared to most arithmetic instructions ranging from 1τ to several τ. It is. That is, most of the execution time is spent on the memory access waiting time (also referred to as latency).
[0004]
Reducing the delay time is a requirement for improving the performance of the RISC type architecture. In view of this, a data cache function has been devised for this purpose. The data cache function is provided with a cache memory having a fast access by hierarchizing memories, and is implemented in most of current CPUs. As the name suggests, the data cache temporarily stores the contents of the memory, and if it can be used repeatedly, the number of accesses to the stale memory can be reduced. However, instead of the data cache operating very fast, the capacity implemented is small.
[0005]
In the case where the primary cache, the secondary cache, and the memory are hierarchically arranged in the order from the CPU, the degree of delay time when there is a load request from the CPU is exemplified by the machine cycle time τ described above, the primary cache If data exists, it is 0τ, if it is in the secondary cache, it is accompanied by a copy to the primary cache, 10τ, and if there is requested data in the memory, it is accompanied by a copy to the primary / secondary cache and a delay time of 100τ. Become. In this way, when the load instruction is executed, the waiting time is less and the processing is performed faster as the target data exists in the hierarchy closer to the CPU.
[0006]
As described above, the conventional computer also has a cache memory that is quickly accessed by hierarchizing the memory, and speeding up the access to the data group on the memory that is repeatedly accessed has been realized. In addition, it is not only expected to increase the access speed for the data group on the memory that has been accessed once, but also the instruction with memory access that should be executed later by analyzing the instructions of the program that is actively executed. Thus, a device for copying data from a normal memory to a high-speed cache memory is also disclosed. For example, Japanese Patent Application Laid-Open No. 8-161226 discloses a data prefetch control method in a system using a cache memory, in which the type of load instruction is divided according to the type according to the arrangement pattern of the data to be accessed by the load instruction. When the load instruction is related to the previously issued load instruction so that it can be identified by a code etc., the load address of the subsequent load instruction is predicted according to the type of the load instruction when the preceding load instruction is processed. A technique for prefetching the data into the cache memory is shown.
[0007]
In the past, the use of data caches was promoted by detecting conditions that had the effect of prefetching in hardware during program execution. However, recently, the function of prefetching the memory contents into the data cache by software instructions, that is, data Computers with prefetch instructions have been developed. Utilization of a data cache using this data prefetch instruction is expected.
[0008]
[Problems to be solved by the invention]
As described above, the delay time due to waiting when loading data on the memory is remarkably reduced by the data cache for the data group that is repeatedly accessed, but there is no effect when it does not exist in the data cache. Some of the conditions shown in the above known example detect the effect expected by prefetching at the time of execution and prefetch data loaded in advance into the data cache. The cache's high-speed access cannot be effectively used.
[0009]
In the past, it was recommended to use data caches by detecting conditions that have the effect of prefetching in hardware during program execution. However, there are limited memory prefetching conditions that enable data caches that can be detected during execution. As a result, the incorporation of data cache utilization procedures at the program creation stage was an issue and a solution was sought.
[0010]
In view of these points, the present invention is a means for analyzing the characteristics of the program structure at the source program creation stage or the compilation stage and copying the memory contents necessary for the data cache prior to the load instruction. The purpose is to provide.
[0011]
[Means for Solving the Problems]
The above problem is solved by a compiling apparatus configured as follows.
FIG. 1 is a block diagram of the present invention.
[0012]
In the figure, reference numeral 1 denotes a compiling device that converts a source program into intermediate text, optimizes the converted intermediate text, and generates a machine language, corresponding to one or more types of preset source program instructions. An intermediate text search means for searching the converted intermediate text. 2 calculates the address of the memory to be copied to the data cache based on the searched intermediate text, and the above calculation is performed at the execution order position before the searched intermediate text. This is prefetch instruction insertion means for inserting a data cache prefetch instruction specifying an address. (Claim 1)
3 goes back to the control flow of the program based on the program execution time to be retroactively set in advance for each source program instruction type from the execution order position of the retrieved intermediate text, and determines the execution order position to insert the prefetch instruction. It is a prefetch instruction insertion position optimizing means for determining (claim 2).
[0013]
The compiling device is a compiling device for generating a program to be executed by a computer having a VLIW type architecture having a VLIW instruction configured by storing a plurality of simple instructions in a plurality of slots, and the prefetch instruction inserting means 2 is empty. When a data cache prefetch instruction is generated in a slot, 4 is a prefetch instruction insertion for setting whether to suppress insertion of a data cache prefetch instruction or to generate a new independent VLIW instruction when there is no empty slot Mode setting means (Claim 7).
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 2 is a configuration diagram of the embodiment of the present invention.
A compiling device 22 converts a source program indicated by the source program 21 into an intermediate text by the source program analysis unit 23, optimizes the converted intermediate text by the optimization execution unit 24, and generates scheduling and code. The unit 25 generates a machine language indicated by the object program 26. The generation and insertion control of the data cache prefetch instruction, which is a feature of the present invention, is performed by the optimization execution unit 24. The compiling device 22 operates on a computer.
[0015]
That is, in the present embodiment, a form realized by a computer program executed on a computer used for general purposes such as a personal computer or a workstation is shown.
[0016]
The compiling device of the present invention is realized by executing a computer program on a computer including a processing device, a main storage device, an auxiliary storage device, an input / output device, and the like. The computer program is stored and provided in a portable medium such as a floppy disk or CD-ROM, or in a main storage device or auxiliary storage device of another computer connected to the network. The recording medium of the present invention corresponds to the portable medium, the main storage device, and the auxiliary storage device.
[0017]
The provided computer program is loaded directly from the portable medium into the main storage device of the computer, or once copied or installed from the portable medium to the auxiliary storage device, then loaded into the main storage device and executed. In addition, when the data is stored and provided in another device connected to the network, it is copied to the auxiliary storage device after being received from the other device via the network, and loaded into the main storage device for execution.
[0018]
The mechanism and operation for inserting a data prefetch instruction will be described below with reference to the drawings and flowcharts.
FIG. 3 is an explanatory diagram of a data prefetch instruction. In FIG. 3A, “strcpy” (string copy, ie, a function for copying a character string) is taken as an example of a function for processing data on the memory, and the function is set at a position on the memory indicated by the address “ad2”. When the character string “a, b, c, d, e” 31 is present, it indicates that the character string “a, b, c, d, e” is to be copied to the memory 33 at the address “ad1” via the REG 32.
[0019]
FIG. 3B shows that the function “strcpy” is generated by the “LOAD instruction (1), (2)” generated by the source program analysis unit 23 of the compiling device 22 and the function “strcpy call instruction: CALL (4)”. Show. In other words, the two addresses ad1 and ad2 of the argument “CALL” are stored in REG1 and REG2, respectively, and intermediate text is generated so as to call the “strcpy” routine. Here, the intermediate text is an intermediate instruction that generates a machine instruction as an object program, and generally corresponds to a machine instruction. However, it also has information necessary for the processing steps after the compiling device. For example, information necessary for optimization includes “route information” indicating from which intermediate text control is passed.
[0020]
Here, “PREFETCH REG2” indicated by {circle over (3)} is a block of data on the memory including the address of the original character string to be copied as an argument of “strcpy call instruction: CALL <4>” in the corresponding data cache. Indicates copying. In this case, since it is known that the character data needs to be loaded from the memory into the register by “strcpy”, an instruction to be copied to the fast-access data cache is inserted before the load instruction is executed.
[0021]
That is, as shown in FIG. 3C, the character data indicated by REG2 is copied to the memory indicated by REG1 using the LOAD instruction and the STORE instruction using REG3. It is desirable that the portion including the contents of the memory accessed by the LOAD instruction has been copied to the data cache before the execution of the LOAD instruction. However, even if copying from the memory is in progress, the LOAD instruction is issued. When this is done, the effect of shortening the time can be surely obtained as compared with starting the operation of copying from the memory to the data cache anew. In other words, if the contents of the memory at the specified address are present in the data cache when the LOAD instruction is issued, the contents of the memory at the address specified by the LOAD instruction are first transferred to the data cache. It waits for completion and is loaded into the register. Therefore, if the transfer of data from the memory to the data cache is started by the PREFETCH instruction issued in advance, the data cache is loaded from the data cache to the register after completion of the transfer, so that the time can be shortened.
[0022]
FIG. 4 shows an explanatory diagram (part 1) of the intermediate text. Here, an example of a user function definition statement is shown as an image of a source program. foo () represents a user-defined function, and “... (1). Subsequently, the statement “... (2)...” Is executed when “if” satisfies the condition [then], and the statement “... (3). The function to be executed is defined by executing “... (4)...” After (2) or (3).
[0023]
The explanatory diagram (part 2) of the intermediate text in FIG. 5 shows the structure of the source program in FIG. 4 as a block diagram. Here, the ones indicated as entry / save at the first 51 and exit / restore at the last 56 are the registers used in the function to be defined, and the contents of the registers called global registers are In order to guarantee even after execution, the contents are saved in the memory at the entrance, and the contents saved at the exit are restored to the register. In other words, the contents of the global register have a specific meaning when each function is called, and are each promise to restore the contents when returning to the caller at the exit of the function. These “save” or “restore” are also called as functions.
[0024]
FIG. 6 is an explanatory diagram (part 3) of the intermediate text. The intermediate text generated corresponding to FIGS. 4 and 5 is shown in an assembler instruction level structure. Although not shown in detail, there is a “clause” in which a plurality of assembler instructions are difficult to unit in a source instruction sentence. These are “then clause”, “else clause”, and the like. Similarly, “evacuation” and “restoration” at the entrance and exit are recorded as a single process, together with information on the type of process and the flow of control.
[0025]
In order to distinguish and explain the intermediate text (command), a number is indicated by “#”, but the upward arrow shown there indicates a path indicating the original intermediate text (command) to which control of the intermediate text (command) is passed. Information. This is one of the information recorded by the source program analysis unit of the compiling device as necessary information in a later process, and the forward control flow is also recorded.
[0026]
Looking specifically at the correspondence, register saving prior to function execution (# 1, # 2), branching of if statement (# 3), post-processing in the then clauses (# 4, # 5, and # 6) ), Else clause (# 7, # 8), post-processing (# 9), restoration at function exit (# 10, # 11). Further, the upward arrow indicates the direction in which the control flow during execution is directed. The arrow from # 4 and # 7 points to # 3, but it corresponds to the fact that it is separated into two ways depending on the determination of the condition of the if sentence. Similarly, # 9 means that the control flow during execution is passed from # 6 or # 8.
[0027]
FIG. 7 is an explanatory diagram of a prefetch target processing table. In order for the optimization execution unit 24 shown in FIG. 2 to receive the intermediate text shown in FIGS. 4 to 6 from the source program analysis unit 23 and to find out that it is effective to insert a data prefetch instruction in advance, The processing name information recorded in the intermediate text as a key is listed and stored in the computer. As shown in FIG. 7, the type is a system function. Strcppy (character string copy), strncpy (character string copy specifying the number of characters), strlen (character string length), strcmp (character string comparison), memcpy ( Memory content copy), memcmp (memory content comparison), and the like. These are system functions that are processed after loading the data in the memory into the register, and are system functions whose execution time is greatly influenced by how short the load waiting time from the memory before processing is reduced. The target system function is registered in advance in this table.
[0028]
Similarly, fox, foo, and foo whose types are user-defined functions are user-defined functions that are processed after loading the data on the memory into the register, and only those that can be expected to be effective are registered in this table.
[0029]
If the type is register restoration, some types are registered as part of program development as a part of program development. As mentioned above, the register used to transfer contents in common as a global register is used for other purposes locally. The contents saved by itself are restored and the process is returned to the caller. That is, since the load from the memory to the register is always executed, it is desirable to prefetch the memory at the address accessed in advance and copy it to the data cache.
[0030]
When the type is user-specified prefetch, it is described in the source program and a hardware instruction that explicitly instructs prefetching is issued.
The list of arguments, the target argument of the load instruction, and the number of retroactive instructions are shown corresponding to each processing name in the prefetch target processing table. The address of the memory loaded in each process, that is, the address of the memory to be prefetched can be found by searching the argument position indicated by the target argument of the load instruction from the argument list. In addition, the number of retroactive instructions is the number of prefetch instructions ahead of each other, corresponding to how far the processing load instruction is executed from the beginning of the processing at the time of execution. Indicates what should be done. The numerical values shown here are recorded so as to correspond to the number of instructions to be inserted in order to insert an instruction at such a position. However, since the instruction execution time is slightly different for each instruction, that is, the time in units of machine cycles is different, the number of instructions is adjusted and set by each function.
[0031]
Next, FIGS. 8 and 9 are explanatory views (No. 1) and (No. 2) of empty slots and prefetch instruction arrangements of VLIW instructions. This is for explaining a form when the present invention is implemented in a computer having a VLIW architecture.
[0032]
A feature of the computer having the VLIW type architecture is that it has a VLIW instruction configured by storing a plurality of simple instructions in a plurality of slots. As a matter of course, a compiling device that generates a program to be executed by a computer having a VLIW architecture is used.
[0033]
First, as shown in FIG. 8 (a) VLIW instruction and slot, the VLIW instruction is an instruction having a plurality of slots, here, four slots, slot a to slot d, and instructions stored in each slot are executed simultaneously. Will come to be.
[0034]
FIG. 8B illustrates an instruction that can be stored together in one VLIW instruction by parallelizing instruction arrangement. First, in the case of a normal computer, a sequence of instructions executed in order is shown in (1). This is an instruction group for loading the data of address A and address B into registers REG1 and REG2, adding them with an ADD instruction to create a result in register REG3, and storing the result of REG3 into address C with a STORE instruction. Subsequently, in (2), instructions that can be executed in parallel are arranged horizontally, and instructions that require an order are arranged vertically. In other words, loads to REG1 and REG2 are separate registers and are not ordered and can be executed simultaneously, and instructions for storing additions and results thereof can be executed only after waiting for completion of the previous instruction in order. Indicates that is required. FIG. 8C shows an example in which the LOAD instructions that can be executed in parallel are stored in one VLIW instruction. Here, “NOP” stored in the slot b and the slot d is an instruction meaning No Operation, and is an instruction code to be filled when there is no instruction that can be executed in parallel and is unavoidably left as an empty slot.
[0035]
Next, the arrangement of prefetch instructions in FIG. The position where the prefetch instruction is inserted in the instruction sequence shown in FIG. 8B is after the LOAD instruction and before the ADD instruction as shown in (1). The result of inserting this as a VLIW instruction is shown in (2). That is, one VLIW instruction is inserted only for the PREFETCH instruction, but the above-described NOP instruction occupies many. Therefore, in the present invention, in the VLIW instruction, when there is already a NOP instruction, that is, there is a vacancy, the PREFETCH instruction is arranged and stored therein. The arrangement thus arranged is shown in FIG. By doing so, the effect of reducing the number of instructions and the instruction execution waiting time can be obtained. Conversely, in a loop or the like, an extra cost is required for inserting and adding one VLIW instruction, and a prefetch instruction can be inserted only when there is an empty slot. This is realized by the prefetch instruction insertion mode setting means 4 in FIG.
[0036]
FIG. 10 shows a prefetch instruction insertion flowchart. Here, the address of the data on the memory to be prefetched by finding a process effective to insert the prefetch instruction before the intermediate text as shown in FIG. 6 which is the output of the source program analysis unit 23 of FIG. 2 is input. A procedure for generating a prefetch instruction designating and inserting it at an optimum position will be described.
[0037]
In step S101, it is confirmed that a prefetch option is designated by the user as a compilation mode when compiling. In step S102, intermediate texts are extracted one by one in order. In step S103, in the intermediate text to check whether it is an intermediate text of the function call, the function is not “CALL” instruction or illustrated here as shown in FIG. 3B, but the type in FIG. Since the function name is expressed as an argument of the “pragm” instruction which is an extension instruction specified at the time of user-specified prefetch, this is taken out and examined.
[0038]
In step S104, the extracted function name is compared with the process name registered in the prefetch target process table of FIG. If it is not registered in the table, it is assumed that there is no effect even if a prefetch instruction is inserted, and nothing is performed and the process proceeds to step S107 and the next intermediate text process is performed.
[0039]
If it is in the table, the PREFETCH text is generated by examining the address specified in the prefetch instruction from the argument list of the function found in step S105 and the load instruction target argument. The arrangement of the generated PREFETCH text is optimized in a later step in step S106, and an insertion position is determined and the generated PREFETCH text is inserted. After that, the end is confirmed in step S107 and the process is ended.
[0040]
Finally, optimization of the prefetch instruction arrangement will be described with reference to FIGS. FIG. 11 and FIG. 12 show a prefetch instruction insertion position optimization flowchart (part 1) and part (part 2). The flowchart (part 2) is called from the flowchart (part 1) and shows the operation of the insertion position detection program.
[0041]
The prefetch instruction insertion position optimization flowchart (part 1) detects a function to insert a prefetch instruction as described above, and is a program that is called and started when a PREFETCH text to be inserted is generated and placed. It is. Accordingly, in step S111, the counter that gave the initial value 0 for counting the position of the intermediate text, the position to be inserted, and the number of retroactive instructions shown in the table of FIG. 7 corresponding to the function are set as arguments, and step S112. In FIG. 12, the PREFETCH text insertion position detection program shown in FIG. 12 is called. As shown in FIG. 6, since the insertion position follows a plurality of path information indicated by ↑, one or more prefetch instructions can be arranged. Therefore, the PREFETCH text insertion position detection program returns one or more pieces of position information. It is.
[0042]
In step S113, the generated PREFETCH text is placed at one or more insertion positions stored and returned.
The description of the flowchart of FIG. This is called when the prefetch instruction is arranged, and shows the processing procedure of the PREFETCH text insertion position detection program. This program traces the route information indicated by ↑ in FIG. 6 and stores the position as many as the number of instructions to be retroactively indicated as an argument as the optimum arrangement position. There is also text with a plurality of route information in the middle. However, in order to return to the position of the intermediate text having the closest plurality of route information and go to another route, in the step S126, a re-calling form for calling itself is used as described later.
[0043]
In step S121, the text position and counter address given as arguments are received. In step S122, the text position is incremented by one and 1 is added to the counter. In step S123, it is checked whether the counter has reached the number of retroactive instructions, that is, whether more prefetch instructions should be arranged. When it has been reached, in step S127, the text position at that time is accumulated and stored as the insertion position of the PREFETCH text and returned to the caller.
[0044]
In step S124, it is checked whether there is unprocessed route information in the current intermediate text. If not, exit this program and return to the caller.
If there is unprocessed path information, the unprocessed path information is extracted in step S125, and the current text position and the counter are used as arguments, ie, the PREFETCH text insertion position detection program so as to talk about the path extracted in step S126. call. Thus, every time a position satisfying the condition of step S123 is found over the branched path, it is accumulated and stored as the insertion position of the PREFETCH text in step S127. The stored PREFETCH text insertion position every time a target position is found through one path is fetched in step S113 when returning in response to the first call in FIG. 11, and the prefetch instruction is arranged based on it. Become. The return in step S126 searches for the next separated route in step S124.
[0045]
Although not shown in the flowchart, the counter is retroactive when the text cannot be further moved by the additional information recorded along with the path information of the intermediate text, for example, the head of the function definition or the intermediate text is a function call. It is handled that the number of instructions has been reached, and processing is performed so as to transfer control to step S127 in step S123.
[0046]
In this way, an effective prefetch instruction can be generated for each call of a function in which a prefetch instruction should be inserted with respect to the intermediate text, and can be inserted at an optimal position by tracing the possibility of a path at the time of execution.
[0047]
Even if the number of instructions struck by a user-defined function with a short step does not satisfy the number of retroactive instructions in the table of FIG. 7 and the optimization layout is not perfect, as described above, The effect that the completion waiting time for the completion of copying from the memory to the data cache becomes smaller can be expected. In extreme terms, even if the prefetch instruction is placed immediately before the function to be inserted, the effect can be obtained.
[0048]
In addition, it is a normal means for the program creator to describe the prefetch instruction at an appropriate position in the source program at the source program creation stage to obtain the effect of improving the built-in execution performance. FIG. There is also a method of incorporating by user-specified prefetch in the prefetch target processing table.
[0049]
【The invention's effect】
As is clear from the above description, according to the present invention, it is possible to analyze the characteristics of the structure of the program at the compilation stage and copy the memory contents necessary for the data cache prior to the load instruction. Thus, there is a significant industrial effect of improving the instruction execution performance of the computer by improving the hit rate of the data cache or reducing the waiting time for copying from the memory to the data cache.
[Brief description of the drawings]
FIG. 1 is a block diagram of the present invention.
FIG. 2 is a configuration diagram of an embodiment of the present invention.
FIG. 3 is an explanatory diagram of a data prefetch instruction.
FIG. 4 is an explanatory diagram of intermediate text (part 1).
FIG. 5 is an explanatory diagram of intermediate text (part 2).
FIG. 6 is an explanatory diagram of intermediate text (part 3).
FIG. 7 is an explanatory diagram of a prefetch target processing table.
FIG. 8 is an explanatory diagram of empty slots of VLIW instructions and prefetch instruction arrangement (part 1).
FIG. 9 is an explanatory diagram of empty slots of VLIW instructions and arrangement of prefetch instructions (part 2)
FIG. 10 is a flowchart for inserting a prefetch instruction.
FIG. 11 is a flowchart of optimizing the prefetch instruction insertion position (part 1).
FIG. 12 is a flowchart of optimizing the prefetch instruction insertion position (part 2).
[Explanation of symbols]
1 Intermediate text search means
2 Prefetch instruction insertion means
3 Prefetch instruction insertion position optimization means
4 Prefetch instruction insertion mode setting means

Claims (6)

A compiling device for optimizing an intermediate text stored by converting a source program by inserting a prefetch instruction from the memory into the data cache at a preceding execution order position corresponding to the load processing instruction from the memory to the register Because
Execution of inserting a prefetch instruction to be executed prior to the processing corresponding to the processing name of the processing name information recorded in the intermediate text by converting the source program instruction with respect to one or more source program instructions set in advance A prefetch target processing table that stores the number of instructions that are determined by retroactively counting the sequential positions along the execution path information stored in the intermediate text;
For each processing instruction of the intermediate text converted and stored from the original program, the processing name is searched for a match with any of the processing names stored in the prefetch target processing table, and the prefetch corresponding to the matching processing name is searched. Intermediate text search means for temporarily storing the number of retroactive instructions stored in the target processing table;
The control flow of the program is traced back along the execution path information stored in the intermediate text based on the number of retrospectively stored instructions from the execution order position of the processing instruction of the intermediate text whose search name matches the search. , Prefetch instruction insertion position optimization means for determining an execution order position for inserting the prefetch instruction;
Prefetch instruction insertion means for inserting a data cache prefetch instruction designating an address of a memory to be loaded by the processing instruction of the intermediate text whose processing name is matched by the search at the determined execution order position;
A compiling device comprising:   2. The compiling apparatus according to claim 1, wherein the source program instruction preset in the prefetch target processing table is a system function that specifies an address of data to be loaded from a memory to a register as an argument.   2. The compiling apparatus according to claim 1, wherein the source program instruction preset in the prefetch target processing table is a user-defined function that specifies an address of data to be loaded from a memory to a register as an argument.   The primitive program instruction preset in the prefetch target processing table is a register restoration function that specifies an address of data to be loaded from a memory in a program describing a procedure and a user-defined function as an argument. 1. The compiling device according to 1. A compiling method for optimizing an intermediate text stored by converting a source program by inserting a prefetch instruction from the memory into the data cache at a preceding execution order position corresponding to the load processing instruction from the memory to the register Because
Execution of inserting a prefetch instruction to be executed prior to the processing corresponding to the processing name of the processing name information recorded in the intermediate text by converting the source program instruction with respect to one or more source program instructions set in advance A storage unit stores in the prefetch target processing table the number of instructions that are determined by retroactively counting the sequential positions along the execution path information stored in the intermediate text.
The search means searches for a match with one of the process names stored in the prefetch target process table for each process instruction of the intermediate text converted and stored from the source program, and corresponds to the matched process name. An intermediate text search step in which the storage means temporarily stores the number of retroactive instructions stored in the prefetch target processing table;
The control flow of the program is traced back along the execution path information stored in the intermediate text based on the number of retrospectively stored instructions from the execution order position of the processing instruction of the intermediate text whose search name matches the search. A prefetch instruction insertion position optimizing step in which the determining means determines an execution order position for inserting the prefetch instruction,
A prefetch instruction insertion step in which an insertion means inserts a data cache prefetch instruction specifying an address of a memory to be loaded by a processing instruction of an intermediate text whose processing name is matched by the search at the determined execution order position;
Compile method having A compiler program that optimizes an intermediate text stored by converting a source program by inserting a prefetch instruction from the memory into the data cache at a preceding execution order position corresponding to the load processing instruction from the memory to the register A recording medium on which
Computer
Execution of inserting a prefetch instruction to be executed prior to the processing corresponding to the processing name of the processing name information recorded in the intermediate text by converting the source program instruction with respect to one or more source program instructions set in advance Means for storing in the prefetch target processing table the number of instructions that are determined by retroactively counting the sequential positions along the execution path information stored in the intermediate text;
For each processing instruction of the intermediate text converted and stored from the original program, the processing name is searched for a match with any of the processing names stored in the prefetch target processing table, and the prefetch corresponding to the matching processing name is searched. Intermediate text search means for temporarily storing the number of retroactive instructions stored in the target processing table;
The control flow of the program is traced back along the execution path information stored in the intermediate text based on the number of retrospectively stored instructions from the execution order position of the processing instruction of the intermediate text whose search name matches the search. , Prefetch instruction insertion position optimization means for determining an execution order position for inserting the prefetch instruction,
Prefetch instruction insertion means for inserting a data cache prefetch instruction designating an address of a memory to be loaded by the processing instruction of the intermediate text whose processing name is matched by the search at the determined execution order position;
A computer-readable recording medium in which a program for functioning as a computer is recorded.

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