JP3861236B2 - Multiple coincidence detection circuit for associative memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an associative memory device, and more particularly to a multiple coincidence detection circuit that generates multiple detection signals at high speed.
[0002]
[Prior art]
FIG. 11 is a logic circuit diagram showing a configuration of a multiple coincidence detection circuit of a conventional content addressable memory device. The associative memory device shown in this figure includes, for example, an associative memory element group 50 having 256 associative memory elements provided corresponding to 256 entries, and 256 ANDs respectively arranged on the output side of each associative memory element. A circuit 51, an 8-bit counter 52, a decoder 53 for sequentially setting each signal obtained by decoding the counter output to 256 bits to a high level, and an OR circuit 54 for logically summing the high level outputs of the respective AND circuits 51; And a 2-bit counter 55 that counts when the output of the OR circuit 54 is at a high level. A conventional multiple coincidence detection circuit is constituted by circuits other than the associative memory element group 50.
[0003]
In the conventional associative memory device configured as described above, when search data is given to the associative memory element group 50, each associative memory element compares the held data with the search data, and the two data are identical. If it does, the search match signals M0, M1,... At high level are output. On the other hand, the 8-bit counter 52 (256 = 2)⁸) The 2-bit counter 55 is initialized.
[0004]
When the clock is supplied to the 8-bit counter 52, the decoder 53 sequentially sets each signal obtained by decoding the counter output to 256 bits to the High level, and outputs it to each AND circuit 51. Each AND circuit 51 sets the output to the high level when the high level decode signal and the search match signal are input, and the OR circuit 54 outputs the signal from the AND circuit 51 to the 2-bit counter 55. The 2-bit counter 55 counts when the output of the OR circuit 54 is at a high level, and when the count is counted two times, the output is set at a high level. That is, when two or more search coincidence signals are input, the upper bits of the 2-bit counter 55 are at a high level, so this signal is output as a multiple detection signal.
[0005]
[Problems to be solved by the invention]
The above-described conventional multiple match detection circuit sequentially searches for search match signals for a plurality of entries, and outputs multiple detection signals when two or more search match signals are confirmed. Since it takes time to determine the presence or absence of the memory, and the configuration of the 8-bit counter 52 and the decoder 53 differs depending on the number of entries, the development of an associative memory device having a different number of entries based on the associative memory device having a certain number of entries. However, there is a problem that reusability is difficult.
[0006]
[Means for Solving the Problems]
  The multiple coincidence detection circuit of the associative memory device according to the present invention has a plurality of associative memory elements each having retained data and outputting a retrieval coincidence signal when the retained data and the retrieved data coincide with each other. The input side has a plurality of search match lines for transmitting search match signals, and the output side has a search match lineCorresponded to eachWhen there are the same number of match detection lines and one search match signal is input via any of the search match lines, the search match lineCorresponding toOn other match detection lines exceptLowWhen two or more search match signals are input via any search match line, each of the two match detection circuits that set all match detection lines to the low level and one of the match detection circuits Each search of the first search match detection circuit that is inserted into the search match line and inverts the output side from the high level to the low level when the search match signal flows in any of the search match lines, and the other match detection circuit A second search match detection circuit that is inserted into the match line and inverts the output side from a high level to a low level when a search match signal flows through any of the search match lines, and each match detection of one match detection circuit A plurality of first AND circuits that are respectively inserted into the lines and take the logical product of the level on each match detection line and the output level of the second search match detection circuit, and each match detection line of the other match detection circuit Each inserted A plurality of second AND circuits that take the logical product of the levels on the respective match detection lines and the output levels of the first search match detection circuits, and NOR provided on the output side of the first and second AND circuits And when two or more search match signals are respectively input to any one of the two match detection circuits via any search match line, or to each of the two match detection circuits. When one search match signal is input via one of the search match lines, the outputs of the first and second AND circuits are set to the low level, and a multiple detection signal is output from the NOR circuit.
[0007]
  In the present invention,For example, when two or more search match signals are input to one match detection circuit via any search match line, all match detection lines on the output side of one match detection circuit are displayed. Low Level, and the output of the first AND circuit Low To level. On the other hand, the output level of the first search match detection circuit also depends on the input of the search match signal. High From level Low Invert to the level and the output of the second AND circuit Low To level. At this time, the outputs of the first and second AND circuits are Low Because of the level, a multiple detection signal is output from the NOR circuit. Also, when one search match signal is input to each of the two match detection circuits via any search match line, the respective outputs of the first and second AND circuits are Low The multiple detection signal is output from the NOR circuit.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
1 is a circuit diagram showing a configuration of a multiple coincidence detection circuit of an associative memory device according to Embodiment 1 of the present invention. In order to simplify the description, the associative memory device having four entries will be described.
The multiple match detection circuit of the first embodiment shown in FIG. 1 includes a match detection circuit 2 connected to four associative memory elements C0 to C3 constituting the associative memory element group 1 via search match lines M0 to M3, respectively. The NOR circuit 3 is connected to the coincidence detection circuit 2 via coincidence detection lines A0 to A3.
[0009]
The coincidence detection circuit 2 is connected to a switching N-type transistor Q01 disposed at the intersection of the search coincidence lines M0 to M3 and the coincidence detection lines A0 to A3, and is pulled up to the respective coincidence detection lines A0 to A3. And a diode-connected P-type transistor (●). The associative memory elements C0 to C3 described above each have retained data, and output a high level search match signal to the match detection circuit 2 via the search match lines M0 to M3 when they match the search data.
[0010]
As shown in the figure, the N-type transistor Q01 has a gate side connected to the search match lines M0 to M3, a drain side connected to the match detection lines A0 to A3, and a source side connected to the ground. Further, the N-type transistors Q01 are not arranged at the intersections of all the search match lines M0 to M3 and the match detection lines A0 to A3, but are arranged based on a certain rule. Explain the rules.
[0011]
Although one coincidence detection line has intersections with four search coincidence lines, the N-type transistors Q01... Are arranged except for one of the four intersections. The intersection with the search match line to be excluded is made different for all match detection lines. For example, the match detection line A0 is arranged at the intersection of the other search match lines M1, M2, and M3 except the search match line M0, and the match detection line A1 is the search match lines M0, M2, excluding the search match line M1 It is placed at the intersection with M3, and the match detection line A2 is placed at the intersection with the search match lines M0, M1, M3 excluding the search match line M2, and the match detection line A3 The search match lines M0, M1, and M2 are arranged at the intersections.
[0012]
The operation of the multiple match detection circuit of the first embodiment configured as described above will be described. First, the operation when only the data held in the associative memory element C0 matches the search data will be described. Next, the data held in the associative memory elements C0 and C1 match the search data. The operation will be described.
[0013]
Before the search operation, the search match lines M0 to M3 are at a low level, the match detection lines A0 to A3 are at a high level by pull-up, and the output of the NOR circuit 3 is at a low level. Here, when the search data is input and the search operation is completed, since the data held in the associative memory element C0 matches the search data as described above, only the search match line M0 becomes the high level, and the remaining search Match lines M1 to M3 remain at low level.
[0014]
At this time, the N-type transistors Q10, Q20, and Q30 are turned on when the search match line M0 becomes High level, and the remaining N-type transistors Q01 to QO3, Q12, Q13, Q21, Q23, Q31, and Q32 are turned off. It is left. As a result, the coincidence detection lines A1 to A3 connected to the N-type transistors Q10, Q20, and Q30 are at the low level, and the remaining coincidence detection lines A0 remain at the high level. Therefore, the output of the NOR circuit 3 is at the low level. It remains. Even if another search match line is at a high level, similarly, only one match detection line is at a high level, so that the output of the NOR circuit 3 is at a low level.
[0015]
Next, when the data held in the associative memory elements C0 and C1 match the search data, the search match lines M2 and M3 remain at the low level, and the search match lines M0 and M1 become the high level. At this time, the N-type transistors Q10, Q20, Q30 and Q01, Q21, Q31 are turned on, and all of the coincidence detection lines A0 to A3 connected to them are at the low level. For this reason, the output of the NOR circuit 3 is inverted to a high level and output as a multiple detection signal. Even in other combinations in which two or more of the search match lines M0 to M3 are at the high level, all of the match detection lines A0 to A3 are at the low level, so that the output of the NOR circuit 3 becomes the high level and is multiplexed as described above. A detection signal is output.
[0016]
Therefore, the coincidence detection circuit 2 of the multiple coincidence detection circuit has a coincidence coincidence detection line at a high level and a disagreement coincidence detection line at a low level only when one of the associative memory elements C0 to C3 is coincident. When two or more coincide, all coincidence detection lines A0 to A3 are at a low level. This is a circuit having a multiple match filter function of the search match lines M0 to M3, and can detect multiples with the all-value low level as a result of the multiple match filter.
[0017]
As described above, according to the first embodiment, it is possible to simultaneously detect search match signals of all entries regardless of the number of entries in the associative memory elements C0 to C3. The effect becomes more remarkable as the number of entries increases.
Further, the configuration of the coincidence detection circuit 2 is extremely regular, and circuits for different numbers of entries are diverted from already designed circuits and already designed layouts, that is, entries from an associative memory device having 4 entries as shown in FIG. It is easy to divert and reuse the associative memory device of the number 8, and it is possible to shorten the development period when developing the associative memory device having a different number of entries for a specific application.
[0018]
Embodiment 2. FIG.
The second embodiment is an associative memory device that uses two match detection circuits shown in FIG. 1 and expands from the number of entries 4 to the number of entries 8, and will be described below with reference to FIG. FIG. 3 is a circuit diagram showing the configuration of the multiple match detection circuit of the associative memory device according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same or equivalent part as Embodiment 1 demonstrated in FIG. 1, and description is abbreviate | omitted.
[0019]
The multiple match detection circuit shown in FIG. 3 includes one match detection circuit H1 connected to four associative memory elements C0 to C3 via search match lines M0 to M3, respectively, and the remaining four associative memory elements C4. To the other match detection circuit H2 connected to search match lines M4 to M7, respectively, and AND circuits 4 to 7 (first circuits) connected to one match detection circuit H1 via match detection lines A0 to A3. 1 AND circuit), AND circuit 8 to 11 (second AND circuit) connected to the other match detection circuit H2 via match detection lines A4 to A7, and AND circuits 4 to 7, respectively. N-type transistors for switching Q101 to Q104 (second search match detection circuit) disposed at the intersections of the match detection line A4_7 and the search match lines M4 to M7, and match detection connected to the AND circuits 8 to 11, respectively. For switching placed at the intersection of line A0_3 and search match lines M0-M3 Type transistors Q201 to Q204 (first search coincidence detection circuit), NOR circuit 3 to which outputs A01 to A31 and A41 to A71 of AND circuits 4 to 11 are connected, and coincidence detection lines A4_7 and A0_3, respectively. And a diode-connected P-type transistor (●).
[0020]
The positions of the N-type transistors Q01... Provided in the coincidence detection circuits H1 and H2 are the same as those of the coincidence detection circuit 2 shown in FIG. In the N-type transistors Q101 to Q104 and Q201 to Q204 described above, the gate side is connected to the search match lines M0 to M7, the drain side is connected to the match detection lines A0 to A7, and the source side is connected to the ground.
[0021]
The operation of the multiple match detection circuit of the second embodiment configured as described above will be described. First, the operation when only the data held in the associative memory element C0 matches the search data will be described, and then the operation when the data held in the associative memory elements C0 and C1 match the search data will be described. Further, the operation when the data held in the associative memory elements C0 and C4 and the search data match will be described.
[0022]
When the data held in the associative memory element C0 and the search data match, the match detection lines A0 to A3 on the match detection circuit H1 side are the same as those in the first embodiment, and only the match detection line A0 is at the high level. The coincidence detection lines A1 to A3 are at the low level, and the added coincidence detection line A4_7 remains at the high level. Also, the match detection lines A4 to A7 on the match detection circuit H2 side remain at the high level, and the added match detection line A0_3 is set to the low level when the N-type transistor Q201 is turned on by the high level of the search match line M0. Become. Here, when the outputs A01 to A31 and A41 to A71 of the AND circuits 4 to 11 are viewed, since both the input sides of the AND circuit 4 are at the High level, the output A01 becomes the High level, and the other AND circuits 5 11 to 11, since either one of the input sides is at the low level, the respective outputs A11 to A31 and A41 to A71 are at the low level. Therefore, the output of the NOR circuit 3 remains at the low level, and the multiple detection signal Is not output.
[0023]
  Next, when the data held in the associative memory elements C0 and C1 match the search data, the coincidence detection lines A0 to A3 on the coincidence detection circuit H1 side are all the same as in the first embodiment.LowThe added coincidence detection line A4_7 remains at the high level. The coincidence detection lines A4 to A7 on the coincidence detection circuit H2 side remain at the high level, and the added coincidence detection line A0_3 is low because the N-type transistors Q201 and Q202 are turned on by the high level of the search coincidence lines M0 and M1. Become a level. Here, looking at the outputs of the AND circuits 4 to 11, since either one of the input sides of all the AND circuits 4 to 11 is at a low level, the outputs A01 to A31 and A41 to A71 are low. Therefore, the output of the NOR circuit 3 is inverted from the low level to the high level and output as a multiple detection signal.
[0024]
Further, when the data held in the associative memory elements C0 and C4 and the search data match, the match detection lines A0 to A3 on the match detection circuit H1 side are only in the match detection line A0 as described above. The coincidence detection lines A1 to A3 are at the low level, and the added coincidence detection line A4_7 is turned to the low level when the N-type transistor Q101 is turned on by the high level of the search coincidence line M4. In addition, the match detection lines A4 to A7 on the match detection circuit H2 side are such that only the match detection line A4 is at the high level, the other match detection lines A5 to A7 are at the low level, and the added match detection line A0_3 is as described above. Similarly, the N-type transistor Q201 is turned on by the high level of the search match line M0 and becomes the low level. Looking at the outputs of the AND circuits 4 to 11, since either one of the input sides of the AND circuits 4 to 11 is at a low level, all the outputs A01 to A31 and A41 to A71 are at a low level. Therefore, the output of the NOR circuit 3 becomes a high level and is output as a multiple detection signal.
[0025]
As described above, in the second embodiment, when the number of entries is expanded from the associative memory device shown in the first embodiment, the number of circuit elements to be used is reduced to about ½ compared to the expansion method shown in FIG. Can do. Further, since the regularity for expansion is as high as in the first embodiment, it is easy to divert and reuse from the already designed circuit and layout, and in the case of developing an associative memory device having a different number of entries for a specific application. This has the effect of shortening the development period.
[0026]
In the second embodiment, the description is applied to the associative memory device having eight entries. However, the multiple match detection circuit of the second embodiment shown in FIG. May be combined according to the number of entries. For example, when applied to an associative memory device with 16 entries, a multiple match detection circuit is configured with two sets of basic circuits, and when applied to an associative memory device with 24 entries, multiple matches with three sets of basic circuits. A detection circuit is configured. In this case, since the output of the AND circuit increases, a corresponding NOR circuit is prepared.
[0027]
Embodiment 3 FIG.
In the third embodiment, the multiple coincidence detection circuit of the associative memory device is configured by a logic circuit, and will be described below with reference to FIG. FIG. 4 is a logic circuit diagram showing a configuration of a 4-bit multiple coincidence detection circuit of the associative memory device according to Embodiment 3 of the present invention.
[0028]
The 4-bit multiple coincidence detection circuit shown in FIG. 4 includes, for example, two multiple detection input circuits 21 and 22 and a multiple detection output circuit 23 provided on the output side of these multiple detection input circuits 21 and 22. ing. The multiple detection input circuit 21 includes an AND circuit 21a and an OR circuit 21b. When a high level search match signal Y1, Y2 is output from an associative memory element (not shown), the AND circuit 21a outputs the output Y5 to High. The OR circuit 21b sets the output Y6 to the high level and outputs it as a search match detection signal. When either one of the search match signals Y1 and Y2 is at a high level, the OR circuit 21b sets the output Y6 to a high level and outputs it as a search match detection signal.
[0029]
The other multiple detection input circuit 22 includes an AND circuit 22a and an OR circuit 22b as described above. When the two-input search match signals Y3 and Y4 are both at the high level, the AND circuit 22a outputs Y7. Is set to a high level and output as a search match multiple detection signal, while the OR circuit 22b sets the output Y8 to a high level and outputs it as a search match detection signal Y8. When either one of the search match signals Y3 and Y4 is at a high level, the OR circuit 22b sets the output Y8 to a high level and outputs it as a search match detection signal.
[0030]
The multiple detection output circuit 23 includes an AND circuit 23a and an OR circuit 23b each having an input terminal connected to outputs Y6 and Y8 on the multiple detection input circuits 21 and 22 side, and an output of the AND circuit 23a and the multiple detection input circuit 21 side. Is connected to the output Y5, and the OR circuit 23d is connected to the output of the OR circuit 23c and the output Y7 on the multiple detection input circuit 22 side. When either one of the output Y5 on the multiple detection input circuit 21 side or the output Y7 on the multiple detection input circuit 22 side is at a high level (search match multiple detection signal), the multiple detection input circuit 21 side output Y6 and multiple detection When both of the outputs Y8 on the input circuit 22 side are at a high level (search match detection signal), the OR circuit 23d sets the output Y9 to a high level and outputs it as a multiple detection signal. When either the output Y6 on the multiple detection input circuit 21 side or the output Y8 on the multiple detection input circuit 22 side is at the high level (search match detection signal), the OR circuit 23b sets the output Y10 to the high level to search. Output as coincidence detection signal.
[0031]
The operation of the 4-bit multiple match detection circuit configured as described above will be described with reference to the truth table shown in FIG.
First, a case will be described in which all four input bits (search match signals Y1 to Y4) are at a low level (search mismatch). In this case, since the multiple detection input circuits 21 and 22 are both composed of AND circuits 21a and 22a and OR circuits 21b and 22b, the multiple detection output circuit 23 outputs a low-level multiple detection signal Y9. Low level search match detection signal Y10 is output.
[0032]
Next, a case where only one bit of the four input bits is at the high level (search match) will be described. That is, of the four search match signals Y1 to Y4, for example, when only the search match signal Y1 is at the high level, the multiple detection input circuit 21 sets the output Y5 to the low level and the output Y6 to the high level to detect the search match. The signal is output to the multiple detection output circuit 23 as a signal. Since the search match signals Y3 and Y4 are both at the low level, the other multiple detection input circuit 22 sets the outputs Y7 and Y8 to the low level. Since only the output Y6 on the multiple detection input circuit 21 side is at the high level, the multiple detection output circuit 23 sets only the output Y10 to the high level and outputs it as a search match detection signal.
[0033]
When only the search match signal Y2 is at the high level, the multiple detection input circuit 21 sets the output Y5 to the low level and the output Y6 to the high level, and outputs it to the multiple detection output circuit 23 as the search match detection signal. . The other multiple detection input circuit 22 sets the outputs Y7 and Y8 to low level. At this time, since the output Y6 on the multiple detection input circuit 21 side is at the high level, the multiple detection output circuit 23 sets only the output Y10 to the high level and outputs it as a search match detection signal.
[0034]
When only the search match signal Y3 is at the high level, the multiple detection input circuit 21 sets both the outputs Y5 and Y6 to the low level, and the other multiple detection input circuit 22 sets the output Y7 to the low level and the output Y8 to the high level. And output to the multiple detection output circuit 23 as a search match detection signal. At this time, since the output Y8 on the multiple detection input circuit 22 side is at a high level, the multiple detection output circuit 23 sets only the output Y10 to a high level and outputs it as a search match detection signal.
[0035]
When only the search match signal Y4 is at the high level, the multiple detection input circuit 21 sets both the outputs Y5 and Y6 to the low level, and the other multiple detection input circuit 22 sets the output Y7 to the low level, as described above. The output Y8 is set to the high level and is output to the multiple detection output circuit 23 as a search match detection signal. At this time, since the output Y8 on the multiple detection input circuit 22 side is at a high level, the multiple detection output circuit 23 sets only the output Y10 to a high level and outputs it as a search match detection signal.
[0036]
As described above, when only one bit out of the four input bits is at the high level (coincidence detection), the output Y9 of the multiple detection output circuit 23 is at the low level and there is no multiple detection, while the output Y10 is It becomes a high level and a search match is detected.
[0037]
Next, a case where 2 bits out of the 4 input bits are at the high level (search match) will be described.
When the search match signals Y1 and Y2 are at the high level, the multiple detection input circuit 21 sets the output Y5 to the high level and outputs it as the search match multiple detection signal to the multiple detection output circuit 23. It outputs to the multiple detection output circuit 23 as a detection signal. Since the search match signals Y3 and Y4 are both at the low level, the other multiple detection input circuit 22 sets the outputs Y7 and Y8 to the low level. The multiple detection output circuit 23 sets the output Y9 to the high level and outputs it as the multiple detection signal because the outputs Y5 and Y6 on the multiple detection input circuit 21 side are both at the high level, and also sets the output Y10 to the high level and the search match detection signal. Output as.
[0038]
When the search match signals Y1, Y3 are at the high level, the multiple detection input circuit 21 sets the output Y5 to the low level and the output Y6 to the high level, and outputs it to the multiple detection output circuit 23 as the search match detection signal. The other multiple detection input circuit 22 sets the output Y7 to low level and the output Y8 to high level, and outputs it to the multiple detection output circuit 23 as a search match detection signal. Since the output Y6 on the multiple detection input circuit 21 side and the output Y8 on the multiple detection input circuit 22 side are both at the high level, the multiple detection output circuit 23 sets the output Y9 to the high level and outputs it as a multiple detection signal. Output Y10 is set to High level and output as a search match detection signal.
[0039]
When the search match signals Y1 and Y4 are at the high level, the multiple detection input circuit 21 sets the output Y5 to the low level and the output Y6 to the high level, and outputs it to the multiple detection output circuit 23 as the search match detection signal. The other multiple detection input circuit 22 sets the output Y7 to low level and the output Y8 to high level, and outputs it to the multiple detection output circuit 23 as a search match detection signal. Since the output Y6 on the multiple detection input circuit 21 side and the output Y8 on the multiple detection input circuit 22 side are both at the high level, the multiple detection output circuit 23 sets the output Y9 to the high level and outputs it as a multiple detection signal. Output Y10 is set to High level and output as a search match detection signal.
[0040]
Although the above three patterns are shown, in other cases, when 2 bits out of the 4 input bits are at the high level (search match), the outputs Y9 and Y10 of the multiple detection output circuit 23 are both at the high level, and the search match is found. Detection and multiple detection. When 3 bits out of the 4 input bits are at the high level, the outputs Y9 and Y10 of the multiple detection output circuit 23 are both at the high level as shown in the truth table of FIG. It becomes detection.
[0041]
As described above, in the third embodiment, the search match multiple detection signal and the search match detection signal are output when two or more search match signals are input, and the search match detection is performed when one search match signal is input. Multiple detection input circuits 21 and 22 for outputting signals, and when a search match multiple detection signal or two or more search match detection signals are input from the multiple detection input circuits 21 and 22, a multiple detection signal is output. When a search match detection signal is input, a multiple match detection circuit is configured with the multiple detection output circuit 23 that outputs the search match detection signal, so that the search match signal can be multiplexed at a high speed with a small number of logic circuits. There is an effect that it can be detected.
[0042]
Embodiment 4 FIG.
In the fourth embodiment, a 16-bit multiple match detection circuit is configured using the 4-bit multiple match detection circuit of the third embodiment. FIG. 6 is a logic circuit diagram showing a configuration of a 16-bit multiple coincidence detection circuit of the associative memory device according to Embodiment 4 of the present invention.
In the 16-bit multiple coincidence detection circuit shown in this figure, a combination of the multiple detection input circuits 21 and 22 and the multiple detection output circuit 23 shown in FIG. 4 is used as a basic circuit 30, and this basic circuit 30 is used as an associative memory element. 4 are arranged in accordance with the number (not shown) (16 bits), and multiple detection output circuits 23 (hereinafter referred to as “symbols”) used for the basic circuit 30 are provided on the output side of two basic circuits 30 each. 31 ”and“ 32 ”), and the same multiple detection output circuit 33 is provided on the output side of the two multiple detection output circuits 31 and 32.
[0043]
Of the two basic circuits 30 connected to one multiple detection output circuit 31, the output Y9 of one basic circuit 30 is connected to the OR circuit 31c of the multiple detection output circuit 31, and the output Y10 is the AND circuit 31a. And the output Y9 of the other basic circuit 30 is connected to the OR circuit 31d of the multiple detection output circuit 31, and the output Y10 is connected to the AND circuit 31a and the OR circuit 31b.
[0044]
Of the two multiple detection output circuits 31 and 32 connected to one multiple detection output circuit 33 provided on the output end side, the output Y91 of one of the multiple detection output circuits 31 is on the output end side. The output Y101 is connected to the AND circuit 33a and the OR circuit 33b, and the output Y91 of the other multiple detection output circuit 32 is connected to the multiple detection output circuit 33 on the output end side. Connected to the OR circuit 33d, the output Y10 is connected to the AND circuit 33a and the OR circuit 33b.
[0045]
In the 16-bit multiple match detection circuit configured as described above, when any one of the 16 search match signals is input, as in the third embodiment, an output is made. Only the output Y102 of the multiple detection output circuit 33 on the end side becomes High level and is output as a search match detection signal. When two or more search match signals are input, the output Y92 of the multiple detection output circuit 33 becomes a high level and is output as a multiple detection signal, and the output Y102 becomes a high level and is output as a search match detection signal. Is done.
[0046]
As described above, a multiple match detection circuit with an extended number of bits can be configured very easily, and multiple search match signals can be detected at high speed regardless of the expansion of the number of bits.
[0047]
Embodiment 5. FIG.
FIG. 7 is a block diagram showing the configuration of the multiple match detection circuit of the associative memory device according to the fifth embodiment of the present invention.
The multiple match detection circuit according to the fifth embodiment includes an effective data area detection circuit 40, an effective data area mask circuit 41, and an effective data detection circuit 42. When the signal in [n-1: 0] having an n-bit signal width is input to the valid data area detection circuit 40 described above, a bit “1” (search) indicating the first validity from the LSB side of the input signal. When the first "1" is detected by this search, an effective area signal m1 [n-1: 0] is generated up to that bit as an effective data area. The valid data area mask circuit 41 is an inversion logic of the valid area signal m1 [n-1: 0] of the valid data area detection circuit 40 with respect to an input signal in [n-1: 0] having an n-bit signal width. The product is taken to mask the signal in the valid data area and output as signal m2 [n-1: 0]. The valid data detection circuit 42 detects whether valid data is included in the signal m2 [n-1: 0] masked by the valid data area mask circuit 41, and outputs the result.
[0048]
Next, the operation of the multiple match detection circuit of the fifth embodiment will be described for the case of n = 8. Note that positive logic is used, and “1” on the bit is valid data and “0” is invalid data.
For example, when a signal in [7: 0] = 0010_0010 having a signal width of 8 bits is inputted, the valid data area detection circuit 40 first valid data from the LSB side, in this case, the first bit is valid data. Therefore, an effective area signal m1 = 0000_0011 is generated from the input signal in [7: 0] = 0010_0010 and output to the effective data area mask circuit 41. This valid data area mask circuit 41 takes the logical product of each bit of the input signal in [7: 0] = 0010_0010 and the inversion (1111_1100) of the valid area signal m1 = 0000_0011 to obtain a signal in the valid data area. Mask and output signal m2 [7: 0] = 0010_0000. That is, this output signal m2 [7: 0] is expressed by the following equation.
m2 [7: 0] = in [7: 0] & ￣ m1 [7: 0] (&: logical product, ￣: inverted)
On the other hand, the valid data detection circuit 42 searches whether or not “1” is included in the input signal m2 [7: 0]. In this case, two or more valid data are input to the input signal in [7: 0], the output signal out is set to “1” to notify that two or more valid data are included. This logic means taking the logical sum of individual bits of the input signal. That is, the output signal out is expressed by the following equation.
out = (m2 [7] | m2 [6] | m2 [5] | m2 [4] | m2 [3] | m2 [2] | m2 [1] | m2 [0]) (|: logical sum)
[0049]
Next, a case where the input signal is in [7: 0] = 0000_1000 will be described. In this case, since the third bit from the LSB side is valid data, the output of the valid data area detection circuit 40 is m1 [7: 0] = 0000_1111, and the output of the valid data area mask circuit 41 is m2 = 0000_0000. . Therefore, the valid data detection circuit 42 sets the output signal out to “0” and notifies that two or more valid data are not included in the input signal in [7: 0].
[0050]
The multiple coincidence detection circuit according to the fifth embodiment detects an area width from the LSB side of the input signal in [n-1: 0] having an n-bit signal width to the first valid data “1” to detect an effective area signal. m1 [n-1: 0] is generated, and the logical product of the inversion of the effective area signal m1 [n-1: 0] with respect to the input signal in [n-1: 0] is obtained. This generates a signal m2 [n-1: 0] by masking the signal, detects whether this masked signal m2 [n-1: 0] contains valid data, and outputs the result. Therefore, a multiple match detection circuit corresponding to the number of entries in the associative memory device can be easily provided.
[0051]
(Example 1)
Here, the configuration of the above-described valid data area detection circuit 40 will be specifically described. FIG. 8 is a circuit configuration diagram showing an example of an effective data area detection circuit of the multiple coincidence detection circuit.
In the figure, INV1_0 to INV1_7 are inverters to which signals in [0] to in [7] are respectively input. N1_0 to N1_7 are NMOS transistors. Among them, the NMOS transistor N1_0 has a source side connected to the internal node net_0, a gate side connected to the output terminal of the inverter INV1_0, and a drain side connected to the internal node net_1. The NMOS transistor N1_1 has a source side connected to the internal node net_1, a gate side connected to the output terminal of the inverter INV1_1, and a drain side connected to the internal node net_2.
[0052]
The NMOS transistor N1_2 has a source side connected to the internal node net_2, a gate side connected to the output terminal of the inverter INV1_2, and a drain side connected to the internal node net_3. The NMOS transistor N1_3 has a source side connected to the internal node net_3, a gate side connected to the output terminal of the inverter INV1_3, and a drain side connected to the internal node net_4. The NMOS transistor N1_4 has a source side connected to the internal node net_4, a gate side connected to the output terminal of the inverter INV1_4, and a drain side connected to the internal node net_5. The NMOS transistor N1_5 has a source side connected to the internal node net_5, a gate side connected to the output terminal of the inverter INV1_5, and a drain side connected to the internal node net_6. The NMOS transistor N1_6 has a source side connected to the internal node net_6, a gate side connected to the output terminal of the inverter INV1_6, and a drain side connected to the internal node net_7. The NMOS transistor N1_7 has a source connected to the internal node net_7, a gate connected to the output terminal of the inverter INV1_7, and a drain connected to the drain of the PMOS transistor P0.
[0053]
NO is an NMOS transistor, the source side is connected to the ground, the gate side is connected to the precharge terminal pc, and the drain side is connected to the internal node net_0. P0 is the above-described PMOS transistor. The source is connected to the power supply VDD, the gate is connected to the precharge terminal pc, and the drain is connected to the drain of the NMOS transistor N1_7. P1_0 to P1_7 are PMOS transistors, each source side is connected to the power supply VDD, each gate side is connected to the precharge terminal pc, and each drain side is connected to the internal nodes net_0 to net_7, respectively. INV2_0 to INV2_7 are inverters provided on the output side, and the input side is connected to the internal nodes net_0 to net_7, respectively.
[0054]
Next, the operation of the valid data area detection circuit described above will be described.
First, when the precharge signal line pc becomes low level, the NMOS transistor NO is turned off, and the PMOS transistor P0 and the eight PMOS transistors P1_0 to P1_7 are turned on. At this time, regardless of the values of the input signals in [7] to in [0], the internal nodes net_0 to net_7 are at the high level, and the output signals out [7] to out [0] of the inverters INV2_0 to INV2_7 are respectively low. Become a level.
[0055]
In the circuit 40, the values of the input signals in [7] to in [0] are determined while the precharge terminal pc is in the precharge state (low level), and then the precharge terminal pc is set to the high level. Then, a charge is accumulated in the internal nodes net_0 to net_7 through the NMOS transistor NO and the eight NMOS transistors N1_0 to N1_7, thereby forming a dynamic logic circuit that executes a logical operation.
[0056]
In this case, the NMOS transistor NO is turned on, the PMOS transistor P0 and the eight PMOS transistors P1_0 to P1_7 are turned off, and the outputs of the inverters INV1_0 to INV1_7 to which the input signals in [7] to in [0] are inputted. The output signals out [7] to out [0] of the inverters INV2_0 to INV2_7 are determined by the NMOS transistors N1_0 to N1_7 that are turned on according to the values.
[0057]
For example, when the input signal in [7: 0] = 0010_0010 described in FIG. 7 is input, the output signals of the inverters INV1_7 to INV1_0 are INV1 [7: 0] = 1101_1101. At this time, the NMOS transistors N1_0, N1_2 to N1_4, N1_6 and N1_7 are turned on, and the other NMOS transistors N1_1 and N1_5 are turned off. On the other hand, in the internal node net_0, since the NMOS transistor NO is turned on by the high level of the input terminal pc, the charge accumulated in the internal node net_0 is released and transitions to the low level.
[0058]
Since the NMOS transistor N1_0 is in the on state, the internal node net_1 is discharged through the NMOS transistor N1_0 and the NMOS transistor NO, and transits to the low level. In addition, since the NMOS transistor N1_1 is in the OFF state, the charge accumulated in the internal node net_2 is not released and remains at the high level in the internal node net_2. Furthermore, since the NMOS transistor N1_1 is in the off state, the internal nodes net_3 to net_7 are not discharged as in the case of the internal node net_2, and remain at the high level.
[0059]
As described above, the internal nodes net_0 and net_1 transition to the low level, and the other internal nodes net_2 to net_7 continue to maintain the high level. Therefore, the output signal out through the inverters INV2_7 to INV2_0 becomes [0000_0011], and the above-described valid [0000_0011], which is the same result as the area signal m1, is output.
[0060]
Next, a case where the input signal is in [7: 0] = 0000_1000 will be described.
In this case, the output signals of the inverters INV1_7 to INV1_0 are INV1 [7: 0] = 1111_0111. At this time, only the NMOS transistor N1_3 is turned off, and the other NMOS transistors are turned on. At this time, the charges accumulated in the internal nodes net_0 to net_3 are discharged through the NMOS transistor transistors N1_0 to N1_2 and the NMOS transistor NO and transit to the low level, and the NMOS transistors N1_3 are in the off state in the other internal nodes net_4 to net_7 Therefore, the charge is not released and remains at the high level. Accordingly, the output signal out output via the inverters INV2_7 to INV2_0 is [0000_1111], and [0000_1111], which is the same result as the above-described effective area signal m1, is output.
[0061]
Since the valid data area detection circuit 40 configured as described above is used as a member of the multiple coincidence detection circuit, the bit width can be easily expanded, and a highly integrated multiple coincidence can be incorporated into an associative memory device. A detection circuit can be configured.
[0062]
(Example 2)
In the second embodiment, the effective data area detection circuit of the first embodiment shown in FIG. 8 is divided into a plurality of parts, which will be described below with reference to FIG. FIG. 9 is a circuit configuration diagram showing an effective data area detection circuit according to the second embodiment. To simplify the description, a circuit to which signals in [0] to in [3] are input is an LSB side circuit, and a circuit to which signals in [4] to in [7] are input is an MSB side circuit. Called. Further, the PMOS transistors P0, P1_0 to P1_7, the NMOS transistors N0, N1_0 to N1_7, the eight inverters INV1_0 to INV1_7, and the eight inverters INV2_0 to INV2_7 are the same as those in the first embodiment, and thus detailed description thereof is omitted.
[0063]
The PMOS transistor P2 of the LSB side circuit has a source side connected to the power supply VDD, a gate side connected to the precharge terminal pc, and a drain side connected to the drain (net_c) of the NMOS transistor N1_3 on the MSB side. The internal node net_c is connected to the input side of the inverter INV3.
The NMOS transistor N2 of the MSB side circuit is connected to the output side of the inverter INV3 provided in the LSB side circuit, the source side is connected to the drain of the NMOS transistor N0, and the drain side is connected to the source (net_4) of the NMOS transistor N1_4 Has been.
[0064]
Next, the operation of the valid data area detection circuit according to the second embodiment will be described.
First, when the precharge terminal pc goes low, the NMOS transistor N0 is turned off, the PMOS transistor P0 and the eight PMOS transistors P1_0 to P1_7 are turned on, and the values of the input signals in [7] to in [0] are obtained. Regardless, the internal nodes net_0 to net_7 are at high level, and the output signals out [7] to out [0] are at low level. At this time, the internal node net_c of the LSB side circuit is also charged to the high level, the output terminal C of the inverter INV3 is at the low level, and the output signal C of the inverter INV3 is at the low level in the MSB side circuit. The NMOS transistor N2 is turned off.
[0065]
Here, when the input signal in [7: 0] = 0010_0010 is input, the NMOS transistors N1_0, N1_2 to N1_4, N1_6, and N1_7 are turned on as in the first embodiment, and the remaining two NMOS transistors N1_1, N1_5 Is turned off. At this time, in the LSB side circuit, as in the first embodiment, the internal nodes net_0 and net_1 transition to the low level, and the other internal nodes net_2, net_3 and net_c continue to maintain the high level. For this reason, the inverter INV3 holds the low level output signal C, and accordingly, the NMOS transistor N2 also holds the off state. In the MSB side circuit, since the NMOS transistor N2 is in the OFF state, the charges of all the internal nodes net_4 to net_7 are kept at the high level. Therefore, the output signal out through the inverters INV2_1 to INV2_7 becomes 0000_0011, and the same result as the effective area signal m1 = 0000_0011 shown in the fifth embodiment is output.
[0066]
Next, the case where the input signal in [7: 0] = 0000_1000 will be described. In this case, the output signals of the inverters INV1_7 to INV1_0 are INV1 [7: 0] = 1111_0111. At this time, in the LSB side circuit, only the NMOS transistor N1_3 is turned off, and the other NMOS transistors N1_0 to N1_2 are turned on. In addition, the charges accumulated in the internal nodes net_0 to net_3 are discharged through the NMOS transistor N0 and the NMOS transistors N1_0 to N1_2, and transit to the low level. Since the NMOS transistor N1_3 is in the off state, the internal node net_c is kept at the high level without being discharged. Accordingly, similarly to the above, the output signal C of the inverter INV3 is at the low level, and in the circuit on the MSB side, the NMOS transistor N2 keeps the off state, so the output signal out output through the inverters INV2_0 to INV2_7 is 0000_1111 Thus, the same result as the effective area signal m1 = 0000_1111 shown in the fifth embodiment is output.
[0067]
Next, the case where the output signal C of the inverter INV3 becomes valid will be described.
When the input signal in [7: 0] = 0001_0000, the output signals of the inverters INV1_7 to INV1_0 are INV1 = 1110_1111. In the LSB side circuit, all NMOS transistors N1_0 to N1_3 are turned on, and the internal nodes net_0 to net_3 and net_c release charges through the NMOS transistors N0 and N1_0 to N1_3, and become Low level. The output signal C of the inverter INV3 is at a high level, and in the MSB side circuit, the NMOS transistor N2 is turned on, and the charge accumulated in the internal node net_4 passes through the NMOS transistors N0 and N1_4 of the MSB side circuit. Released and transitions to low level. Since the NMOS transistor N1_4 is in the off state, the charges of the other internal nodes net_5 to net_7 continue to be held. Therefore, the output signal out through the eight inverters INV2_7 to INV2_0 is 0001_1111.
[0068]
As described above, according to the second embodiment, it is possible to provide a multiple coincidence detection circuit capable of high-speed processing by dividing this circuit even when the bit width becomes wide and the operation speed deteriorates. .
[0069]
  Embodiments as described above5The multiple coincidence detection circuit in FIG. 1 detects the area width from the LSB side to the first valid data “1” with respect to the input signal in [n−1: 0] having an n-bit signal width and detects the valid area signal m1 [n -1: 0] and masks the signal outside the invalid region by taking the logical product of each bit of the input signal in [n-1: 0] and its valid region signal m1 [n-1: 0] Generate signal m3 [n-1: 0], perform binary encoding on this masked input signal m3 [n-1: 0], and output signal m [m-1: 0] is output, a multiple match detection circuit corresponding to the number of entries in the associative memory device can be easily provided.
[0070]
Even if the valid data area detection circuit 40 shown in the first embodiment (FIG. 8) and the second embodiment (FIG. 9) is used, only the matching result on the LSB side is extracted when multiple matching occurs. Thus, it becomes possible to output an encoding result of an accurate address value.
[0071]
Embodiment 6 FIG.
FIG. 10 is a block diagram showing the configuration of the multiple match detection circuit of the content addressable memory device according to Embodiment 6 of the present invention. In addition, the same code | symbol is attached | subjected to the same or equivalent part as Embodiment 5 demonstrated in FIG. 7, and description is abbreviate | omitted.
[0072]
The multiple match detection circuit of the sixth embodiment includes a selection circuit 45, an effective data area detection circuit 40 to which an output signal of the selection circuit 45 is input, an output signal of the selection circuit 45 and an effective area of the effective data area detection circuit 40. The invalid data area mask circuit 43 to which the signal m1 [n-1: 0] is input and the m3 [n-1: 0] signal m3 [n-1: 0] of the invalid data area mask circuit 43 are subjected to binary encoding, and m bits An encoder circuit 44 that outputs a signal out [m-1: 0] having a signal width, an output signal of the selection circuit 45, and an effective area signal m1 [n-1: 0] of the effective data area detection circuit 40 are input. The valid data area mask circuit 41 and a data holding circuit 46 that holds the output signal m2 [n-1: 0] of the valid data area mask circuit 41 are included.
[0073]
The invalid data area mask circuit 43 described above masks the invalid area signal by taking the logical product of the bits of the input signal in [n-1: 0] and the valid area signal m1 [n-1: 0]. It is output as a signal m3 [n-1: 0]. The encoder circuit 44 performs binary encoding on the signal m3 [n-1: 0] masked by the invalid data area mask circuit 43 and performs a signal out [m-1: 0] having a signal width of m bits. Is output.
[0074]
The selection circuit 45 outputs an input signal in [n-1: 0] having an n-bit signal width, and the valid data “1” is contained in the signal m2 [n-1: 0] held in the data holding circuit 46. "Is included and output as a signal m4 [n-1: 0]. The data holding circuit 46 is composed of a memory element constituted by a flip-flop or the like, and has a function of holding the input signal m2 [n-1: 0] for a certain period.
[0075]
Next, the operation of the multiple match detection circuit of the sixth embodiment will be described for the case of n = 8. It is to be noted that positive logic is used, positive logic is used, “1” on the bit is valid data, and “0” is invalid data.
For example, when a signal in [7: 0] = 0010_0010 having an 8-bit signal width is input, the selection circuit 7 selects the input signal in [7: 0], and the effective data area detection circuit 40, the effective data The data is output to the area mask circuit 43 and the invalid data area mask circuit 41, respectively.
[0076]
At this time, since the valid data area detection circuit 40 is the first valid data from the LSB side, in this case, the first bit is valid data, the valid area signal m1 = 0000_0011 from the input signal in [7: 0] = 0010_0010 Is output to the invalid data area mask circuit 43. The invalid data area mask circuit 43 masks the invalid data area signal by ANDing each bit of the input signal in [7: 0] = 0010_0010 and each bit of the valid area signal m1 = 0000_0011, The signal m3 [7: 0] = 0000_0010 is output to the encoder circuit 44. The encoder circuit 44 executes binary encoding of the input signal m3 [7: 0] and outputs a signal out [2: 0] = 001. This “001” informs that there is valid data (search match signal) in the first bit of the input signal in [7: 0].
[0077]
On the other hand, the valid data area mask circuit 41 calculates the logical product of the individual bits of the input signal in [7: 0] = 0010_0010 and the inversion (1111_1100) of the valid area signal m1 = 0000_0011, and outputs the signal of the valid data area. And the output signal m2 [7: 0] = 0010_0000 is held in the data holding circuit 46. The selection circuit 45 selects when the signal m4 [7: 0] = 0010_0000 held in the data holding circuit 6 is input, and selects the valid data area detection circuit 40, the valid data area mask circuit 41, and the invalid data area mask circuit. Output to 43 respectively.
[0078]
The valid data area detection circuit 40 to which the signal m4 [7: 0] = 0010_0000 is input generates the valid area signal m1 = 0011_1111 (the fifth bit is the first valid data on the LSB side), and the invalid data area mask circuit The invalid data area mask circuit 43 logically ANDs the individual bits of the input signal m4 [7: 0] = 0010_0000 and the individual bits of the valid area signal m1 = 0011_1111, respectively. And the signal m3 [7: 0] = 0000_0010 is output to the encoder circuit 44. The encoder circuit 44 executes binary encoding of the input signal m3 [7: 0] and outputs a signal out [2: 0] = 101. In this case, it is notified that there is valid data (search match signal) in the fifth bit of the input signal in [7: 0].
[0079]
On the other hand, the valid data area mask circuit 41 performs an AND operation on the individual bits of the output signal m4 [7: 0] = 0010_0000 of the selection circuit 45 and the inversion (1100_0000) of the valid area signal m1 = 0011_1111. The data area signal is masked, and the output signal m2 [7: 0] = 0000_0000 is output to the data holding circuit 46. In the present embodiment, since the number of valid display bits included in the input signal in [7: 0] = 0010_0010 is 2, the output signal m2 [7: 0] of the valid data area mask circuit 41 is “0000_0000”. The calculation is terminated at that time. When the number of effective display bits included in the input signal in [7: 0] is N, the encoded value of the address from the LSB side is sequentially and accurately output by repeating the above calculation N times. It becomes possible.
[0080]
  Embodiments as described above6According to the present invention, only the LSB side matching result is extracted even when multiple matching occurs by using the effective data area detection circuit 40 shown in the first and second embodiments and only by increasing the number of small circuits. Thus, it is possible to sequentially output all the encoding results of accurate address values.
[0081]
【The invention's effect】
  As described above, according to the present invention,It has a plurality of search match lines that transmit search match signals on the input side, and has the same number of match detection lines respectively corresponding to the search match lines on the output side,When one search match signal is input via any search match line, the search match lineCorresponding toOn other match detection lines exceptLowWhen two or more search match signals are input via any search match line, all match detection lines are set to low level.TwoA coincidence detection circuit;Inserted into each search match line of one match detection circuit, and when the search match signal flows through any of the search match lines, the output side is High From level Low Inserted into each search match line of the first search match detection circuit that inverts to the level and the other match detection circuit, and when the search match signal flows through any of the search match lines, the output side High From level Low A second search match detection circuit that inverts to a level, and a logical product of the level on each match detection line and the output level of the second search match detection circuit inserted into each match detection line of one match detection circuit And a logical product of the level on each match detection line and the output level of the first search match detection circuit. Provided on the output side of the plurality of second AND circuits and the first and second AND circuitsSince a multiple coincidence detection circuit comprising a NOR circuit is used, it becomes possible to simultaneously detect search coincidence signals of all entries regardless of the number of entries in the associative memory element, thereby speeding up multiple retrieval processing. The effect becomes more remarkable as the number of entries increases. The configuration of the coincidence detection circuit is extremely regular. For circuits with different numbers of entries, the flow from the pre-designed circuit and pre-designed layoutFor re-useThis makes it easy to use and has the effect of shortening the development period when developing associative memory devices with different numbers of entries for specific applications.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a multiple match detection circuit of an associative memory device according to Embodiment 1 of the present invention;
FIG. 2 is a circuit diagram showing a configuration of a multiple match detection circuit of an associative memory device when the number of entries 4 is changed to 8. FIG.
FIG. 3 is a circuit diagram showing a configuration of a multiple match detection circuit of an associative memory device according to Embodiment 2 of the present invention;
FIG. 4 is a logic circuit diagram showing a configuration of a 4-bit multiple coincidence detection circuit of an associative memory device according to Embodiment 3 of the present invention;
FIG. 5 is a diagram showing a truth table of a multiple match detection circuit in the third embodiment.
FIG. 6 is a logic circuit diagram showing a configuration of a 16-bit multiple coincidence detection circuit of an associative memory device according to Embodiment 4 of the present invention;
FIG. 7 is a block diagram showing a configuration of a multiple match detection circuit of an associative memory device according to a fifth embodiment of the present invention.
FIG. 8 is a circuit configuration diagram showing an example of an effective data area detection circuit according to the fifth embodiment.
FIG. 9 is a circuit configuration diagram showing another embodiment of the valid data area detection circuit.
FIG. 10 is a block diagram showing a configuration of a multiple match detection circuit of an associative memory device according to a sixth embodiment of the present invention.
FIG. 11 is a logic circuit diagram showing a configuration of a multiple coincidence detection circuit of a conventional content addressable memory device.
[Explanation of symbols]
1 associative memory element group, 2, H1, H2 coincidence detection circuit, 3 NOR circuit,
21, 22 Multiple detection input circuit, 23, 31-33 Multiple detection output circuit,
30 basic circuit, 40 valid data area detection circuit, 41 valid data area mask circuit, 42 valid data detection circuit, 43 invalid data area mask circuit,
44 encoder circuit, 45 selection circuit, 46 data holding circuit.

Claims (7)

In an associative memory device having a plurality of associative memory elements each having holding data and outputting a search match signal when the holding data and the search data match,
The input side has a plurality of search match lines for transmitting the search match signals, and the output side has the same number of match detection lines respectively corresponding to the search match lines. When input via a search match line , the other match detection lines except for the match detection line corresponding to the search match line are set to low level, and two or more search match signals pass through any search match line. Two coincidence detection circuits that set all coincidence detection lines to low level,
A first search match detection circuit that is inserted into each search match line of one match detection circuit and inverts the output side from a high level to a low level when a search match signal flows through any of the search match lines;
A second search match detection circuit that is inserted into each search match line of the other match detection circuit and inverts the output side from a high level to a low level when a search match signal flows through any of the search match lines;
A plurality of first AND circuits that are inserted into the respective match detection lines of one match detection circuit and take the logical product of the level on each match detection line and the output level of the second search match detection circuit;
A plurality of second AND circuits that are inserted into the respective coincidence detection lines of the other coincidence detection circuit and take the logical product of the level on the respective coincidence detection lines and the output level of the first search coincidence detection circuit;
A NOR circuit provided on the output side of the first and second AND circuits,
When two or more search match signals are input to any one of the two match detection circuits via any search match line, or one search is made to each of the two match detection circuits. When the coincidence signal is input through any one of the search coincidence lines, the outputs of the first and second AND circuits are at a low level, and a multiple detection signal is output from the NOR circuit. The multiple coincidence detection circuit of the associative memory device. A multiple coincidence detection circuit for an associative memory device, wherein the multiple coincidence detection circuit according to claim 1 is used as a basic circuit, and the basic circuits are combined according to the number of associative memory elements. In an associative memory device having a plurality of associative memory elements each having holding data and outputting a search match signal when the holding data and the search data match,
When a search match signal from a predetermined number of associative memory elements is input and at least one (but less than a predetermined number) of search match signals are detected, a search match detection signal is output, and the predetermined number of associative memory elements A plurality of multiple detection input circuits that respectively output a search match detection signal and a search match multiple detection signal when detecting an input of the search match signal from
Connected to a plurality of multiple detection input circuits and outputs a search match detection signal when an input of one search match detection signal is detected. When an input of a plurality of search match detection signals is detected, a search match detection signal and a search are detected. A multiple detection output circuit that outputs a match multiple detection signal and outputs a search match detection signal and a multiple detection signal, respectively, when detecting the input of the search match detection signal and the search match multiple detection signal ;
A multiple coincidence detection circuit for an associative memory device comprising the plurality of multiple detection input circuits and the multiple detection output circuit as basic circuits, and the basic circuit and the multiple detection output circuits of the basic circuit combined in accordance with the number of associative memory elements. . In an associative memory device having a plurality of associative memory elements each having holding data and outputting a search match signal when the holding data and the search data match,
When a signal as a result of comparison between data held by each associative memory element and search data is input, the first search match signal is searched from the LSB side of the input signal, and the first search match signal is detected by this search Is an effective data area detection circuit that generates an effective area signal with the search match signal as an effective data area, and
An effective data area mask circuit for masking a signal on the effective data area side using the effective area signal for the input signal;
It is effective to search whether there is a search match signal in the input signal in the unmasked area, and to output a multiple detection signal assuming that two or more search match signals exist in the input signal when a search match signal is detected A multiple coincidence detection circuit for an associative memory device, comprising: a data detection circuit; In an associative memory device having a plurality of associative memory elements each having holding data and outputting a search match signal when the holding data and the search data match,
A selection circuit;
When the signal of the comparison result between the data held by each associative memory element and the search data is input through the selection circuit, the first search match signal is searched from the LSB side of the input signal, and the first search is performed by this search. An effective data area detection circuit that generates an effective area signal as an effective data area up to the search match signal when a match signal is detected;
An invalid data area mask circuit that masks signals outside the valid data area using the valid area signal with respect to the input signal from the selection circuit;
A search match signal discriminating circuit for discriminating and outputting a search match signal from the signal on the valid data region side extracted by the mask of the invalid data region mask circuit;
An effective data area mask circuit that masks a signal on the effective data area side using the effective area signal with respect to an input signal from the selection circuit;
A holding circuit that temporarily holds the signal masked by the effective data area mask circuit,
When the selection circuit holds a signal in the holding circuit, the selection circuit outputs the signal as an input signal to the valid data area detection circuit, the invalid data area mask circuit, and the valid data area mask circuit, and the valid data area detection circuit A multiple coincidence detection circuit for an associative memory device, wherein generation of an effective area signal is repeatedly performed until a search coincidence signal is detected in an input signal. The valid data area detection circuit includes:
A dynamic NAND circuit having a plurality of NMOS transistors connected in series;
Charge charge means for charging a power supply voltage to all source terminals of each NMOS transistor of the dynamic NAND circuit,
When a signal from each associative memory element is input to the dynamic NAND circuit with the ground side as the LSB, each NMOS transistor discharges the charge accumulated in the source terminal based on the input signal, and the first search match signal 6. The multiple coincidence detection circuit for an associative memory device according to claim 4 or 5, wherein: The charge charging means is provided corresponding to the search coincidence signal, the source side is connected to the power supply, the gate side is connected to the precharge terminal, and the drain side is connected to the source side of each NMOS transistor of the dynamic NAND circuit. 7. The associative memory device according to claim 6 , further comprising a PMOS transistor that charges a source voltage to each source side of the NMOS transistor when a low- level precharge signal is input to the precharge terminal. Match detection circuit.

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