JP3843103B2 - パルス幅制御回路 - Google Patents
パルス幅制御回路 Download PDFInfo
- Publication number
- JP3843103B2 JP3843103B2 JP2004014675A JP2004014675A JP3843103B2 JP 3843103 B2 JP3843103 B2 JP 3843103B2 JP 2004014675 A JP2004014675 A JP 2004014675A JP 2004014675 A JP2004014675 A JP 2004014675A JP 3843103 B2 JP3843103 B2 JP 3843103B2
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- Japan
- Prior art keywords
- delay
- signal
- circuit
- vco
- input
- Prior art date
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- Signal Processing For Digital Recording And Reproducing (AREA)
- Optical Recording Or Reproduction (AREA)
- Pulse Circuits (AREA)
Description
M,Nを各々「4」に変更し、f0を「34.56MHz」に変更すれば、式(3)より遅延量dtは「0.90nsec」とpsecオーダーの分解能となる。
2 ディレイライン
3 PLL回路
4 VCO
5 プログラマブルデバイダ
6 リファレンスデバイダ
7 位相比較器
8 ローパスフィルタ
12 ANDゲート
20、11、31 セレクタ
32 ORゲート
40 遅延セル
50 ディスク
51 EFMエンコーダ
52 パルス幅制御回路
54 ディスク記録制御回路
55 レーザー装置
101、102 インバータ
105、106、107、108 電流制御用トランジスタ
110 第1制御端子
111 第2制御端子
Claims (1)
- 遅延素子を複数段接続して入力信号を遅延させる第1及び第2の遅延回路と、
第1及び第2の遅延回路毎に各遅延素子段の出力信号のいずれかを選択して遅延信号として出力する第1及び第2のセレクタと、
各遅延回路毎に入力信号と前記遅延信号との論理演算を行う第1及び第2の論理回路を有し、第1の論理回路の出力信号を第2の遅延回路の入力信号とすると共に、第1及び第2の論理回路の一方を論理積回路とし他方を論理和回路とするパルス幅制御回路であって、
前記遅延回路は、
遅延素子を複数段リング状に接続して構成され、各段の遅延量が入力される制御電圧により制御されるVCOと、該VCOの出力信号もしくはその分周信号と基準信号もしくはその分周信号とを入力し両信号の位相を比較する位相比較器と、該位相比較器で検出された位相差に応じた前記制御電圧を発生するローパスフィルタと、前記VCOの遅延素子と同一構成の遅延素子を複数段接続して構成され、各段の遅延量が前記制御電圧により制御されるディレイラインと、を備え、
前記位相比較器に入力される前記VCOの出力信号もしくはその分周信号及び前記基準信号もしくはその分周信号の周波数を可変とすることを特徴とするパルス幅制御回路。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004014675A JP3843103B2 (ja) | 2004-01-22 | 2004-01-22 | パルス幅制御回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004014675A JP3843103B2 (ja) | 2004-01-22 | 2004-01-22 | パルス幅制御回路 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP07878998A Division JP3547983B2 (ja) | 1998-03-26 | 1998-03-26 | パルス幅制御回路及びディスク記録制御回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004194346A JP2004194346A (ja) | 2004-07-08 |
JP3843103B2 true JP3843103B2 (ja) | 2006-11-08 |
Family
ID=32768116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2004014675A Expired - Lifetime JP3843103B2 (ja) | 2004-01-22 | 2004-01-22 | パルス幅制御回路 |
Country Status (1)
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JP (1) | JP3843103B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7504872B2 (en) * | 2007-08-13 | 2009-03-17 | Nvidia Corporation | Generic flexible timer design |
US9374216B2 (en) * | 2013-03-20 | 2016-06-21 | Qualcomm Incorporated | Multi-wire open-drain link with data symbol transition based clocking |
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2004
- 2004-01-22 JP JP2004014675A patent/JP3843103B2/ja not_active Expired - Lifetime
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JP2004194346A (ja) | 2004-07-08 |
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