JP3811030B2 - Digital amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital amplifier, and more particularly to a PWM digital amplifier that converts an input analog signal into a PWM (Pulse Width Modulation) signal and amplifies it.
[0002]
[Prior art]
Various types of digital amplifiers have been proposed, but roughly divided into the following two types. That is, a system using a PWM signal and a system using a 1-bit signal represented by a ΔΣ modulation system. Among these, for a digital amplifier using a PWM signal, a method of obtaining a PWM signal by comparing an input analog signal with a reference signal composed of a triangular wave or a sawtooth wave is widely known.
[0003]
FIG. 7 is a diagram showing a conventional digital amplifier using the PWM modulation method. In the figure, 1 is an analog signal input terminal for inputting an analog signal, 2 is a variable resistor for adjusting the input level of the analog signal, 3 is an input amplifier, 4 is a limiter, and overmodulation by an excessive level analog signal is performed. To prevent. 5 is a reference wave generating circuit for generating a reference wave composed of a triangular wave such as a sawtooth wave, 6 is a comparator for comparing the output signal of the limiter with the reference signal and generating a comparison output (PWM signal), 7 is a driver, Is a switching amplifier and amplifies the PWM signal. Reference numeral 9 denotes an LPF which outputs the analog signal amplified by removing noise and drives the speaker 10.
[0004]
FIG. 8 is a diagram showing details of the limiter 4. In the figure, 1 is an operational amplifier, 2 and 3 are resistors, and 4 and 5 are Zener diodes that limit the output of the operational amplifier 1.
[0005]
[Problems to be solved by the invention]
In the method of preventing overmodulation using the limiter, for example, when a music signal having a relatively low average level and a relatively high peak level, such as classical music, is reproduced by an audio device having a small maximum output, When the volume is set so that a sound with a low signal level can be heard well, when the music signal having a peak level is input, the music signal is clipped by the limiter. In the region where the limiter operates, the output signal has a rectangular wave shape and generates harmonics (particularly odd-order harmonics). The distortion due to the harmonics may sound a little distorted with an analog amplifier, but the digital amplifier may lack a signal and generate large noise.
[0006]
Furthermore, in the method of inserting a limiter circuit or an ALC circuit (a circuit that detects the average value of a signal and controls the amount of amplification or attenuation of the signal) in the path of the analog signal before PWM, the operation timing is set or the limiter is effective. Is difficult to set and tends to be unnatural in nature.
[0007]
The present invention has been made in view of the above problems, and a digital amplifier that can obtain an output without noise and without unnaturalness even when a signal having a relatively high peak level is input. provide.
[0008]
[Means for Solving the Problems]
The present invention employs the following means in order to solve the above problems.
[0009]
Reference wave generating circuit for outputting a triangular reference wave, a level detector for detecting the level of an input analog signal, a delay circuit for delaying and outputting a level detection signal detected by the level detector , and the delay circuit A variable amplifier that adjusts the amplitude of the reference wave output from the reference wave generation circuit based on the level detection signal output from the signal, and a pulse width modulation signal by comparing the input analog signal and the output signal of the variable amplifier And a filter circuit for smoothing the pulse width modulation signal output from the comparator, the time constant of the delay circuit is small when the level of the input analog signal is increased, and the level of the input analog signal is decreased. When big.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a digital amplifier according to a first embodiment of the present invention. In the figure, 1 is an analog signal input terminal for inputting an analog signal, 2 is a variable resistor for adjusting the input level of the analog signal, and 3 is an input amplifier. A signal level detection circuit 41 detects the level of an analog signal and outputs a level detection signal of one level selected from several output levels according to the detected level. A timing circuit (delay circuit) 42 having a predetermined time constant has a short time constant when the analog signal rises and a long time constant when the analog signal falls. 43 is a variable amplifier with a control terminal, such as a VCA (voltage control amplifier), which amplifies the output of the reference wave generating circuit 5 with an amplification factor in accordance with the output signal of the signal level detecting circuit 4 1. Reference numeral 5 is a reference wave signal generating circuit for generating a reference wave composed of a triangular wave such as a sawtooth wave, 6 is a comparator for comparing the output signal 101 of the input amplifier with the reference signal 102 and generating a comparison output (PWM signal) 103, 7 Is a driver, and 8 is a switching amplifier, which amplifies the PWM signal. Reference numeral 9 denotes an LPF, which outputs the analog input signal amplified by removing noise and drives the speaker 10.
[0011]
2A and 2B are diagrams showing operation waveforms of the digital amplifier shown in FIG. 1. FIG. 2A is an input waveform of the comparator 6, and FIG. 2B is an amplitude of a reference wave signal input to the comparator. The output PWM signal waveform when the output is small, (c) is the output PWM signal waveform when the amplitude of the reference wave signal input to the comparator 6 is A and the output of the input amplifier 3 is large, and (d) is input to the comparator 6. This is an output PWM waveform when the amplitude of the reference wave signal is 2A and the output of the input amplifier 3 is large. The operation of the digital amplifier shown in FIG. 1 will be described below with reference to FIG.
[0012]
The analog signal input to the input terminal 1 is adjusted in level by the variable resistor 2, amplified by the input amplifier 3, and input to the comparator 6. The output signal of the input amplifier 3 is also input to the signal level detection circuit 41. The signal level detection circuit 41 outputs voltage signals in several stages according to the level of the output signal of the input amplifier 3, for example. The voltage signal is supplied as a control signal to the control terminal of the variable amplifier 43 with a control terminal via the timing circuit 42.
[0013]
On the other hand, the reference wave signal generated by the reference wave generating circuit 5 is supplied to the input terminal of the variable amplifier 43, and the variable amplifier 43 converts the reference wave signal with an amplification degree according to the level of the voltage signal appearing at the control terminal. Amplify.
[0014]
The comparator 6 compares the output signal 101 of the input amplifier 3 with the reference wave signal 102, converts the input analog signal into a PWM signal 103, which is a high-frequency pulse train, based on the comparison result, and outputs the PWM signal 103. The PWM signal 103 controls a switching amplifier 8 comprising power switching means via a driver 7. The PWM signal amplified by the switching amplifier 8 is converted into the analog signal 104 amplified through the LPF 9 to drive the speaker 10.
[0015]
Now, as shown in FIG. 2 (a), a level 101b of the input analog signal, when the level of the reference wave signal 102 is 102b includes obtaining a PWM modulated signal 103 a shown in FIG. 2 (b) Can do.
[0016]
However, when the level of the input analog signal increases to 101a shown in FIG. 2A, the pulses X1 and X2 are missing from the PWM signal, as shown in FIG. 2C. When such a missing pulse occurs, discontinuity occurs in the audio signal obtained by amplification by the switching amplifier 8 and smoothing by the LPF 9, and noise is generated. In particular, when the level of the input analog signal is much higher than the level of the reference wave signal, the missing of the pulse occurs in blocks over several cycles of the reference wave signal, generating a large noise.
[0017]
Therefore, when the level of the input analog signal 101 increases, the amplification level of the variable amplifier 43 is controlled based on the detection signal level from the signal level detection circuit 41, and the reference wave signal 102 level becomes the level of the input analog signal 101. Control not to drop below the level. The example of FIG. 2 shows an example in which the level of the reference wave signal is doubled (2A). At this time, the obtained PWM signal is shown in FIG.
[0018]
By the way, if only the level of the reference wave signal is doubled, the output level of the comparator 6 is naturally halved and the output level of the LPF 9 is also halved. As described above, when the output of the comparator 6 decreases and the amplification factor as an amplifier changes abruptly, the audio signal output from the speaker 10 becomes an unnatural signal for hearing.
[0019]
The timing circuit (delay circuit) 42 is a circuit provided to eliminate the unnaturalness in hearing. By providing this circuit, the level of the reference wave signal is adjusted by providing a time constant suitable for each rising edge when the level of the input analog signal 101 suddenly increases and when it falls rapidly, for example, a short time constant when rising and a long time constant when falling. It can be increased or decreased, thereby eliminating auditory unnaturalness associated with changes in amplification.
[0020]
FIG. 3 is a diagram showing details of the signal level detection circuit 41. In the figure, 41a is a full-wave rectifier circuit unit, and 41b is a signal level detection circuit unit, which detects the level of an input signal and selects a level detection signal of one level selected from several levels of output levels according to the detected level. Is output. R1, r2, r3, r4, r5 are resistors, D1, D2 are diodes, and A1, A2 are operational amplifiers. 32 and 33 are comparators, 34, 35 and 36 are resistors for adjusting the amplification degree, and 37 is an operational amplifier which synthesizes the outputs of the comparators 32 and 33 and amplifies them. Reference numerals 38 and 39 are reference voltage sources having different voltage values V1 and V2 (V1 <V2), respectively.
[0021]
The input signal amplified by the input amplifier 3 is full-wave rectified by the full-wave rectifier circuit unit 41 a and is input to the comparators 32 and 33. Comparators 32 and 33 compare the input signal voltage with reference voltages V1 and V2, respectively, and output an H level or L level output voltage according to the comparison result. The resistors 34, 35 and 36 and the operational amplifier 37 combine the outputs of the operational amplifiers 32 and 33 to generate a three-level level detection signal.
[0022]
That is, in each comparator, both the comparators 32 and 33 output the L level, only the comparator 32 outputs the H level, or both the comparators 32 and 33 output the H level according to the level of the input signal. An amplifier circuit including an operational amplifier 37 and resistors 34, 35, and 36 outputs a three-stage output voltage as a level detection signal according to the combination of the output levels of the comparators.
[0023]
FIG. 4 is a diagram showing details of the timing circuit (delay circuit). In the figure, D10 is a diode, R10 is a resistor, and C10 is a capacitor. The time constant when the input voltage Vin increases, that is, the time constant composed of the diode D10 and the capacitor C10 is set short, and the time constant when the input voltage Vin decreases, that is, the time constant composed of the resistor R10 and the capacitor C10 is set long. is there.
[0024]
FIG. 5 is a diagram showing a digital amplifier according to the second embodiment of the present invention. In the figure, 51 is a level detection circuit, 58 is an attenuator, 52 and 53 are comparators, 54 and 55 are NAND circuits 56 and 57, timing circuits, TR1 and TR2 are transistors, and R20, R21, and R22 are resistors. In the figure, the same parts as those shown in FIGS. 1 and 3 are denoted by the same reference numerals, and the description thereof is omitted.
[0025]
In the first embodiment, the amplitude of the reference wave signal generated by the reference wave generating circuit 5 is variably controlled by the variable amplifier 43. On the other hand, as shown in FIG. 5, the amplitude of the reference wave signal generated by the reference wave generating circuit 5 is set sufficiently large, and the amplitude is set to the resistors R20 and R21 and the transistor TR1, and the resistors R20 and R22 and the transistor. By attenuating using the attenuator composed of TR2, the amplitude of the reference wave signal can be variably controlled.
[0026]
FIG. 6 is a diagram showing details of the timing circuits (delay circuits) 56 and 57. In the figure, D11 is a diode, R11 is a resistor, and C11 is a capacitor. The time constant when the input voltage Vin decreases, that is, the time constant constituted by the diode D11 and the capacitor C11 is set short, and the time constant when the input voltage Vin increases, that is, the time constant constituted by the resistor R11 and the capacitor C11 is set long. is there.
[0027]
In the case of this embodiment, the transistors TRl and TR2 are turned on and off according to the level of the input signal, and the attenuation rate is determined by the combination of R20, R21 and R22. Since the signal rise / fall relationship is opposite to that in the first embodiment, that is, the base potential of the transistor TR1 or TR2 is lowered at the rise of the input signal, and the transistor is turned off. The direction of the diode D11 of the (delay circuit) is opposite to that of the timing circuit shown in FIG.
[0028]
As described above, according to the present embodiment, noise is not generated even when an input signal having a high peak level that is overmodulated at the peak, that is, a signal exceeding the limit output of the amplifier is input. It is possible to provide a digital amplifier that is not particularly required to lower the average audition level and that is particularly suitable for a small output amplifier. Furthermore, according to the present embodiment, since the amplitude of a simple triangular wave or sawtooth wave is controlled, it is more accurate than a conventional circuit using an ALC (Auto Level Control) circuit that adjusts a music signal having a complex waveform. The output can be adjusted, and distortion or noise can be further reduced.
[0029]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a digital amplifier capable of obtaining an output free from noise and without unnaturalness even when a signal having a relatively high peak level is input. Can do.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a digital amplifier according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating operation waveforms of a digital amplifier.
FIG. 3 is a diagram showing details of a signal level detection circuit.
FIG. 4 is a diagram showing details of a timing circuit.
FIG. 5 is a diagram illustrating a digital amplifier according to a second embodiment of the present invention.
FIG. 6 is a diagram showing details of a timing circuit.
FIG. 7 is a diagram illustrating a conventional digital amplifier using a PWM modulation method.
FIG. 8 is a diagram showing details of a limiter.
[Explanation of symbols]
1 Analog signal input terminal 2 Variable resistor 3 Input amplifier
4 Limiter 5 Reference Wave Generation Circuit 6 Comparator 7 Driver 8 Switching Amplifier 9 LPF
10 Speaker 30 Full-wave rectifier circuit 38, 39 Reference voltage source 41 Signal level detection circuit 41a Full-wave rectifier circuit section 41b Signal level detection circuit section 42, 56, 57 Timing circuit 43 Variable amplifier 51 Signal level detection circuit 58 Attenuator

Claims (3)

A reference wave generating circuit that outputs a triangular reference wave;
A level detector for detecting the level of the input analog signal;
A delay circuit for delaying and outputting the level detection signal detected by the level detector ;
A variable amplifier that adjusts the amplitude of the reference wave output from the reference wave generating circuit based on the level detection signal output from the delay circuit ;
A comparator that compares the input analog signal with the output signal of the variable amplifier and outputs a pulse width modulation signal;
A filter circuit for smoothing the pulse width modulation signal output by the comparator;
The time constant of the delay circuit is small when the level of the input analog signal increases and large when the level of the input analog signal decreases. A reference wave generating circuit that outputs a triangular reference wave;
A level detector for detecting the level of the input analog signal;
A delay circuit for delaying and outputting the level detection signal detected by the level detector ;
A variable attenuation factor attenuator for adjusting the amplitude of the reference wave output from the reference wave generation circuit based on the level detection signal output from the delay circuit ;
A comparator that compares the input analog signal and the output signal of the attenuator to output a pulse width modulation signal;
A filter circuit for smoothing a pulse width modulation signal output from the comparator is provided, and the time constant of the delay circuit is small when the level of the input analog signal increases and large when the level of the input analog signal decreases. Digital amplifier. The digital amplifier according to claim 1, wherein:
The level detector outputs a level detection signal of one level selected from a plurality of output levels according to the level of the detected input analog signal.

Images