JP3799166B2 - Manufacturing method of MOS type semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as a semiconductor integrated circuit on which two types of MOSFETs having different threshold voltages are mounted, and more particularly to a method for manufacturing a device including a nonvolatile memory cell.
[0002]
[Prior art]
Usually, a semiconductor integrated circuit equipped with a nonvolatile memory has a nonvolatile memory cell region and a peripheral circuit region, and a plurality of types of MOS transistors having different threshold voltages are arranged in the peripheral circuit region. Is done.
[0003]
FIGS. 3A to 3C and FIGS. 4A and 4B are cross-sectional views showing an example of a manufacturing process of a semiconductor integrated circuit equipped with a conventional nonvolatile memory.
[0004]
3 (a)-(c) and FIGS. 4 (a) and 4 (b), 100 is a Si substrate, 101 is a first transistor formation region for forming a first MOS transistor having a high threshold voltage, 102 Is a second transistor formation region for forming a second MOS transistor having a low threshold voltage, 103 is a nonvolatile memory cell formation region, 104 is an element isolation insulating film, 105 is a tunnel oxide film, and 106 is a floating gate electrode 107 is a bottom oxide film, 108 is an intermediate nitride film, 109 is a first oxide film formed by CVD and heat treatment, 110 is a resist mask, 111 is a gate insulating film of the first MOS transistor, and 112 is a gate of the second MOS transistor. Insulating film, 113 is a top oxide film of ONO film, 114 is a gate electrode of the first MOS transistor, 1 5 denotes a gate electrode of the second 2MOS transistor, 116 denotes a control gate electrode, respectively.
[0005]
First, in the process shown in FIG. 3A, an element isolation insulating film 104 for partitioning the Si substrate 100 into a first transistor formation region 101, a second transistor formation region 102, and a nonvolatile memory cell formation region 103 is formed. In the non-volatile memory cell formation region 103, a tunnel oxide film 105, a floating gate electrode 106, a bottom oxide film 107 of an ONO film, and an intermediate nitride film 108 of an ONO film are sequentially stacked.
[0006]
Next, in the step shown in FIG. 3B, an CVD method is used to form an HTO film having a thickness of about 6 nm, and then thermal oxidation is performed to form a thermal oxide film having a thickness of about 15 nm. A first oxide film 109 made of a laminated film is formed.
[0007]
Next, in the step shown in FIG. 3C, a resist mask 110 having an opening in the second transistor formation region 102 is formed, and etching is performed using the resist mask 110. Only a portion on the two-transistor formation region 102 is selectively removed.
[0008]
Next, in the step shown in FIG. 4A, a gate insulating film 112 having a thickness of about 5 nm is formed on the second transistor formation region 102 by thermal oxidation. At the same time, a second oxide film 112a having a thickness of about 2 nm is also formed between the first oxide film 109 and the substrate surface in the first transistor formation region 101. In the nonvolatile memory cell formation region 103, the nitride film 108 of the ONO film is oxidized to form a top oxide film 113. As a result, a gate insulating film 111 made of a stacked film of the second oxide film 112 a and the first oxide film 109 is formed in the first transistor formation region 101. However, in the first transistor formation region 101, the thickness of the first oxide film 109 is reduced when the substrate is subjected to acid cleaning, pre-furnace cleaning, etc. before performing the second thermal oxidation process. A typical thickness of the gate insulating film 111 is about 15 nm.
[0009]
Next, in the step shown in FIG. 4B, after depositing a polysilicon film on the substrate, it is patterned to form a gate electrode 114 of the first MOS transistor, a gate electrode 115 of the second MOS transistor, and a non-volatile property. A control gate electrode 116 of the memory cell is formed.
[0010]
That is, the first MOS transistor having a high threshold voltage has a thick gate insulating film 111 having a thickness of about 15 nm formed of a laminated film of the first oxide film 109 and the second oxide film 112a, and has a low threshold. The second MOS transistor having a value voltage has a thin gate insulating film 112 having a thickness of about 5 nm made of only an oxide film formed by the second thermal oxidation process. Due to the difference in thickness of the gate insulating film, two types of transistors that operate with different threshold voltages are arranged in the peripheral circuit.
[0011]
[Problems to be solved by the invention]
However, the semiconductor device having the conventional nonvolatile memory cell has the following problems.
[0012]
There is a problem in that variations in threshold voltage occur in the first transistor formation region 101 having the thick gate insulating film 111.
[0013]
However, there are variations that cannot be explained only by this cause. As a result of further experiments, the following data was obtained.
[0014]
FIG. 5B is a diagram showing Vg-Id characteristics of the conventional second MOS transistor on the high threshold voltage side. This figure shows Vg-Id characteristics for five types of substrate potentials Vsub with the substrate potential Vsub as a parameter. Here, as shown in the figure, some humps appear, and in particular, even in a sample with a substrate potential Vsub = 0 (actual use potential) where the hump is inconspicuous, humps occur when the differential characteristics are examined. I understood.
[0015]
The cause of such a hump is not necessarily clear, but it is presumed that it is due to the following cause.
[0016]
4A, when the second oxide film 112a of the first MOS transistor 101 is formed by thermal oxidation in the step shown in FIG. 4A, the boundary between the first transistor formation region 101 and the element isolation insulating film 104 region. The local thinning of the end portion of the second oxide film 112a occurs at this portion. As a result, another transistor (so-called edge transistor) having a lower threshold voltage at the both end portions than the other portions operates. Thereby, it seems that the hump of the Vg-Id characteristic has generate | occur | produced. In addition, it is considered that variations in threshold voltage also occur due to the breakdown voltage / reliability degradation of the gate insulating film 111 and the electric field concentration due to the shape of the boundary.
[0017]
The present invention has been made in view of such a point, and an object thereof is to form two MOS transistors having different threshold voltages on a common semiconductor substrate by changing the thickness of the gate insulating film. In the semiconductor device manufacturing method, the threshold voltage of the high threshold voltage MOS transistor is stabilized by establishing a process for improving the Vg-Id characteristics of the high threshold voltage MOS transistor. There is to plan.
[0018]
[Means for Solving the Problems]
The means taken by the present invention to achieve the above object is to realize two MOS transistors having different threshold voltages by changing the thickness of the gate insulating film, and after forming the thermal oxide film first. Then, a CVD oxide film is laminated, and then, a thermal oxide film of a MOS transistor having a thicker gate insulating film is laminated simultaneously with a thermal oxidation of the MOS transistor having a thinner gate insulating film.
[0019]
A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a first MOS transistor and a second MOS transistor having a threshold voltage lower than that of the first MOS transistor on a common semiconductor substrate. A first step of forming an element isolation region for partitioning a first region for forming the first MOS transistor and a second region for forming the second MOS transistor on the upper surface of the first MOS transistor; A second step of forming a first thermal oxide film on the first region and the second region by performing thermal oxidation; and a CVD oxide film on the first thermal oxide film by performing CVD. Performing a third step of selectively removing only a portion of the first thermal oxide film and the CVD film in the second region, and a second thermal oxidation. , The second territory The gate insulating film of the second MOS transistor made of the second thermal oxide film is formed, while the first thermal oxide film, the CVD film and the second thermal oxide film are stacked in the first region. And a sixth step of forming a gate electrode on each of the gate insulating films in the first and second regions, respectively.
[0020]
This method is considered to be because the thinning at the boundary between the gate insulating film of the first MOS transistor and the element isolation insulating film is suppressed, and the concentration of the electric field can be avoided, but the Vg-Id characteristic of the first MOS transistor. The hump in the can be eliminated, and variations in threshold voltage can be suppressed. Moreover, variation in threshold voltage can also be suppressed by suppressing deterioration in breakdown voltage and reliability in the gate insulating film of the first MOS transistor.
[0021]
In the manufacturing process of the semiconductor device, in the first step, a third region for forming a nonvolatile memory cell on the semiconductor substrate is also partitioned by the element isolation region. The method further includes: forming a tunnel insulating film and a floating gate electrode in the third region; and forming a stacked capacitor film including at least an oxide film and a nitride film on the floating gate electrode, In the third step, an oxide film of the stacked capacitor film is formed in the third region, and in the fifth step, a control gate electrode of a nonvolatile memory cell is formed on the capacitor stacked film. In addition, the number of manufacturing steps for forming a nonvolatile memory cell having a stacked capacitor film made of an ON film or ONO film on a common semiconductor substrate can be reduced.
[0022]
In the method of manufacturing the semiconductor device, the CVD oxide film can be densified by further including a step of performing an annealing process after the third step.
[0023]
In that case, the annealing treatment is preferably performed in a nitrogen atmosphere, and the temperature of the annealing treatment is preferably equal to or higher than the deposition temperature of the CVD oxide film.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIGS. 1A to 1C and 2A to 2C are cross-sectional views showing a manufacturing process of a semiconductor integrated circuit on which the nonvolatile memory according to this embodiment is mounted.
[0025]
1A to 1C and 2A to 2B, 1 is a first transistor formation region for forming a first MOS transistor having a high threshold voltage, and 2 is a low threshold value. Second transistor formation region for forming a second MOS transistor having a voltage, 3 is a nonvolatile memory cell formation region, 4 is an element isolation insulating film, 5 is a tunnel oxide film, 6 is a floating gate electrode, and 7 is bottom oxidation 8 is an intermediate nitride film, 10 is a first thermal oxide film formed by the first thermal oxidation, 11 is a CVD oxide film, 12 is a gate insulating film of the first MOS transistor, and 13 is a gate of the second MOS transistor. Insulating film, 14 is the top oxide film of ONO film, 16 is the gate electrode of the first MOS transistor, 17 is the gate electrode of the second MOS transistor, and 18 is the control gate. Electrode, 20 is a resist mask, 50 denotes a Si substrate, respectively.
[0026]
First, in the step shown in FIG. 1A, an element isolation insulating film 4 for partitioning the Si substrate 50 into a first transistor formation region 1, a second transistor formation region 2, and a nonvolatile memory cell formation region 3 is formed. Then, a tunnel oxide film 5, a floating gate electrode 6, a bottom oxide film 7 of an ONO film, and an intermediate nitride film 8 of an ONO film are sequentially stacked in the nonvolatile memory cell formation region 3.
[0027]
Next, in the step shown in FIG. 1B, the first thermal oxidation is performed at 850 ° C., and the first transistor having a thickness of about 12 nm is formed on the first transistor formation region 1 and the second transistor formation region 2. The thermal oxide film 10 is formed.
[0028]
Next, in the step shown in FIG. 1C, CVD is performed at 800 ° C. to form a CVD oxide film 11 made of an HTO film having a thickness of about 10 nm. At this time, in the nonvolatile memory cell formation region 3, since the top oxide film is on the intermediate nitride film 8 of the ONO film, almost no increase in film thickness due to thermal oxidation is observed, and the CVD oxide film 11 on the intermediate nitride film 8 is almost not observed. Only formed.
[0029]
Next, in the step shown in FIG. 2A, a resist mask 20 having an opening in the second transistor formation region 2 is formed, and etching is performed using the resist mask 20 to form the first thermal oxide film 10 and the CVD. Only a portion of the oxide film 11 on the second transistor formation region 2 is removed by wet etching.
[0030]
Next, in the step shown in FIG. 2B, a gate insulating film 13 made of a thermal oxide film having a thickness of about 5 nm is formed on the second transistor formation region 2 by thermal oxidation. At the same time, a second thermal oxide film 13a having a thickness of about 1 nm is also formed between the first thermal oxide film 10 and the substrate surface in the first transistor formation region 1. In the nonvolatile memory cell formation region 3, the nitride film 8 of the ONO film is oxidized to form a top oxide film 14. As a result, a gate insulating film 12 composed of a laminated film of the first thermal oxide film 10, the CVD film 11, and the second thermal oxide film 13a is formed in the first transistor formation region 1. However, in the first transistor formation region 1, when the substrate is subjected to acid cleaning, pre-furnace cleaning, and the like before the second thermal oxidation treatment, the first thermal oxide film 10 and the CVD oxide film 11 have a thickness. Since the reduction occurs, the final thickness of the gate insulating film 12 is about 15 nm.
[0031]
Next, in the step shown in FIG. 2C, after a polysilicon film is deposited on the substrate, annealing is performed in a nitrogen atmosphere at 800 ° C. for 30 minutes, for example. By this annealing, the CVD oxide film 11 formed by CVD is densified. Note that annealing may be performed at a high temperature of 800 ° C. or higher.
[0032]
Thereafter, the polysilicon film is patterned to form the gate electrode 14 of the first MOS transistor, the gate electrode 115 of the second transistor, and the control gate electrode 6.
[0033]
That is, the first MOS transistor having a high threshold voltage has a thick gate insulation having a thickness of about 15 nm formed of a laminated film of the first thermal oxide film 10, the CVD oxide film 11, and the second thermal oxide film 13a. The second MOS transistor having the film 12 and having a low threshold voltage has a thin gate insulating film 13 having a thickness of about 5 nm made of only the oxide film formed by the second thermal oxidation process. Due to the difference in thickness of the gate insulating film, two types of transistors that operate with different threshold voltages are arranged in the peripheral circuit.
[0034]
That is, the high threshold side MOS transistor includes a thick gate insulating film 12 having a thickness of about 15 nm formed of a laminated film of the first thermal oxide film 10, the CVD oxide film 11, and the second thermal oxide film 13a. The low threshold voltage side MOS transistor has a thin gate insulating film 13 having a thickness of about 5 nm made of only an oxide film formed by the second thermal oxidation process. Due to the difference in thickness of the gate insulating film, two types of transistors that operate with different threshold voltages are arranged in the peripheral circuit.
[0035]
According to the manufacturing method of this embodiment, in the step of forming the gate insulating films 12 and 13 of the two MOS transistors arranged in the peripheral circuit portion, unlike the conventional manufacturing method, first, the first thermal oxidation is performed. After the film 10 is formed, the CVD thermal oxide film 11 is formed. After that, in the second transistor formation region 2, thermal oxidation is also performed for the second time for forming the gate insulating film 13 of the second MOS transistor. At this time, the first transistor formation region 1 has a thickness of about A very thin second thermal oxide film 13a of 1 nm is formed.
[0036]
As a result, according to the method of the present embodiment, it was found that the Vg-Id characteristics of the formed high threshold voltage first MOS transistor 1 were improved.
[0037]
FIG. 5A is a diagram showing the Vg-Id characteristics of the high threshold voltage MOS transistor formed according to this embodiment. As shown in FIG. 5A, almost no hump appears compared to the Vg-Id characteristic of the conventional high threshold voltage side MOS transistor shown in FIG. Such a difference in the characteristics of the semiconductor device between the method of the present embodiment and the conventional method is more remarkable when the differential coefficient of the Vg-Id characteristic is compared, and the high threshold voltage is increased by the manufacturing method of the present embodiment. It was found that variations in the threshold voltage of the side MOS transistor were also suppressed.
[0038]
In the second thermal oxidation as described above, the cause of the difference in the Vg-Id characteristics shown in FIGS. 5A and 5B is not completely clarified, but the first transistor is formed. It is presumed that the thinning of the gate insulating film 12 at the boundary with the element isolation insulating film 4 in the region 1 is prevented, and the concentration of the electric field at this boundary is avoided.
[0039]
Further, the manufacturing method according to the present embodiment can suppress the deterioration of the breakdown voltage and the reliability of the gate insulating film 12 of the high threshold voltage side MOS transistor, and also suppress the variation of the threshold voltage. be able to.
[0040]
In the present embodiment, the case where the non-volatile memory cell formation region 3 is present on the Si substrate 20 has been described. However, the present invention is not limited to such an embodiment, and the non-volatile memory cell region is provided. The present invention can also be applied to semiconductor devices that are not. However, when the nonvolatile memory cells are provided on a common semiconductor substrate, the number of steps can be reduced as much as possible by using the manufacturing method of this embodiment.
[0041]
【The invention's effect】
According to the method for manufacturing a semiconductor device of the present invention, the method for manufacturing a semiconductor device in which the first MOS transistor on the high threshold voltage side and the second MOS transistor on the low threshold voltage side are provided on a common semiconductor substrate. First, when the first thermal oxide film is formed, the CVD oxide film is stacked, and then the thermal oxidation for forming the gate insulating film of the second MOS transistor is performed, the CVD oxide film of the first MOS transistor Since the second thermal oxide film is formed below the first MOS transistor, variation in threshold voltage can be suppressed by improving the Vg-Id characteristics of the first MOS transistor and suppressing deterioration of breakdown voltage and reliability. It became so.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a process until a CVD oxide film is formed in a manufacturing process of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a process after forming a CVD oxide film in a manufacturing process of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view showing a process until a second MOS transistor portion of a CVD oxide film is selectively removed in a conventional semiconductor device manufacturing process;
FIG. 4 is a cross-sectional view showing a process after a CVD oxide film is selectively removed in a manufacturing process of a conventional semiconductor device.
FIG. 5 shows Vg-Id characteristics of a high threshold voltage side MOS transistor in a semiconductor device according to an embodiment of the present invention, and Vg-Id characteristics of a high threshold voltage side MOS transistor in a conventional semiconductor device. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 1st transistor formation area 2 2nd transistor formation area 3 Non-volatile memory cell formation area 4 Isolation insulating film 5 Tunnel oxide film 6 Floating gate electrode 7 Bottom oxide film 8 of ONO film 8 Intermediate nitride film 10 of ONO film Thermal oxide film 11 CVD film 12 Gate insulating film (first MOS transistor)
13 Gate insulation film (second MOS transistor)
13a Second thermal oxide film 14 Top oxide film 16 of ONO film Gate electrode (first MOS transistor)
17 Gate electrode (second MOS transistor)
18 Control gate electrode 20 Resist mask 50 Si substrate

Claims (4)

A method of manufacturing a semiconductor device having a first MOS transistor and a second MOS transistor having a threshold voltage lower than that of the first MOS transistor on a common semiconductor substrate,
Forming a first region for forming the first MOS transistor on the upper surface of the semiconductor substrate and an element isolation region for partitioning a second region for forming the second MOS transistor;
A second step of performing a first thermal oxidation to form a first thermal oxide film on the first region and the second region;
A third step of performing CVD to form a CVD oxide film on the first thermal oxide film;
A fourth step of selectively removing only the portion in the second region of the first thermal oxide film and the CVD film;
A second thermal oxidation is performed to form a gate insulating film of the second MOS transistor composed of a second thermal oxide film in the second region, while the first thermal oxidation is performed in the first region. A fifth step of forming a gate insulating film of the first MOS transistor comprising a laminated film of a film, a CVD film, and a second thermal oxide film;
A sixth step of forming a gate electrode on each of the gate insulating films in the first and second regions ,
In the first step, the element isolation region also partitions a third region for forming a nonvolatile memory cell on the semiconductor substrate,
Before the second step, a step of forming a tunnel insulating film and a floating gate electrode in the third region, and a step of forming a stacked capacitor film including at least an oxide film and a nitride film on the floating gate electrode And further comprising
In the third step, an oxide film of the stacked capacitor film is formed in the third region,
In the fifth step, a control gate electrode of a nonvolatile memory cell is formed on the capacitor stacked film . In the manufacturing method of the semiconductor device according to claim 1 ,
A method of manufacturing a semiconductor device, further comprising a step of performing an annealing process after the third step. The method of manufacturing a semiconductor device according to claim 2 .
A method of manufacturing a semiconductor device, wherein the annealing treatment is performed in a nitrogen atmosphere. In the manufacturing method of the semiconductor device of Claim 2 or 3 ,
A method of manufacturing a semiconductor device, wherein the annealing temperature is equal to or higher than the deposition temperature of the CVD oxide film.

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