JP3772901B2 - コンピュータシステム - Google Patents
コンピュータシステム Download PDFInfo
- Publication number
- JP3772901B2 JP3772901B2 JP2004337022A JP2004337022A JP3772901B2 JP 3772901 B2 JP3772901 B2 JP 3772901B2 JP 2004337022 A JP2004337022 A JP 2004337022A JP 2004337022 A JP2004337022 A JP 2004337022A JP 3772901 B2 JP3772901 B2 JP 3772901B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- address
- instruction
- load
- store
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000872 buffer Substances 0.000 claims description 84
- 238000001514 detection method Methods 0.000 claims description 6
- 238000004364 calculation method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000012546 transfer Methods 0.000 description 9
- 238000006073 displacement reaction Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 230000000873 masking effect Effects 0.000 description 6
- 238000013519 translation Methods 0.000 description 6
- 230000007246 mechanism Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61K—PREPARATIONS FOR MEDICAL, DENTAL OR TOILETRY PURPOSES
- A61K47/00—Medicinal preparations characterised by the non-active ingredients used, e.g. carriers or inert additives; Targeting or modifying agents chemically bound to the active ingredient
- A61K47/30—Macromolecular organic or inorganic compounds, e.g. inorganic polyphosphates
- A61K47/32—Macromolecular compounds obtained by reactions only involving carbon-to-carbon unsaturated bonds, e.g. carbomers, poly(meth)acrylates, or polyvinyl pyrrolidone
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Pharmacology & Pharmacy (AREA)
- Medicinal Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Epidemiology (AREA)
- Life Sciences & Earth Sciences (AREA)
- Animal Behavior & Ethology (AREA)
- General Health & Medical Sciences (AREA)
- Public Health (AREA)
- Veterinary Medicine (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Memory System (AREA)
Description
本出願は、本出願の代理人に譲渡されている下記の出願に関連するものである。すなわち、ニューエン(Nguyen)その他による1991年7月8日出願の米国特許出願香号 07/727,058(代理人整理番号SP021)、「拡張可能RISCマイクロプロセサ・アーキテクチャ」(EXTENSIBLE RISC MICROPROCESSOR ARCHITECTURE )、及び′058 出願の継続出願である、1992年1月8日出願の出願番号07/817,809に関連する。上記出願の開示を参照することによって当該特許出願の明細書の記載内容が本明細書に組み込まれているものとする。
R4:=R3 +1 (2)
R3:=R5 +1 (3)
R7:=R3 op R4 (4)
この場合、一般的にアウト・オブ・オーダの命令了が可能であっても、第1命令の代入は第3命令の代入の後には完了できない。第1命令と第3命令がアウト・オブ・オーダで実行された場合、異常且つ不正な値がR3レジスタに残り、例えば第4命令が不正なオペレランド値を受け取るような事態が生じる。第3命令の結果は第1命令に対して「出力依存性」を有し、このコードシーケンスに於いて正しい出力値を得るためには第3命令は第1命令の後に完了しなければならない。従って、第3命令の結果が、計算にもっと時間の掛かるより古い命令によって上書きされる場合、第3命令の発行は待たなければならない。
デコードされた命令が資源競合を生じた場合、真の依存性を有する場合、あるいは未完了の命令に対して出力依存性を有する場合、イン・オーダ命令発行プロセサは命令のデコードを中止する。従って、後続する一つ又は複数の命令が実行可能であっても、プロセサは競合又は依存性を生じた命令の後に来るものを先読み(lookahead )処理できない。従来の解決策はデコーダを実行段階から分離して、命令が直ちに実行可能であるか否かにかかわらず命令のデコードを継続して行なえるようにすることである。この分離はデコード段階と命令段階の間に「命令ウィンドウ」と呼ばれるバッファを配置することによって実施される。先読みのために、プロセサは命令をデコードし、ウィンドウ中に場所がある限りデコードされた命令を命令ウィンドウに入れ、それと同時に、実行可能な命令(すなわち、資源競合又は依存性を持たない命令)を見出すためにウィンドウ中の命令を検査する。命令ウインドウは命令のプールとしての機能があり、この機能によってプロセサは先読みの能力を得る。この能力はウィンドウのサイズとプロセサの命令フェッチ・ユニット(IFU )の性能によって制約されるものである。これによって、各命令の最初のプログラム順序と無関係にウィンドウから発行できるので、命令のアウト・オブ・オーダ発行が可能となる。この場合、命令発行元に対する唯一の制約はプログラムが正常に動作することを保証するのに必要な制約である。
b) [R2]<-[R2]OR R4
但し、[x] はアドレスxに存在するメモリ・オペランドである。好適な実施例に於ける命令デコード・ユニット(図示せず)はこれらのCISC型命令を次のようにRISC型シーケンスに分解する。
Execute R1+Te mp ->R1
b) LOAD[R2]->Temp Register
Execute Temp OR R4->Te mp Register
STORE Temp Register to addrcss[R2]
このどちらの場合でも、DAFU230 はメモリ・オペランドのアドレスを計算するが、ロード及びストアは同じアドレスを共有しているので1個の命令バケット当たり一つのアドレス計算だけが必要である。CISC型命令をRISC型命令にデコーディングすることについての説明に関しては1992年3 月31日出願の米国特許出願番号07/857,599(代理人整理香号SP032 )「CISC型からRISC型命令への変換のためのアライメント並びにデコーディング」(CISC to RISC Instruction Translation Alignment and Decoding)を参照されたい。当該出願の開示を参照することによって本出願に含まれているものとする。
1バイト 0ビットマスク
2バイト アドレスが0で終わる場合、1ビットマスク
アドレスが01で終わる場合、2ビットマスク
アドレスが11で終わる場合、3ビットマスク
4バイト アドレスが00で終わる場合、2ビットマスク
アドレスが1又は10で終わる場合、3ビットマスク
8バイト 3ビットマスク
10バイト 4ビットマスク
更に、ロード・オペレーションが4ワード境界を越えるたびに、アドレス衝突が発生していることが仮定される。その理由は、ロードの最初のアドレスだけがストア・アドレスと比較されるので、アドレス衝突が検出されないことがあるからである。ハードウェア中で使用されるコンパレータの数を二倍に増やすことにより、この制約は削除できる。ストア・アドレスが4ワード境界を越えることがあれば、アドレス衝突は検出される。
例1:
オペレーション アドレス1 アドレス2 サイズ マスク
LOAD …1001 … 2バイト 2ビット
STORE …1000 …1011 4バイト 2ビット
ロード・アドレス1001がマスクなしに1000及び1011と比較された場合、ストアがバイト1000,1001、1010、及び1011に書き込んだとしても衝突は検出されない。2個のLSB がマスクされていれば、結果は次のようになる。
LOAD …1000 …
STORE …1000 …1000
例2:
オペレーション アドレス1 アドレス2 サイズ マスク
LOAD …0100 … 4バイト 2ビット
STORE …0001 …1000 8バイト 3ビット
3個のMSB がマスクされていれば、下記のアドレスが生成され、アドレス衝突が検出される。
LOAD …0000 …
STORE …0000 …1000
2個のLSB だけがマスクされているならば、下記のアドレスが生成され、アドレス衝突は検出されない。
LOAD …0100 …
STORE …0000 …1000
前述の如く、LSU205はキャッシュ要求を必要とする最大4個のロード命令と最大4個のストア命令のウィンドウから選択を行なうことができる。これらのロード及びストアはCCU110に対して互いに競合し、競合するロード及びストア間の選択は下記の如く行なわれる。
LSU205のオペレーション例
表AにLSU205のオペレーションを示すサンプル・プログラムを示す。プログラムはインテル486 (Intel 486 )の表記法で記述されている。3個のレジスタが使用され、それらはeax 、ebx 、そしてecx とラベルされている。ロードされ、ロード及び/ 又はストアされるデータは32ビット幅のデータであると仮定される。ブラケットにアドレス・ロケーションを示す。
(1)mov ebx,[ecx]
(2)dec ebx
(3)or[eax],ebx
(4)(size 16)mov ebx,[eax+3]
このコードの最初の行では、アドレスecx に格納されたデータがebx に移される。従って、この命令は一つのロード・オペレーションである。第2の命令ではレジスタebx にある値が減少され、この命令ではロードもストアも行なわれない。第3の命令はアドレスeax に格納されたデータ及びデータebx に対して論理和をとり、結果を[eax] に格納する。従って、このオペレーションではロードとストアの両方が行なわれる。最後に第4命令ではアドレスeax+3 に格納された16ビットのデータがebx に移動される。従って、この命令ではロード・オペレーションが行なわれる。
eax=0000 0100[0100]=0000 4321
[0104]=FFFF FFFF
ecx=0000 1201[1200]=6500 01FF
[1204]=FFFF FF87
表Aの命令の実行の結果を表Cに示す。
mov ebx,[ecx ] EBX <…[1201]=8765 0001
dec ebx EBX <…8765 0001-1=8765 0000
or[eax ], ebx EAX <…0000 4321or8765 0000=8765 4321
(SIZE 16)mov ebx,[eax+3 ] EBX <…[0100+3]= [0103]
=FF87 …>8765 FF87
次に、表Aの命令の実行の結果の詳細を説明する。
Claims (2)
- プログラムストリームを実行するためのマイクロコンピュータシステムであって、前記マイクロコンピュータシステムが、
(a)メモリシステムから命令をフェッチし、所定の複数の命令を命令バッファへ提供するための命令フェッチ・ユニットと、
(b)前記命令バッファからの前記複数の前記命令をアウト・オブ・オーダで実行するための実行ユニットであって、前記命令バッファ内の命令に関しては、アウト・オブ・オーダでメモリシステムにロード要求を行い、前記命令バッファ内の命令に関しては、イン・オーダでストア要求を行うように適応させたロードストア・ユニットを含む実行ユニットと、
を含み、
前記ロードストア・ユニットが、前記複数の前記命令の間にアドレス衝突が存在するかどうかを検出するアドレス衝突検出手段を含み、
前記アドレス衝突検出手段は、ロードに関わるロードすべきデータの最初のアドレスのみと、先行するストアに関わるストアすべきデータの最初のアドレス及び、最後のアドレスもしくはデータ長と、に基づいて、前記アドレス衝突の存在を検出することを特徴とするマイクロコンピュータシステム。 - 前記アドレス衝突検出手段は、ストアに関わる前記アドレスが有効でない場合には、前記アドレス衝突が存在すると仮定することを特徴とする請求項1記載のマイクロコンピュータシステム。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US95408492A | 1992-09-29 | 1992-09-29 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004306379A Division JP3772900B2 (ja) | 1992-09-29 | 2004-10-21 | コンピュータシステム |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004370411A Division JP3772902B2 (ja) | 1992-09-29 | 2004-12-22 | コンピュータシステム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005166046A JP2005166046A (ja) | 2005-06-23 |
JP3772901B2 true JP3772901B2 (ja) | 2006-05-10 |
Family
ID=25494898
Family Applications (28)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50906394A Expired - Lifetime JP3644959B2 (ja) | 1992-09-29 | 1993-09-03 | マイクロプロセッサシステム |
JP2000008267A Withdrawn JP2000148483A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008270A Pending JP2000148493A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008264A Pending JP2000148481A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008271A Pending JP2000148494A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008263A Withdrawn JP2000148480A (ja) | 1992-09-29 | 2000-01-17 | 要求管理方法 |
JP2000008268A Pending JP2000148491A (ja) | 1992-09-29 | 2000-01-17 | マイクロコンピュ―タシステム |
JP2000008265A Withdrawn JP2000148490A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008269A Pending JP2000148492A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008266A Withdrawn JP2000181708A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2002312519A Expired - Lifetime JP3588755B2 (ja) | 1992-09-29 | 2002-10-28 | コンピュータシステム |
JP2002312520A Expired - Lifetime JP3620530B2 (ja) | 1992-09-29 | 2002-10-28 | コンピュータシステム |
JP2002312518A Expired - Lifetime JP3627737B2 (ja) | 1992-09-29 | 2002-10-28 | コンピュータシステム |
JP2002312517A Withdrawn JP2003131870A (ja) | 1992-09-29 | 2002-10-28 | コンピュータシステム |
JP2004273803A Expired - Lifetime JP3772899B2 (ja) | 1992-09-29 | 2004-09-21 | コンピュータシステム |
JP2004306379A Expired - Lifetime JP3772900B2 (ja) | 1992-09-29 | 2004-10-21 | コンピュータシステム |
JP2004337022A Expired - Lifetime JP3772901B2 (ja) | 1992-09-29 | 2004-11-22 | コンピュータシステム |
JP2004370411A Expired - Lifetime JP3772902B2 (ja) | 1992-09-29 | 2004-12-22 | コンピュータシステム |
JP2005013797A Expired - Lifetime JP3772903B2 (ja) | 1992-09-29 | 2005-01-21 | コンピュータシステム |
JP2005043359A Expired - Lifetime JP3741144B2 (ja) | 1992-09-29 | 2005-02-21 | コンピュータシステム |
JP2005083005A Expired - Lifetime JP3741146B2 (ja) | 1992-09-29 | 2005-03-23 | コンピュータシステム |
JP2005124391A Expired - Lifetime JP3772905B2 (ja) | 1992-09-29 | 2005-04-22 | コンピュータシステム |
JP2005148862A Expired - Lifetime JP3741149B2 (ja) | 1992-09-29 | 2005-05-23 | コンピュータシステム |
JP2005181820A Expired - Lifetime JP3772907B2 (ja) | 1992-09-29 | 2005-06-22 | コンピュータシステム |
JP2005212306A Expired - Lifetime JP3852474B2 (ja) | 1992-09-29 | 2005-07-22 | コンピュータシステム |
JP2005239264A Expired - Lifetime JP3852475B2 (ja) | 1992-09-29 | 2005-08-22 | コンピュータシステム |
JP2005274178A Expired - Lifetime JP3815507B2 (ja) | 1992-09-29 | 2005-09-21 | コンピュータシステム |
JP2006195680A Expired - Lifetime JP3874022B2 (ja) | 1992-09-29 | 2006-07-18 | コンピュータシステム |
Family Applications Before (16)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50906394A Expired - Lifetime JP3644959B2 (ja) | 1992-09-29 | 1993-09-03 | マイクロプロセッサシステム |
JP2000008267A Withdrawn JP2000148483A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008270A Pending JP2000148493A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008264A Pending JP2000148481A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008271A Pending JP2000148494A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008263A Withdrawn JP2000148480A (ja) | 1992-09-29 | 2000-01-17 | 要求管理方法 |
JP2000008268A Pending JP2000148491A (ja) | 1992-09-29 | 2000-01-17 | マイクロコンピュ―タシステム |
JP2000008265A Withdrawn JP2000148490A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008269A Pending JP2000148492A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2000008266A Withdrawn JP2000181708A (ja) | 1992-09-29 | 2000-01-17 | コンピュ―タシステム |
JP2002312519A Expired - Lifetime JP3588755B2 (ja) | 1992-09-29 | 2002-10-28 | コンピュータシステム |
JP2002312520A Expired - Lifetime JP3620530B2 (ja) | 1992-09-29 | 2002-10-28 | コンピュータシステム |
JP2002312518A Expired - Lifetime JP3627737B2 (ja) | 1992-09-29 | 2002-10-28 | コンピュータシステム |
JP2002312517A Withdrawn JP2003131870A (ja) | 1992-09-29 | 2002-10-28 | コンピュータシステム |
JP2004273803A Expired - Lifetime JP3772899B2 (ja) | 1992-09-29 | 2004-09-21 | コンピュータシステム |
JP2004306379A Expired - Lifetime JP3772900B2 (ja) | 1992-09-29 | 2004-10-21 | コンピュータシステム |
Family Applications After (11)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004370411A Expired - Lifetime JP3772902B2 (ja) | 1992-09-29 | 2004-12-22 | コンピュータシステム |
JP2005013797A Expired - Lifetime JP3772903B2 (ja) | 1992-09-29 | 2005-01-21 | コンピュータシステム |
JP2005043359A Expired - Lifetime JP3741144B2 (ja) | 1992-09-29 | 2005-02-21 | コンピュータシステム |
JP2005083005A Expired - Lifetime JP3741146B2 (ja) | 1992-09-29 | 2005-03-23 | コンピュータシステム |
JP2005124391A Expired - Lifetime JP3772905B2 (ja) | 1992-09-29 | 2005-04-22 | コンピュータシステム |
JP2005148862A Expired - Lifetime JP3741149B2 (ja) | 1992-09-29 | 2005-05-23 | コンピュータシステム |
JP2005181820A Expired - Lifetime JP3772907B2 (ja) | 1992-09-29 | 2005-06-22 | コンピュータシステム |
JP2005212306A Expired - Lifetime JP3852474B2 (ja) | 1992-09-29 | 2005-07-22 | コンピュータシステム |
JP2005239264A Expired - Lifetime JP3852475B2 (ja) | 1992-09-29 | 2005-08-22 | コンピュータシステム |
JP2005274178A Expired - Lifetime JP3815507B2 (ja) | 1992-09-29 | 2005-09-21 | コンピュータシステム |
JP2006195680A Expired - Lifetime JP3874022B2 (ja) | 1992-09-29 | 2006-07-18 | コンピュータシステム |
Country Status (7)
Country | Link |
---|---|
US (5) | US5659782A (ja) |
EP (1) | EP0663083B1 (ja) |
JP (28) | JP3644959B2 (ja) |
KR (1) | KR100248903B1 (ja) |
DE (1) | DE69329778T2 (ja) |
HK (1) | HK1014780A1 (ja) |
WO (1) | WO1994008287A1 (ja) |
Families Citing this family (161)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4237417C2 (de) * | 1992-03-25 | 1997-01-30 | Hewlett Packard Co | Datenverarbeitungssystem |
KR100248903B1 (ko) * | 1992-09-29 | 2000-03-15 | 야스카와 히데아키 | 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템 |
US6735685B1 (en) * | 1992-09-29 | 2004-05-11 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
US5721857A (en) * | 1993-12-30 | 1998-02-24 | Intel Corporation | Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor |
US6378062B1 (en) * | 1994-01-04 | 2002-04-23 | Intel Corporation | Method and apparatus for performing a store operation |
US5694574A (en) * | 1994-01-04 | 1997-12-02 | Intel Corporation | Method and apparatus for performing load operations in a computer system |
US5717882A (en) * | 1994-01-04 | 1998-02-10 | Intel Corporation | Method and apparatus for dispatching and executing a load operation to memory |
US6021471A (en) * | 1994-11-15 | 2000-02-01 | Advanced Micro Devices, Inc. | Multiple level cache control system with address and data pipelines |
US5734874A (en) * | 1994-04-29 | 1998-03-31 | Sun Microsystems, Inc. | Central processing unit with integrated graphics functions |
US6279099B1 (en) * | 1994-04-29 | 2001-08-21 | Sun Microsystems, Inc. | Central processing unit with integrated graphics functions |
JP3164732B2 (ja) | 1994-07-04 | 2001-05-08 | 富士通株式会社 | データ処理装置 |
US5761475A (en) * | 1994-12-15 | 1998-06-02 | Sun Microsystems, Inc. | Computer processor having a register file with reduced read and/or write port bandwidth |
US5784586A (en) * | 1995-02-14 | 1998-07-21 | Fujitsu Limited | Addressing method for executing load instructions out of order with respect to store instructions |
US5745729A (en) * | 1995-02-16 | 1998-04-28 | Sun Microsystems, Inc. | Methods and apparatuses for servicing load instructions |
US5638312A (en) * | 1995-03-03 | 1997-06-10 | Hal Computer Systems, Inc. | Method and apparatus for generating a zero bit status flag in a microprocessor |
TW448403B (en) * | 1995-03-03 | 2001-08-01 | Matsushita Electric Ind Co Ltd | Pipeline data processing device and method for executing multiple data processing data dependent relationship |
US5802588A (en) * | 1995-04-12 | 1998-09-01 | Advanced Micro Devices, Inc. | Load/store unit implementing non-blocking loads for a superscalar microprocessor and method of selecting loads in a non-blocking fashion from a load/store buffer |
US5887152A (en) * | 1995-04-12 | 1999-03-23 | Advanced Micro Devices, Inc. | Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions |
US5625835A (en) * | 1995-05-10 | 1997-04-29 | International Business Machines Corporation | Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor |
US5761712A (en) * | 1995-06-07 | 1998-06-02 | Advanced Micro Devices | Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array |
US5778434A (en) | 1995-06-07 | 1998-07-07 | Seiko Epson Corporation | System and method for processing multiple requests and out of order returns |
US5694565A (en) * | 1995-09-11 | 1997-12-02 | International Business Machines Corporation | Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions |
US5745724A (en) * | 1996-01-26 | 1998-04-28 | Advanced Micro Devices, Inc. | Scan chain for rapidly identifying first or second objects of selected types in a sequential list |
US5754812A (en) * | 1995-10-06 | 1998-05-19 | Advanced Micro Devices, Inc. | Out-of-order load/store execution control |
US6038657A (en) * | 1995-10-06 | 2000-03-14 | Advanced Micro Devices, Inc. | Scan chains for out-of-order load/store execution control |
JPH11510290A (ja) * | 1995-10-06 | 1999-09-07 | アドバンスト・マイクロ・デバイシズ・インコーポレイテッド | シーケンシャルなリスト内の選択されたタイプの第1もしくは第2のオブジェクトを迅速に特定するためのスキャンチェーン |
US5835747A (en) * | 1996-01-26 | 1998-11-10 | Advanced Micro Devices, Inc. | Hierarchical scan logic for out-of-order load/store execution control |
US5764943A (en) * | 1995-12-28 | 1998-06-09 | Intel Corporation | Data path circuitry for processor having multiple instruction pipelines |
US6092184A (en) * | 1995-12-28 | 2000-07-18 | Intel Corporation | Parallel processing of pipelined instructions having register dependencies |
US5781790A (en) * | 1995-12-29 | 1998-07-14 | Intel Corporation | Method and apparatus for performing floating point to integer transfers and vice versa |
US5778210A (en) * | 1996-01-11 | 1998-07-07 | Intel Corporation | Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time |
US5751946A (en) * | 1996-01-18 | 1998-05-12 | International Business Machines Corporation | Method and system for detecting bypass error conditions in a load/store unit of a superscalar processor |
US5930489A (en) * | 1996-02-09 | 1999-07-27 | Advanced Micro Devices, Inc. | Microprocessor configured to detect memory operations having data addresses indicative of a boundary between instructions sets |
US5809275A (en) * | 1996-03-01 | 1998-09-15 | Hewlett-Packard Company | Store-to-load hazard resolution system and method for a processor that executes instructions out of order |
US5838942A (en) * | 1996-03-01 | 1998-11-17 | Hewlett-Packard Company | Panic trap system and method |
US5813033A (en) * | 1996-03-08 | 1998-09-22 | Advanced Micro Devices, Inc. | Superscalar microprocessor including a cache configured to detect dependencies between accesses to the cache and another cache |
US5968166A (en) * | 1996-03-22 | 1999-10-19 | Matsushita Electric Industrial Co., Ltd. | Information processing apparatus and method, and scheduling device for reducing inactivity due to wait state |
US5737749A (en) * | 1996-05-20 | 1998-04-07 | International Business Machines Corporation | Method and system for dynamically sharing cache capacity in a microprocessor |
US5860158A (en) * | 1996-11-15 | 1999-01-12 | Samsung Electronics Company, Ltd. | Cache control unit with a cache request transaction-oriented protocol |
US5884055A (en) * | 1996-11-27 | 1999-03-16 | Emc Corporation | Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource |
US5890207A (en) * | 1996-11-27 | 1999-03-30 | Emc Corporation | High performance integrated cached storage device |
US5890219A (en) * | 1996-11-27 | 1999-03-30 | Emc Corporation | Redundant writing of data to cached storage system |
US5897666A (en) * | 1996-12-09 | 1999-04-27 | International Business Machines Corporation | Generation of unique address alias for memory disambiguation buffer to avoid false collisions |
US5841998A (en) * | 1996-12-31 | 1998-11-24 | Metaflow Technologies, Inc. | System and method of processing instructions for a processor |
US6230245B1 (en) | 1997-02-11 | 2001-05-08 | Micron Technology, Inc. | Method and apparatus for generating a variable sequence of memory device command signals |
US6175894B1 (en) | 1997-03-05 | 2001-01-16 | Micron Technology, Inc. | Memory device command buffer apparatus and method and memory devices and computer systems using same |
US5931957A (en) * | 1997-03-31 | 1999-08-03 | International Business Machines Corporation | Support for out-of-order execution of loads and stores in a processor |
US6021485A (en) * | 1997-04-10 | 2000-02-01 | International Business Machines Corporation | Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching |
US5987574A (en) * | 1997-04-30 | 1999-11-16 | Sony Corporation | Bank arbitration for SDRAM memory control |
US5996043A (en) | 1997-06-13 | 1999-11-30 | Micron Technology, Inc. | Two step memory device command buffer apparatus and method and memory devices and computer systems using same |
US6484244B1 (en) | 1997-06-17 | 2002-11-19 | Micron Technology, Inc. | Method and system for storing and processing multiple memory commands |
US6058472A (en) * | 1997-06-25 | 2000-05-02 | Sun Microsystems, Inc. | Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine |
US6085289A (en) * | 1997-07-18 | 2000-07-04 | International Business Machines Corporation | Method and system for load data formatting and improved method for cache line organization |
US6070238A (en) * | 1997-09-11 | 2000-05-30 | International Business Machines Corporation | Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction |
US6112293A (en) * | 1997-11-17 | 2000-08-29 | Advanced Micro Devices, Inc. | Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result |
US6202119B1 (en) | 1997-12-19 | 2001-03-13 | Micron Technology, Inc. | Method and system for processing pipelined memory commands |
US6112297A (en) * | 1998-02-10 | 2000-08-29 | International Business Machines Corporation | Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution |
US6360314B1 (en) * | 1998-07-14 | 2002-03-19 | Compaq Information Technologies Group, L.P. | Data cache having store queue bypass for out-of-order instruction execution and method for same |
US6175905B1 (en) * | 1998-07-30 | 2001-01-16 | Micron Technology, Inc. | Method and system for bypassing pipelines in a pipelined memory command generator |
US7779236B1 (en) * | 1998-12-31 | 2010-08-17 | Stmicroelectronics, Inc. | Symbolic store-load bypass |
US7111290B1 (en) | 1999-01-28 | 2006-09-19 | Ati International Srl | Profiling program execution to identify frequently-executed portions and to assist binary translation |
US6954923B1 (en) | 1999-01-28 | 2005-10-11 | Ati International Srl | Recording classification of instructions executed by a computer |
US6978462B1 (en) * | 1999-01-28 | 2005-12-20 | Ati International Srl | Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled |
US7275246B1 (en) | 1999-01-28 | 2007-09-25 | Ati International Srl | Executing programs for a first computer architecture on a computer of a second architecture |
US7941647B2 (en) | 1999-01-28 | 2011-05-10 | Ati Technologies Ulc | Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination |
US8074055B1 (en) | 1999-01-28 | 2011-12-06 | Ati Technologies Ulc | Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code |
US7065633B1 (en) | 1999-01-28 | 2006-06-20 | Ati International Srl | System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU |
US8065504B2 (en) | 1999-01-28 | 2011-11-22 | Ati International Srl | Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor |
US8127121B2 (en) | 1999-01-28 | 2012-02-28 | Ati Technologies Ulc | Apparatus for executing programs for a first computer architechture on a computer of a second architechture |
US6336183B1 (en) * | 1999-02-26 | 2002-01-01 | International Business Machines Corporation | System and method for executing store instructions |
US6237066B1 (en) * | 1999-03-22 | 2001-05-22 | Sun Microsystems, Inc. | Supporting multiple outstanding requests to multiple targets in a pipelined memory system |
US6473832B1 (en) | 1999-05-18 | 2002-10-29 | Advanced Micro Devices, Inc. | Load/store unit having pre-cache and post-cache queues for low latency load memory operations |
US6415360B1 (en) | 1999-05-18 | 2002-07-02 | Advanced Micro Devices, Inc. | Minimizing self-modifying code checks for uncacheable memory types |
US6266744B1 (en) * | 1999-05-18 | 2001-07-24 | Advanced Micro Devices, Inc. | Store to load forwarding using a dependency link file |
US6393536B1 (en) | 1999-05-18 | 2002-05-21 | Advanced Micro Devices, Inc. | Load/store unit employing last-in-buffer indication for rapid load-hit-store |
US6473837B1 (en) | 1999-05-18 | 2002-10-29 | Advanced Micro Devices, Inc. | Snoop resynchronization mechanism to preserve read ordering |
US6427193B1 (en) | 1999-05-18 | 2002-07-30 | Advanced Micro Devices, Inc. | Deadlock avoidance using exponential backoff |
US7089404B1 (en) | 1999-06-14 | 2006-08-08 | Transmeta Corporation | Method and apparatus for enhancing scheduling in an advanced microprocessor |
US6134646A (en) * | 1999-07-29 | 2000-10-17 | International Business Machines Corp. | System and method for executing and completing store instructions |
US6915385B1 (en) * | 1999-07-30 | 2005-07-05 | International Business Machines Corporation | Apparatus for unaligned cache reads and methods therefor |
US6549959B1 (en) | 1999-08-30 | 2003-04-15 | Ati International Srl | Detecting modification to computer memory by a DMA device |
US6662280B1 (en) | 1999-11-10 | 2003-12-09 | Advanced Micro Devices, Inc. | Store buffer which forwards data based on index and optional way match |
US6539467B1 (en) * | 1999-11-15 | 2003-03-25 | Texas Instruments Incorporated | Microprocessor with non-aligned memory access |
US6970996B1 (en) | 2000-01-04 | 2005-11-29 | National Semiconductor Corporation | Operand queue for use in a floating point unit to reduce read-after-write latency and method of operation |
US6934832B1 (en) | 2000-01-18 | 2005-08-23 | Ati International Srl | Exception mechanism for a computer |
DE10121792C2 (de) * | 2000-05-26 | 2003-09-25 | Ibm | Universelle Ladeadresse/Wertevorhersageschema |
US6732234B1 (en) * | 2000-08-07 | 2004-05-04 | Broadcom Corporation | Direct access mode for a cache |
US6748492B1 (en) | 2000-08-07 | 2004-06-08 | Broadcom Corporation | Deterministic setting of replacement policy in a cache through way selection |
US6848024B1 (en) | 2000-08-07 | 2005-01-25 | Broadcom Corporation | Programmably disabling one or more cache entries |
JP4025493B2 (ja) * | 2000-08-08 | 2007-12-19 | 富士通株式会社 | 適切な発行先に命令を発行する命令発行装置 |
US7757066B2 (en) | 2000-12-29 | 2010-07-13 | Stmicroelectronics, Inc. | System and method for executing variable latency load operations in a date processor |
JP3776732B2 (ja) * | 2001-02-02 | 2006-05-17 | 株式会社東芝 | プロセッサ装置 |
FR2821449B1 (fr) * | 2001-02-27 | 2003-07-04 | St Microelectronics Sa | Procede de gestion d'instructions au sein d'un processeur a architecture decouplee, en particulier un processeur de traitement numerique du signal, et processeur correspondant |
US6748495B2 (en) | 2001-05-15 | 2004-06-08 | Broadcom Corporation | Random generator |
US6959348B1 (en) * | 2001-07-30 | 2005-10-25 | Vixs Systems, Inc. | Method and system for accessing data |
US20030065909A1 (en) * | 2001-09-28 | 2003-04-03 | Jourdan Stephan J. | Deferral of dependent loads until after execution of colliding stores |
US7529912B2 (en) * | 2002-02-12 | 2009-05-05 | Via Technologies, Inc. | Apparatus and method for instruction-level specification of floating point format |
US7181596B2 (en) | 2002-02-12 | 2007-02-20 | Ip-First, Llc | Apparatus and method for extending a microprocessor instruction set |
US7315921B2 (en) * | 2002-02-19 | 2008-01-01 | Ip-First, Llc | Apparatus and method for selective memory attribute control |
US7328328B2 (en) * | 2002-02-19 | 2008-02-05 | Ip-First, Llc | Non-temporal memory reference control mechanism |
US7546446B2 (en) * | 2002-03-08 | 2009-06-09 | Ip-First, Llc | Selective interrupt suppression |
US7395412B2 (en) * | 2002-03-08 | 2008-07-01 | Ip-First, Llc | Apparatus and method for extending data modes in a microprocessor |
US6963964B2 (en) | 2002-03-14 | 2005-11-08 | International Business Machines Corporation | Method and apparatus for detecting pipeline address conflict using parallel compares of multiple real addresses |
US6804759B2 (en) * | 2002-03-14 | 2004-10-12 | International Business Machines Corporation | Method and apparatus for detecting pipeline address conflict using compare of byte addresses |
US7155598B2 (en) * | 2002-04-02 | 2006-12-26 | Ip-First, Llc | Apparatus and method for conditional instruction execution |
US7185180B2 (en) * | 2002-04-02 | 2007-02-27 | Ip-First, Llc | Apparatus and method for selective control of condition code write back |
US7373483B2 (en) | 2002-04-02 | 2008-05-13 | Ip-First, Llc | Mechanism for extending the number of registers in a microprocessor |
US7302551B2 (en) * | 2002-04-02 | 2007-11-27 | Ip-First, Llc | Suppression of store checking |
US7380103B2 (en) | 2002-04-02 | 2008-05-27 | Ip-First, Llc | Apparatus and method for selective control of results write back |
US7380109B2 (en) * | 2002-04-15 | 2008-05-27 | Ip-First, Llc | Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor |
US7266587B2 (en) * | 2002-05-15 | 2007-09-04 | Broadcom Corporation | System having interfaces, switch, and memory bridge for CC-NUMA operation |
US7181598B2 (en) * | 2002-05-17 | 2007-02-20 | Intel Corporation | Prediction of load-store dependencies in a processing agent |
US7218647B2 (en) * | 2002-06-27 | 2007-05-15 | International Business Machines Corporation | Method and apparatus for implementing frame header alterations |
JP3808013B2 (ja) * | 2002-07-05 | 2006-08-09 | 富士通株式会社 | 命令実行装置 |
US7062636B2 (en) * | 2002-09-19 | 2006-06-13 | Intel Corporation | Ordering scheme with architectural operation decomposed into result producing speculative micro-operation and exception producing architectural micro-operation |
US7145567B2 (en) * | 2003-04-03 | 2006-12-05 | Avid Technology, Inc. | Bitstream format and reading and writing methods and apparatus therefor |
US7321964B2 (en) * | 2003-07-08 | 2008-01-22 | Advanced Micro Devices, Inc. | Store-to-load forwarding buffer using indexed lookup |
US6925928B2 (en) * | 2003-09-18 | 2005-08-09 | Anthony Fox | Trash compactor for fast food restaurant waste |
US7721069B2 (en) * | 2004-07-13 | 2010-05-18 | 3Plus1 Technology, Inc | Low power, high performance, heterogeneous, scalable processor architecture |
US7376817B2 (en) * | 2005-08-10 | 2008-05-20 | P.A. Semi, Inc. | Partial load/store forward prediction |
US9176741B2 (en) * | 2005-08-29 | 2015-11-03 | Invention Science Fund I, Llc | Method and apparatus for segmented sequential storage |
US20070083735A1 (en) * | 2005-08-29 | 2007-04-12 | Glew Andrew F | Hierarchical processor |
US7644258B2 (en) * | 2005-08-29 | 2010-01-05 | Searete, Llc | Hybrid branch predictor using component predictors each having confidence and override signals |
US8296550B2 (en) * | 2005-08-29 | 2012-10-23 | The Invention Science Fund I, Llc | Hierarchical register file with operand capture ports |
US8275976B2 (en) * | 2005-08-29 | 2012-09-25 | The Invention Science Fund I, Llc | Hierarchical instruction scheduler facilitating instruction replay |
US7461239B2 (en) * | 2006-02-02 | 2008-12-02 | International Business Machines Corporation | Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines |
JP4189436B2 (ja) | 2006-11-07 | 2008-12-03 | 日立ソフトウエアエンジニアリング株式会社 | データ処理制御方法 |
JP5145929B2 (ja) * | 2007-03-08 | 2013-02-20 | 株式会社リコー | 半導体集積回路及び画像処理装置 |
US7600099B2 (en) * | 2007-03-08 | 2009-10-06 | International Business Machines Corporation | System and method for predictive early allocation of stores in a microprocessor |
US20090006712A1 (en) * | 2007-06-29 | 2009-01-01 | Fatma Ehsan | Data ordering in a multi-node system |
JP5315748B2 (ja) * | 2008-03-28 | 2013-10-16 | 富士通株式会社 | マイクロプロセッサおよびシグネチャ生成方法ならびに多重化システムおよび多重化実行検証方法 |
JP5206385B2 (ja) * | 2008-12-12 | 2013-06-12 | 日本電気株式会社 | バウンダリ実行制御システム、バウンダリ実行制御方法、及びバウンダリ実行制御プログラム |
US8266411B2 (en) * | 2009-02-05 | 2012-09-11 | International Business Machines Corporation | Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance |
US7895381B2 (en) * | 2009-02-16 | 2011-02-22 | Himax Media Solutions, Inc. | Data accessing system |
GB2469299B (en) * | 2009-04-07 | 2011-02-16 | Imagination Tech Ltd | Ensuring consistency between a data cache and a main memory |
US8078796B2 (en) * | 2009-04-14 | 2011-12-13 | Micron Technology, Inc. | Method for writing to and erasing a non-volatile memory |
US8392666B2 (en) * | 2009-05-21 | 2013-03-05 | Via Technologies, Inc. | Low power high speed load-store collision detector |
US9009414B2 (en) * | 2010-09-21 | 2015-04-14 | Texas Instruments Incorporated | Prefetch address hit prediction to reduce memory access latency |
EP2440016B1 (en) * | 2010-10-08 | 2019-01-23 | Lantiq Beteiligungs-GmbH & Co.KG | Laser diode control device |
US9128725B2 (en) | 2012-05-04 | 2015-09-08 | Apple Inc. | Load-store dependency predictor content management |
US9600289B2 (en) | 2012-05-30 | 2017-03-21 | Apple Inc. | Load-store dependency predictor PC hashing |
JP6344022B2 (ja) * | 2014-04-08 | 2018-06-20 | 富士通株式会社 | 演算処理装置および演算処理装置の制御方法 |
US9710268B2 (en) | 2014-04-29 | 2017-07-18 | Apple Inc. | Reducing latency for pointer chasing loads |
US11561792B2 (en) | 2015-06-08 | 2023-01-24 | Qualcomm Incorporated | System, apparatus, and method for a transient load instruction within a VLIW operation |
US10241800B2 (en) | 2015-06-16 | 2019-03-26 | International Business Machines Corporation | Split-level history buffer in a computer processing unit |
US10503506B2 (en) * | 2015-10-19 | 2019-12-10 | Arm Limited | Apparatus and method for accessing data in a cache in response to an unaligned load instruction |
US10191748B2 (en) * | 2015-11-30 | 2019-01-29 | Intel IP Corporation | Instruction and logic for in-order handling in an out-of-order processor |
DE102015224300A1 (de) * | 2015-12-04 | 2017-06-08 | Siemens Aktiengesellschaft | Speicherprogrammierbarer Baustein und Verfahren zur geschützten Übertragung von Daten auf einen speicherprogrammierbaren Baustein |
US10514925B1 (en) | 2016-01-28 | 2019-12-24 | Apple Inc. | Load speculation recovery |
US10437595B1 (en) | 2016-03-15 | 2019-10-08 | Apple Inc. | Load/store dependency predictor optimization for replayed loads |
US10331357B2 (en) * | 2016-08-19 | 2019-06-25 | Advanced Micro Devices, Inc. | Tracking stores and loads by bypassing load store units |
US11048506B2 (en) | 2016-08-19 | 2021-06-29 | Advanced Micro Devices, Inc. | Tracking stores and loads by bypassing load store units |
US10353707B2 (en) | 2017-07-12 | 2019-07-16 | International Business Machines Corporation | Efficient pointer load and format |
US10606590B2 (en) | 2017-10-06 | 2020-03-31 | International Business Machines Corporation | Effective address based load store unit in out of order processors |
US10417002B2 (en) | 2017-10-06 | 2019-09-17 | International Business Machines Corporation | Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses |
US10572256B2 (en) | 2017-10-06 | 2020-02-25 | International Business Machines Corporation | Handling effective address synonyms in a load-store unit that operates without address translation |
US10606591B2 (en) | 2017-10-06 | 2020-03-31 | International Business Machines Corporation | Handling effective address synonyms in a load-store unit that operates without address translation |
US10579387B2 (en) | 2017-10-06 | 2020-03-03 | International Business Machines Corporation | Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor |
US11175924B2 (en) | 2017-10-06 | 2021-11-16 | International Business Machines Corporation | Load-store unit with partitioned reorder queues with single cam port |
US10394558B2 (en) | 2017-10-06 | 2019-08-27 | International Business Machines Corporation | Executing load-store operations without address translation hardware per load-store unit port |
KR102569336B1 (ko) * | 2019-04-04 | 2023-08-21 | 캠브리콘 테크놀로지스 코퍼레이션 리미티드 | 데이터 처리방법과 장치 및 관련 제품 |
Family Cites Families (131)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3346851A (en) | 1964-07-08 | 1967-10-10 | Control Data Corp | Simultaneous multiprocessing computer system |
US3541528A (en) * | 1969-01-06 | 1970-11-17 | Ibm | Implicit load and store mechanism |
US3789365A (en) | 1971-06-03 | 1974-01-29 | Bunker Ramo | Processor interrupt system |
US3771138A (en) | 1971-08-31 | 1973-11-06 | Ibm | Apparatus and method for serializing instructions from two independent instruction streams |
US3916388A (en) | 1974-05-30 | 1975-10-28 | Ibm | Shifting apparatus for automatic data alignment |
US4084235A (en) | 1975-04-14 | 1978-04-11 | Honeywell Information Systems Inc. | Emulation apparatus |
US4034349A (en) | 1976-01-29 | 1977-07-05 | Sperry Rand Corporation | Apparatus for processing interrupts in microprocessing systems |
AU529675B2 (en) | 1977-12-07 | 1983-06-16 | Honeywell Information Systems Incorp. | Cache memory unit |
US4315314A (en) | 1977-12-30 | 1982-02-09 | Rca Corporation | Priority vectored interrupt having means to supply branch address directly |
US4200927A (en) | 1978-01-03 | 1980-04-29 | International Business Machines Corporation | Multi-instruction stream branch processing mechanism |
US4189772A (en) | 1978-03-16 | 1980-02-19 | International Business Machines Corporation | Operand alignment controls for VFL instructions |
US4189768A (en) | 1978-03-16 | 1980-02-19 | International Business Machines Corporation | Operand fetch control improvement |
US4236206A (en) | 1978-10-25 | 1980-11-25 | Digital Equipment Corporation | Central processor unit for executing instructions of variable length |
US4228495A (en) | 1978-12-19 | 1980-10-14 | Allen-Bradley Company | Multiprocessor numerical control system |
JPS6041768B2 (ja) | 1979-01-19 | 1985-09-18 | 株式会社日立製作所 | デ−タ処理装置 |
US4296470A (en) | 1979-06-21 | 1981-10-20 | International Business Machines Corp. | Link register storage and restore system for use in an instruction pre-fetch micro-processor interrupt system |
JPS5616248A (en) | 1979-07-17 | 1981-02-17 | Matsushita Electric Ind Co Ltd | Processing system for interruption |
JPS5847053B2 (ja) * | 1979-11-19 | 1983-10-20 | 株式会社日立製作所 | デ−タ処理装置 |
CA1174370A (en) | 1980-05-19 | 1984-09-11 | Hidekazu Matsumoto | Data processing unit with pipelined operands |
JPS5743239A (en) | 1980-08-27 | 1982-03-11 | Hitachi Ltd | Data processor |
JPS6028015B2 (ja) | 1980-08-28 | 1985-07-02 | 日本電気株式会社 | 情報処理装置 |
US4434461A (en) | 1980-09-15 | 1984-02-28 | Motorola, Inc. | Microprocessor with duplicate registers for processing interrupts |
JPS5757345A (en) | 1980-09-24 | 1982-04-06 | Toshiba Corp | Data controller |
US4654781A (en) | 1981-10-02 | 1987-03-31 | Raytheon Company | Byte addressable memory for variable length instructions and data |
JPS58151655A (ja) | 1982-03-03 | 1983-09-08 | Fujitsu Ltd | 情報処理装置 |
US4514803A (en) | 1982-04-26 | 1985-04-30 | International Business Machines Corporation | Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof |
JPS58217054A (ja) * | 1982-06-11 | 1983-12-16 | Hitachi Ltd | デ−タ処理装置 |
JPS5932045A (ja) | 1982-08-16 | 1984-02-21 | Hitachi Ltd | 情報処理装置 |
US4587612A (en) | 1982-10-22 | 1986-05-06 | International Business Machines Corporation | Accelerated instruction mapping external to source and target instruction streams for near realtime injection into the latter |
JPS59154548A (ja) * | 1983-02-22 | 1984-09-03 | Hitachi Ltd | 記憶制御方式 |
JPS59165143A (ja) * | 1983-03-11 | 1984-09-18 | Hitachi Ltd | デ−タ処理装置 |
US4569016A (en) | 1983-06-30 | 1986-02-04 | International Business Machines Corporation | Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system |
EP0150177A1 (en) * | 1983-07-11 | 1985-08-07 | Prime Computer, Inc. | Data processing system |
US4800486A (en) | 1983-09-29 | 1989-01-24 | Tandem Computers Incorporated | Multiple data patch CPU architecture |
US4807115A (en) | 1983-10-07 | 1989-02-21 | Cornell Research Foundation, Inc. | Instruction issuing mechanism for processors with multiple functional units |
GB8329509D0 (en) | 1983-11-04 | 1983-12-07 | Inmos Ltd | Computer |
JPH063584B2 (ja) * | 1983-12-19 | 1994-01-12 | 株式会社日立製作所 | 情報処理装置 |
JPS60225943A (ja) | 1984-04-25 | 1985-11-11 | Hitachi Ltd | 例外割込み処理方式 |
US4720779A (en) | 1984-06-28 | 1988-01-19 | Burroughs Corporation | Stored logic program scanner for a data processor having internal plural data and instruction streams |
JPS6133546A (ja) | 1984-07-25 | 1986-02-17 | Nec Corp | 情報処理装置 |
US4766564A (en) | 1984-08-13 | 1988-08-23 | International Business Machines Corporation | Dual putaway/bypass busses for multiple arithmetic units |
US4739472A (en) * | 1984-12-07 | 1988-04-19 | Nec Corporation | Information processing device capable of rapidly processing instructions of different groups |
NL193475C (nl) | 1984-12-27 | 1999-11-02 | Sony Corp | Microprocessorinrichting. |
US4794517A (en) | 1985-04-15 | 1988-12-27 | International Business Machines Corporation | Three phased pipelined signal processor |
US4679141A (en) * | 1985-04-29 | 1987-07-07 | International Business Machines Corporation | Pageable branch history table |
US4714994A (en) | 1985-04-30 | 1987-12-22 | International Business Machines Corp. | Instruction prefetch buffer control |
JPH0762823B2 (ja) | 1985-05-22 | 1995-07-05 | 株式会社日立製作所 | デ−タ処理装置 |
DE3650578T2 (de) * | 1985-06-17 | 1997-03-06 | Nippon Electric Co | Informationsverarbeitungssystem mit einer Steuerschaltung zum Abwarten einer Registererneuerung und einem Aufnahmemittel des zu erneuernden Registers |
US4739471A (en) | 1985-06-28 | 1988-04-19 | Hewlett-Packard Company | Method and means for moving bytes in a reduced instruction set computer |
US4734852A (en) * | 1985-08-30 | 1988-03-29 | Advanced Micro Devices, Inc. | Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor |
US4722049A (en) * | 1985-10-11 | 1988-01-26 | Unisys Corporation | Apparatus for out-of-order program execution |
JPS62152043A (ja) | 1985-12-26 | 1987-07-07 | Nec Corp | 命令コ−ドアクセス制御方式 |
JPS62165242A (ja) | 1986-01-17 | 1987-07-21 | Toshiba Corp | プロセツサ |
DE3603240A1 (de) * | 1986-02-03 | 1987-08-06 | Siemens Ag | Schaltungsanordnung zur bereinigung von operandenkonflikten in nach dem fliessbandprinzip arbeitenden datenverarbeitungsanlagen |
EP0239081B1 (en) | 1986-03-26 | 1995-09-06 | Hitachi, Ltd. | Pipelined data processor capable of decoding and executing plural instructions in parallel |
US4903196A (en) | 1986-05-02 | 1990-02-20 | International Business Machines Corporation | Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor |
US5051940A (en) * | 1990-04-04 | 1991-09-24 | International Business Machines Corporation | Data dependency collapsing hardware apparatus |
JPS6324428A (ja) | 1986-07-17 | 1988-02-01 | Mitsubishi Electric Corp | キヤツシユメモリ |
US4766566A (en) | 1986-08-18 | 1988-08-23 | International Business Machines Corp. | Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing |
EP0259095A3 (en) * | 1986-08-27 | 1990-02-28 | Amdahl Corporation | Cache storage queue |
US5133072A (en) | 1986-11-13 | 1992-07-21 | Hewlett-Packard Company | Method for improved code generation in reduced instruction set computers |
JPS63131230A (ja) | 1986-11-21 | 1988-06-03 | Hitachi Ltd | 情報処理装置 |
US4992934A (en) | 1986-12-15 | 1991-02-12 | United Technologies Corporation | Reduced instruction set computing apparatus and methods |
IL84821A (en) * | 1986-12-15 | 1992-07-15 | United Technologies Corp | Reduced instruction set computing apparatus and methods |
US4814976C1 (en) * | 1986-12-23 | 2002-06-04 | Mips Tech Inc | Risc computer with unaligned reference handling and method for the same |
JPS63163930A (ja) | 1986-12-26 | 1988-07-07 | Toshiba Corp | アライメント補正方式 |
US4991090A (en) * | 1987-05-18 | 1991-02-05 | International Business Machines Corporation | Posting out-of-sequence fetches |
US4992938A (en) | 1987-07-01 | 1991-02-12 | International Business Machines Corporation | Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers |
US5134561A (en) | 1987-07-20 | 1992-07-28 | International Business Machines Corporation | Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries |
US4901233A (en) | 1987-07-20 | 1990-02-13 | International Business Machines Corporation | Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries |
US4942520A (en) * | 1987-07-31 | 1990-07-17 | Prime Computer, Inc. | Method and apparatus for indexing, accessing and updating a memory |
US4916652A (en) | 1987-09-30 | 1990-04-10 | International Business Machines Corporation | Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures |
EP0312764A3 (en) * | 1987-10-19 | 1991-04-10 | International Business Machines Corporation | A data processor having multiple execution units for processing plural classes of instructions in parallel |
US5247628A (en) * | 1987-11-30 | 1993-09-21 | International Business Machines Corporation | Parallel processor instruction dispatch apparatus with interrupt handler |
JP2667849B2 (ja) * | 1988-01-06 | 1997-10-27 | 株式会社日立製作所 | 情報処理装置 |
US4926323A (en) | 1988-03-03 | 1990-05-15 | Advanced Micro Devices, Inc. | Streamlined instruction processor |
JPH01286030A (ja) * | 1988-05-12 | 1989-11-17 | Nec Corp | 情報処理装置 |
US5003462A (en) | 1988-05-31 | 1991-03-26 | International Business Machines Corporation | Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt means |
US4897810A (en) | 1988-06-13 | 1990-01-30 | Advanced Micro Devices, Inc. | Asynchronous interrupt status bit circuit |
EP0348628A3 (en) | 1988-06-28 | 1991-01-02 | International Business Machines Corporation | Cache storage system |
US5148536A (en) * | 1988-07-25 | 1992-09-15 | Digital Equipment Corporation | Pipeline having an integral cache which processes cache misses and loads data in parallel |
JPH0673105B2 (ja) | 1988-08-11 | 1994-09-14 | 株式会社東芝 | 命令パイプライン方式のマイクロプロセッサ |
US5101341A (en) | 1988-08-25 | 1992-03-31 | Edgcore Technology, Inc. | Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO |
JP2810068B2 (ja) | 1988-11-11 | 1998-10-15 | 株式会社日立製作所 | プロセッサシステム、コンピュータシステム及び命令処理方法 |
JPH0760408B2 (ja) * | 1988-11-30 | 1995-06-28 | 松下電器産業株式会社 | データ処理装置 |
JPH02151930A (ja) * | 1988-12-05 | 1990-06-11 | Nec Corp | ストアバツフア管理方式 |
GB8828817D0 (en) | 1988-12-09 | 1989-01-18 | Int Computers Ltd | Data processing apparatus |
US4961162A (en) * | 1989-01-13 | 1990-10-02 | International Business Machines Corporation | Multiprocessing system for performing floating point arithmetic operations |
US5075840A (en) | 1989-01-13 | 1991-12-24 | International Business Machines Corporation | Tightly coupled multiprocessor instruction synchronization |
US5127091A (en) | 1989-01-13 | 1992-06-30 | International Business Machines Corporation | System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor |
US5249273A (en) | 1989-01-17 | 1993-09-28 | Fujitsu Limited | Microprocessor having a variable length instruction format |
US5148528A (en) | 1989-02-03 | 1992-09-15 | Digital Equipment Corporation | Method and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable length |
US5113515A (en) | 1989-02-03 | 1992-05-12 | Digital Equipment Corporation | Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer |
US4985825A (en) | 1989-02-03 | 1991-01-15 | Digital Equipment Corporation | System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer |
US5226126A (en) | 1989-02-24 | 1993-07-06 | Nexgen Microsystems | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags |
US5768575A (en) | 1989-02-24 | 1998-06-16 | Advanced Micro Devices, Inc. | Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions |
GB2230116B (en) | 1989-04-07 | 1993-02-17 | Intel Corp | An improvement for pipelined decoding of instructions in a pipelined processor |
CA2016068C (en) | 1989-05-24 | 2000-04-04 | Robert W. Horst | Multiple instruction issue computer architecture |
JPH0314025A (ja) | 1989-06-13 | 1991-01-22 | Nec Corp | 命令実行制御方式 |
EP0419105B1 (en) | 1989-09-21 | 1997-08-13 | Texas Instruments Incorporated | Integrated circuit formed on a surface of a semiconductor substrate and method for constructing such an integrated circuit |
JP2835103B2 (ja) | 1989-11-01 | 1998-12-14 | 富士通株式会社 | 命令指定方法及び命令実行方式 |
US5487156A (en) * | 1989-12-15 | 1996-01-23 | Popescu; Valeri | Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched |
US5185871A (en) * | 1989-12-26 | 1993-02-09 | International Business Machines Corporation | Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions |
US5193206A (en) | 1989-12-27 | 1993-03-09 | Motorola, Inc. | Reduce instruction set microprocessor |
US5251306A (en) * | 1990-01-16 | 1993-10-05 | Advanced Micro Devices, Inc. | Apparatus for controlling execution of a program in a computing device |
US5185868A (en) * | 1990-01-16 | 1993-02-09 | Advanced Micro Devices, Inc. | Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy |
US5168571A (en) | 1990-01-24 | 1992-12-01 | International Business Machines Corporation | System for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte data |
US5230068A (en) | 1990-02-26 | 1993-07-20 | Nexgen Microsystems | Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence |
GB2241801B (en) * | 1990-03-05 | 1994-03-16 | Intel Corp | Data bypass structure in a register file on a microprocessor chip to ensure data integrity |
CA2038264C (en) | 1990-06-26 | 1995-06-27 | Richard James Eickemeyer | In-memory preprocessor for a scalable compound instruction set machine processor |
US5193167A (en) * | 1990-06-29 | 1993-03-09 | Digital Equipment Corporation | Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system |
US5155843A (en) * | 1990-06-29 | 1992-10-13 | Digital Equipment Corporation | Error transition mode for multi-processor system |
JP2834289B2 (ja) * | 1990-07-20 | 1998-12-09 | 株式会社日立製作所 | マイクロプロセッサ |
US5163139A (en) | 1990-08-29 | 1992-11-10 | Hitachi America, Ltd. | Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions |
DE69130723T2 (de) | 1990-10-05 | 1999-07-22 | Koninklijke Philips Electronics N.V., Eindhoven | Verarbeitungsgerät mit Speicherschaltung und eine Gruppe von Funktionseinheiten |
JP2532300B2 (ja) | 1990-10-17 | 1996-09-11 | 三菱電機株式会社 | 並列処理装置における命令供給装置 |
US5317740A (en) * | 1991-03-07 | 1994-05-31 | Digital Equipment Corporation | Alternate and iterative analysis of computer programs for locating translatable code by resolving callbacks and other conflicting mutual dependencies |
US5261071A (en) | 1991-03-21 | 1993-11-09 | Control Data System, Inc. | Dual pipe cache memory with out-of-order issue capability |
US5539911A (en) | 1991-07-08 | 1996-07-23 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
US5345569A (en) | 1991-09-20 | 1994-09-06 | Advanced Micro Devices, Inc. | Apparatus and method for resolving dependencies among a plurality of instructions within a storage device |
US5323489A (en) * | 1991-11-14 | 1994-06-21 | Bird Peter L | Method and apparatus employing lookahead to reduce memory bank contention for decoupled operand references |
US5371684A (en) * | 1992-03-31 | 1994-12-06 | Seiko Epson Corporation | Semiconductor floor plan for a register renaming circuit |
US5418973A (en) | 1992-06-22 | 1995-05-23 | Digital Equipment Corporation | Digital computer system with cache controller coordinating both vector and scalar operations |
US5442756A (en) | 1992-07-31 | 1995-08-15 | Intel Corporation | Branch prediction and resolution apparatus for a superscalar computer processor |
US5619668A (en) | 1992-08-10 | 1997-04-08 | Intel Corporation | Apparatus for register bypassing in a microprocessor |
KR100248903B1 (ko) | 1992-09-29 | 2000-03-15 | 야스카와 히데아키 | 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템 |
US6735685B1 (en) | 1992-09-29 | 2004-05-11 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
DE69429061T2 (de) | 1993-10-29 | 2002-07-18 | Advanced Micro Devices, Inc. | Superskalarmikroprozessoren |
US5574927A (en) * | 1994-03-25 | 1996-11-12 | International Meta Systems, Inc. | RISC architecture computer configured for emulation of the instruction set of a target computer |
US5778210A (en) * | 1996-01-11 | 1998-07-07 | Intel Corporation | Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time |
US5832205A (en) * | 1996-08-20 | 1998-11-03 | Transmeta Corporation | Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed |
-
1993
- 1993-09-03 KR KR1019950701204A patent/KR100248903B1/ko not_active IP Right Cessation
- 1993-09-03 WO PCT/US1993/008331 patent/WO1994008287A1/en active IP Right Grant
- 1993-09-03 EP EP93921343A patent/EP0663083B1/en not_active Expired - Lifetime
- 1993-09-03 JP JP50906394A patent/JP3644959B2/ja not_active Expired - Lifetime
- 1993-09-03 DE DE69329778T patent/DE69329778T2/de not_active Expired - Lifetime
-
1994
- 1994-09-16 US US08/307,042 patent/US5659782A/en not_active Expired - Lifetime
-
1995
- 1995-06-05 US US08/465,238 patent/US5557763A/en not_active Expired - Lifetime
-
1997
- 1997-11-03 US US08/962,705 patent/US5987593A/en not_active Expired - Lifetime
-
1998
- 1998-12-28 HK HK98116063A patent/HK1014780A1/xx not_active IP Right Cessation
-
1999
- 1999-11-12 US US09/438,359 patent/US6434693B1/en not_active Expired - Fee Related
-
2000
- 2000-01-17 JP JP2000008267A patent/JP2000148483A/ja not_active Withdrawn
- 2000-01-17 JP JP2000008270A patent/JP2000148493A/ja active Pending
- 2000-01-17 JP JP2000008264A patent/JP2000148481A/ja active Pending
- 2000-01-17 JP JP2000008271A patent/JP2000148494A/ja active Pending
- 2000-01-17 JP JP2000008263A patent/JP2000148480A/ja not_active Withdrawn
- 2000-01-17 JP JP2000008268A patent/JP2000148491A/ja active Pending
- 2000-01-17 JP JP2000008265A patent/JP2000148490A/ja not_active Withdrawn
- 2000-01-17 JP JP2000008269A patent/JP2000148492A/ja active Pending
- 2000-01-17 JP JP2000008266A patent/JP2000181708A/ja not_active Withdrawn
-
2002
- 2002-07-01 US US10/185,007 patent/US7000097B2/en not_active Expired - Fee Related
- 2002-10-28 JP JP2002312519A patent/JP3588755B2/ja not_active Expired - Lifetime
- 2002-10-28 JP JP2002312520A patent/JP3620530B2/ja not_active Expired - Lifetime
- 2002-10-28 JP JP2002312518A patent/JP3627737B2/ja not_active Expired - Lifetime
- 2002-10-28 JP JP2002312517A patent/JP2003131870A/ja not_active Withdrawn
-
2004
- 2004-09-21 JP JP2004273803A patent/JP3772899B2/ja not_active Expired - Lifetime
- 2004-10-21 JP JP2004306379A patent/JP3772900B2/ja not_active Expired - Lifetime
- 2004-11-22 JP JP2004337022A patent/JP3772901B2/ja not_active Expired - Lifetime
- 2004-12-22 JP JP2004370411A patent/JP3772902B2/ja not_active Expired - Lifetime
-
2005
- 2005-01-21 JP JP2005013797A patent/JP3772903B2/ja not_active Expired - Lifetime
- 2005-02-21 JP JP2005043359A patent/JP3741144B2/ja not_active Expired - Lifetime
- 2005-03-23 JP JP2005083005A patent/JP3741146B2/ja not_active Expired - Lifetime
- 2005-04-22 JP JP2005124391A patent/JP3772905B2/ja not_active Expired - Lifetime
- 2005-05-23 JP JP2005148862A patent/JP3741149B2/ja not_active Expired - Lifetime
- 2005-06-22 JP JP2005181820A patent/JP3772907B2/ja not_active Expired - Lifetime
- 2005-07-22 JP JP2005212306A patent/JP3852474B2/ja not_active Expired - Lifetime
- 2005-08-22 JP JP2005239264A patent/JP3852475B2/ja not_active Expired - Lifetime
- 2005-09-21 JP JP2005274178A patent/JP3815507B2/ja not_active Expired - Lifetime
-
2006
- 2006-07-18 JP JP2006195680A patent/JP3874022B2/ja not_active Expired - Lifetime
Also Published As
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3772901B2 (ja) | コンピュータシステム |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20051018 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20051219 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060124 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060206 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090224 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100224 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110224 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110224 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120224 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130224 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130224 Year of fee payment: 7 |