JP3718977B2 - Sampling synchronization method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sampling synchronization method for obtaining measurement values at different points by simultaneous sampling, and more particularly to a sampling synchronization method when devices at different points are not connected by an information transmission path.
[0002]
[Prior art]
Conventionally, as for how to synchronize between different points, in digital protection relay devices such as PCM current differential relays, a technique for exchanging information through an optical fiber transmission line and establishing synchronization has been established.
[0003]
For example, as shown in FIG. 9, when the protective relay devices A, B, and C are connected by a loop type optical fiber transmission line, the device C is changed from device A to device B → device C → device B → device A. The synchronization signal is transmitted through the loop transmission path that is turned back in (1). And as shown in FIG. 10, with respect to the transmission / reception of the synchronization signal, each of the devices A to C uses the intermediate time between the transmission timing and the reception timing as the sampling synchronization point from the presence of the transmission delay time in the transmission path. The sampling timing of each device can be matched.
The applicant of the present application has already proposed this sampling synchronization method (for example, JP-A-8-107631). In this method, a timing signal is sent to an information transmission line laid between different points and the round trip time is measured to obtain simultaneous sampling timing. Further, in order to suppress distortion of the generated timing signal, it is used together with a PLL circuit.
As another sampling synchronization method, as in Japanese Patent Laid-Open No. 9-288141, distributed terminal processing devices receive time information from artificial satellites of a radio positioning / navigation system (GPS), and frequency information is obtained from the time information. Some generate a signal and use this signal to obtain a sampling signal in an analog PLL circuit using a voltage controlled oscillator.
In the conventional method using GPS, it is not necessary to install a transmission path between different points, but synchronization becomes impossible when time information from the GPS is interrupted. In order to prevent this, the sample-and-hold circuit holds the input of the voltage-controlled oscillator. However, in this hold state, the oscillation frequency of the voltage-controlled oscillator varies and accurate sampling synchronization cannot be performed.
[0004]
[Problems to be solved by the invention]
A conventional sampling synchronization method (Japanese Patent Laid-Open No. Hei 8-107631) uses a dedicated optical fiber transmission for connecting a non-protective relay device such as a fault location device or a system observation device of an electric power system. Laying the road becomes difficult from the viewpoint of facilities and cost.
[0005]
Therefore, these devices cannot perform sampling synchronization using a conventional transmission line.
[0006]
An object of the present invention is to provide a synchronization method capable of obtaining a reliable sampling synchronization while making it unnecessary to transmit a sampling synchronization signal between devices at different points.
[0007]
[Means for Solving the Problems]
According to the present invention, each sampling device receives a pulse having a fixed period generated by a radio positioning / navigation system (GPS), and obtains a sampling synchronization signal from each pulse using a phase-locked loop circuit or the like. Further, synchronization confirmation and synchronism determination can be obtained, and the following method is characterized.
[0008]
(First invention)
A sampling synchronization method for obtaining measured values at different points by simultaneous sampling,
A receiver that receives pulses of a fixed period transmitted from satellites of a radio positioning / navigation system at different points;
A digital phase-locked loop circuit whose free-running frequency is controlled according to the comparison result of the phase comparator using the pulse received by each receiver as the phase comparison pulse of the phase comparator and the oscillation pulse of the crystal oscillator as the clock The received pulse is multiplied to obtain a sampling synchronization pulse at different points, and whether or not there is a pulse reception with a certain period within a synchronization determination range determined before and after the phase comparison time by the digital phase lock loop circuit A sampling synchronization circuit having a synchronization determination circuit for determining a synchronization state and performing forced synchronization control when asynchronous is detected ;
And a sampling device body for sampling measurement values at different points at the timing of each sampling synchronization pulse.
[0010]
( Second invention)
The sampling synchronization circuit includes a continuous synchronization confirmation circuit that performs synchronization confirmation when synchronization determination by the synchronization determination circuit is continuously obtained a predetermined number of times or more.
[0011]
( Third invention)
The sampling synchronization circuit is provided with a phase difference measurement circuit that determines the synchronism from the allowable time of the phase difference when the phase of the received pulse is compared.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a configuration diagram of a failure point locating device showing a basic configuration of the present invention. The sampling devices 1 and 2 of the failure point locating device show the configuration of the device 1 as a representative.
[0013]
Artificial satellites A _{1 to} A ₃ are _three of the 24 satellites provided in the wireless positioning / navigation system (GPS), and ranging signals and orbit information are transmitted from the satellites to the ground.
[0014]
From these artificial satellites A _{1 to} A ₃ , pulses of 1 minute period or 1 second period are transmitted as time information. The sampling devices 1 and 2 receive these pulses with the GPS receiver 11 through the antenna, and have a constant period. As a synchronization pulse a. The sampling synchronization circuit 12 takes in the synchronization pulse a from the receiver 11 and obtains multiplied pulses b and c having a phase lock loop and synchronized therewith as sampling synchronization pulses.
[0015]
Multiplied pulse b and c are, for example, as shown in FIG. 2, with respect to the sync pulse a of IH _Z, a pulse of 50H _Z / 60H _Z pulse, or 600H _Z / 720H _Z.
[0016]
The sampling device body 13 samples the current and voltage of the power system line at the installation location using the sampling synchronization pulse b or c. The failure point locator main body 3 receives the sampling data from the sampling devices 1 and 2 wirelessly or by wire, and determines the failure point from these sampling data. The failure point locator main body 3 may be provided together with the sampling devices 1 and 2 in some cases.
[0017]
With the above configuration, the sampling devices 1 and 2 can perform sampling synchronization without using a sampling synchronization transmission path. Note that the sampling of the sampling devices 1 and 2 is dependently synchronized by pulses with a constant period received from the artificial satellites A1 to A3.
[0018]
FIG. 3 shows a first embodiment of the sampling synchronization circuit 12. The pulse a having a constant period from the GPS receiver 11 is used as one of the phase comparison pulses of the phase comparison circuit 14 and also as a synchronization control reference clock signal of the synchronization control circuit 15.
[0019]
The digital PLL (phase-locked loop) circuit 16 uses the oscillation pulse of the crystal oscillator 17 as a clock, and the free-running frequency is controlled according to the phase control signal that is the comparison result from the phase comparison circuit 14.
[0020]
The frequency dividing (counter) circuit 18 counts the pulse frequency from the PLL circuit 16 and obtains the sampling synchronization pulses b and c obtained by frequency division. Further, the frequency dividing circuit 18 gives the divided pulse (pulse having a period of 1 second or 1 minute equivalent to the pulse a) as the comparison input d of the phase comparison circuit 14.
[0021]
The synchronization control circuit 15 reloads or resets the frequency dividing circuit 18 at the period of the pulse a. As a result, pulses b, c, and d having the same timing as the pulse a are obtained.
[0022]
When the phase of the free-running timing of the PLL circuit 16 advances with respect to the pulse a having a fixed period, the sampling synchronization circuit 12 having the above configuration delays the phase by lowering the frequency of the PLL circuit 16 from a steady value. Conversely, when the phase of the free-running timing is delayed, the phase is advanced by raising the frequency of the PLL circuit 16 from the steady value. By such a phase lock loop, sampling pulses b and c synchronized with the pulse a can be obtained.
[0023]
FIG. 4 shows a second embodiment of the sampling synchronization circuit 12. 3 differs from FIG. 3 in that a synchronization determination circuit 19 is provided.
[0024]
The synchronization determination circuit 19 decodes a pulse from the PLL circuit 16 or a pulse from the frequency divider circuit 18, thereby timing signals having a synchronization determination range before and after the phase comparison time by the phase comparison circuit 14 (for example, ± 20 μs). It is determined whether or not it is in a synchronized state based on whether or not the pulse a is obtained from the receiver 11 at this timing.
[0025]
This synchronization determination is as shown in FIG. 5, and synchronization / asynchronism is obtained with the synchronization determination range before and after the pulse a. The determination result is the control condition e of the synchronous control circuit 15, and when asynchronous is detected, the synchronous control circuit 15 forcibly reloads or resets to synchronize with the pulse a.
[0026]
By providing this synchronization determination circuit 19, the synchronization with the pulse a can be determined for the sampling synchronization pulse that is dependently synchronized with the pulse a, and reliable synchronization can be obtained.
[0027]
FIG. 6 shows a third embodiment of the sampling synchronization circuit 12. 4 is different from FIG. 4 in that continuous synchronization confirmation circuits 20A and 20B for synchronization determination are provided.
[0028]
The continuous synchronization confirmation circuit 20A counts the number of times when the synchronization determination circuit 19 makes an asynchronous determination, obtains a signal e when the asynchronous determination result is continuously a predetermined number of times, and thereby reloads by the synchronization control circuit 15 Or, forcibly reset.
[0029]
The continuity confirmation circuit 20B counts the number of times when the synchronization determination circuit 19 makes the synchronization determination, and confirms the synchronization state when the synchronization determination result is continuously a predetermined number of times.
[0030]
As a result, the determination is made on the condition that the synchronous / asynchronous determination is continuously obtained a predetermined number of times or more, and the frequency of disturbance of the divided sampling signal can be reduced, and a more stable sampling synchronous signal can be obtained. Obtainable.
[0031]
FIG. 7 shows a fourth embodiment of the sampling synchronization circuit 12. 3 is different from FIG. 3 in that a phase difference measuring circuit 21 is provided.
[0032]
As illustrated in FIG. 8, the phase difference measurement circuit 21 includes a priority determination circuit 21A and a start / stop circuit 21B. The priority determination circuit 21A uses the pulse generated at the earlier timing among the pulse a from the GPS receiver 11 and the constant cycle pulse from the PLL circuit 16 or the frequency dividing circuit 18 as a start pulse, and is generated at the later timing. A judgment output with a pulse as a stop pulse is obtained.
[0033]
The start / stop circuit 21B uses the start signal from the priority determination circuit 21A as a set signal for the flip-flop F / F, uses the stop signal as a reset signal for the flip-flop F / F, and sets the period from the set to the reset of the counter CNT. By counting the clock as an enable signal, the counter CNT obtains a count value (measurement value) proportional to the phase difference.
[0034]
As a result, a phase difference measurement value between the self-running timing by the PLL circuit 16 and the received pulse from the GPS receiver 11 can be obtained, and this phase difference measurement value can be obtained by using a computer or a digital comparator. It is possible to determine whether the signal is within the range, that is, to determine whether it is synchronous or asynchronous, and to adjust the disturbance frequency of the sampling signal, so that the stability of the sampling synchronous signal can be freely set.
[0035]
It is also possible to obtain more accurate determination by adding the continuous confirmation circuits 20A and 20B of FIG. 6 to the phase difference determination.
[0036]
【The invention's effect】
As described above, according to the present invention, each sampling device receives a pulse having a fixed period generated by the radio positioning / navigation system, and a sampling synchronization signal is obtained from each pulse using a phase-locked loop circuit or the like. In addition, since synchronization confirmation and synchronization determination can be obtained, reliable sampling synchronization can be obtained while eliminating the need to transmit sampling synchronization signals between devices at different points.
[Brief description of the drawings]
FIG. 1 is a diagram showing a basic configuration of the present invention.
FIG. 2 is a synchronization pulse waveform in FIG.
FIG. 3 is a sampling synchronization circuit showing a first embodiment of the present invention (part 1);
FIG. 4 is a sampling synchronization circuit showing a second embodiment of the present invention (part 2);
FIG. 5 shows synchronization determination timing by a synchronization determination circuit 19;
FIG. 6 is a sampling synchronization circuit showing a third embodiment of the present invention (part 3);
FIG. 7 is a sampling synchronization circuit showing a fourth embodiment of the present invention (part 4);
FIG. 8 shows an example of a phase difference measurement circuit in the fourth embodiment.
FIG. 9 shows an example of connection between a PCM relay and a transmission line.
FIG. 10 is a synchronization timing explaining a conventional sampling synchronization method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 2 ... Sampling device 3 ... Fault location device 11 ... GPS system receiver 12 ... Sampling synchronization circuit 13 ... Sampling device body 14 ... Phase comparison circuit 15 ... Synchronization control circuit 16 ... Digital type PLL circuit 17 ... Crystal oscillator 18 ... Frequency divider 19 ... Synchronization determination circuits 20A, 20B ... Continuous check circuit 21 ... Phase difference measurement circuit

Claims (3)

A sampling synchronization method for obtaining measured values at different points by simultaneous sampling,
A receiver that receives pulses of a fixed period transmitted from satellites of a radio positioning / navigation system at different points;
A digital phase-locked loop circuit whose free-running frequency is controlled according to the comparison result of the phase comparator using the pulse received by each receiver as the phase comparison pulse of the phase comparator and the oscillation pulse of the crystal oscillator as the clock The received pulse is multiplied to obtain a sampling synchronization pulse at different points, and whether or not there is a pulse reception with a certain period within a synchronization determination range determined before and after the phase comparison time by the digital phase lock loop circuit A sampling synchronization circuit having a synchronization determination circuit for determining a synchronization state and performing forced synchronization control when asynchronous is detected ;
A sampling synchronization system comprising: a sampling device main body that samples measurement values at different points at the timing of each sampling synchronization pulse. 2. The sampling synchronization system according to claim 1 , wherein the sampling synchronization circuit includes a continuous synchronization confirmation circuit that performs synchronization confirmation when synchronization determination by the synchronization determination circuit is continuously obtained a predetermined number of times or more. 3. The sampling synchronization system according to claim 1 , wherein the sampling synchronization circuit is provided with a phase difference measurement circuit that determines the synchronism based on the allowable time of the phase difference when the phase of the received pulse is compared.

Images