JP3711760B2 - Self-luminous display device - Google Patents

Description

となり、従来の１／９の静電容量となる。
【００３８】
そして、三つのＥＬ素子からなるＥＬ部における蓄積電荷Ｑ3は、ＥＬ素子一つにかけられる電圧をＶ（上述のように従来の一つのＥＬ素子にかけられる電圧と同じ）とした場合に、

となり、従来の１／３となる。
【００３９】
そして、一般に、静電容量による充電／放電現象により、ＥＬ素子の発光に寄与する実行電流は減少する。
特に、立ち上がり／立ち下がりにおいて、その減少率が極めて大きくなり、結果として、ＥＬ素子の発光応答性を著しく悪化させる。
第一例においては、上述のように従来に比較して、例えば、静電容量を１／９に減少させることが可能であり、ＥＬ素子の応答特性を大きく改善できる。
【００４０】
すなわち、このように静電容量を減少させた場合に、図５（Ａ）に示す従来のＥＬ素子においては、立ち上がり時に電流がすぐにピークに至らずになだらかに立ち上がり、立ち下がり時に電流がすぐに低下せずに尾を引いた状態となるのに対して、図５（Ｂ）に示す第一例の三段直列のＥＬ素子においては、立ち上がり時に、電流がすぐにピークに至り、立ち下がり時もほとんど尾を引かない状態とすることができる。
従って、第一例の三段直列のＥＬ素子においては、高速応答・正確な輝度制御が実現でき、高品位表示に有用である。
【００４１】
次に、本発明の実施の形態の第二例を図面を参照して説明する。
図６は第二例の自発光表示装置の一画素の構成を説明するための回路図であり、図７は上記一画素のＥＬ素子のカソードを除いた平面構造を示すものであり、図８は上記一画素の平面構造を示すものであり、図９は上記一画素の一部の断面構造を示すものである。
【００４２】
なお、第二例の自発光表示装置は、第一例の自発光表示装置が、ＥＬ素子のアノードをアクティブ素子に接続していたの対して、ＥＬ素子のカーソードをアクティブ素子に接合したものであり、その他の点については、第一例の自発光表示装置とほぼ同様の構成を有するものである。
また、第二例の自発光表示装置において、第一例の自発光表示装置と同様の構成要素には、同一の符号を付すとともに、その説明を一部省略する。
【００４３】
図６に示すように、第一例の自発光表示装置においては、第一例と同様に、選択トランジスタ３と、駆動トランジスタ５とを備えている。
そして、第二例においては、駆動トランジスタ５のソース電極が接地され、ドレイン電極に第一ＥＬ素子１１と、第二ＥＬ素子１２と、第三ＥＬ素子１３とが直列に接続され、さらに、第一ＥＬ素子１１と、第二ＥＬ素子１２と、第三ＥＬ素子１３とが直列にＥＬ用電源に接続されている。
また、図７及び図８の一画素の平面構造を参照して、一画素の構造をより具体的に説明すると、例えば、第一例と同様に、選択ライン１と、データライン２と、ＥＬ電源ライン１４と、ＧＮＤライン１５とが配置されている。なお、第二例においては、ＥＬ電源ライン１４の位置と、ＧＮＤライン１５の位置とが第一例の場合と入れ替わった状態となっている。
【００４４】
そして、上述のように選択トランジスタ３のドレイン電極３ｇ（図９に図示）がデータライン２に接続され、選択トランジスタ３のゲート電極３ａ（図９に図示）が選択ライン１に接続されている。
また、選択トランジスタ３のソース電極３ｂ（図９に図示）は、ゲート絶縁膜２３に設けられたコンタクトホールを介して接続ライン１６の一端に接続され、接続ライン１６の他端は駆動トランジスタ５のゲート電極５ａ（図９に図示）に接続されている。
【００４５】
また、駆動トランジスタ５は、上述のように、そのゲート電極５ａに接続ライン１６が接続されるとともに、ドレイン電極５ｇ（図９に図示）にＧＮＤライン１５が接続されている。そして、駆動トランジスタ５のソース電極５ｂ（図９に図示）に、第一ＥＬ素子１１のカソード１１ｂが接続され、第二ＥＬ素子１２のカソード１２ｂが第一ＥＬ素子１１のアノード１１ａに接続され、第三ＥＬ素子１３のカソード１３ｂが第二ＥＬ素子１２のアノード１２ａに接続され、第三ＥＬ素子１３のアノード１３ａがＥＬ電源ライン１４に接続されている。付加容量１０は、ＧＮＤライン１５に沿った接続ライン１６とその上に設けられたゲート絶縁膜２３と、ゲート絶縁膜２３上に設けられ、引き回し線１４ａとコンタクトホールを介し接続されたキャパシタ電極１０ａと、から構成されている。
【００４６】
また、図９の断面構造に示すように、自発光表示装置の各画素は、ガラス基板２０上に形成されるものであり、ガラス基板２０上には、発光部１１ｃ、１２ｃ、１３ｃの発光領域（図９においては１１ｃだけを図示）を除く部分にブラックマスク２１（例えば、反射防止膜としての酸化クロム）が形成されている。そして、このブラックマスク２１の層上に、絶縁膜２２が形成されている。そして、絶縁膜２２上の選択トランジスタ３及び駆動トランジスタ５となる部分に表面に陽極酸化膜を有するゲート電極３ａ、５ａが形成されている。
【００４７】
そして、上述のようにゲート電極３ａ、５ａが形成された絶縁膜２２上を、ゲート電極３ａ、５ａも覆ってしまうようにゲート絶縁膜２３（例えば、ＳｉＮ）が形成されている。また、ゲート絶縁膜２３の下には、選択トランジスタ３のゲート電極３ａに接続される選択ライン１（図９において図示略）や、選択トランジスタ３のソース電極３ｂと駆動トランジスタ５のゲート電極５ａとを繋ぐ接続ライン１６（ゲート配線となる、例えば、Ａｌ合金）やＥＬ電源ライン１４等が形成されている。なお、図９において、接続ライン１６とゲート電極５ａとは離れているが、図８等に示すように接続されている。
【００４８】
そして、ゲート絶縁膜２３上に、選択トランジスタ３及び駆動トランジスタ５のチャネルが形成される領域となるｉ−Ｓｉ層３ｃ、５ｃ（真性半導体層）が形成され、その上にブロッキング層３ｄ、５ｄが形成され、該ブロッキング層３ｄ、５ｄの左右にドレイン領域３ｅ、５ｅ（ｎ+Ｓｉ）とソース領域３ｆ、５ｆ（ｎ+Ｓｉ）とがそれぞれ形成されている。また、ドレイン領域３ｅ、５ｅ上にドレイン電極３ｇ、５ｇ（例えば、Ａｌ合金）が設けられ、ソース領域３ｆ、５ｆ上にソース電極３ｂ、５ｂが設けられている。
【００４９】
また、上述のように、選択トランジスタ３のドレイン電極３ｇは、図９に図示しないデータライン２に接続され、ソース電極３ｂは、接続ライン１６に接続されている。
また、上述のように、駆動トランジスタ５のドレイン電極５ｇは、図９に図示しないＧＮＤライン１５に接続され、ソース電極５ｂは、第一ＥＬ素子１１のカソード１１ｂに接続されている。
【００５０】
また、上記ゲート絶縁膜２３上には、第一〜第三ＥＬ素子１１、１２、１３のアノード１１ａ、１２ａ、１３ａ（例えば、ＩＴＯ、図９においては、一つのアノード１１ａだけを図示）が形成されている。なお、第三ＥＬ素子１３のアノード１３ａは、図７等に示すようにＥＬ電源ライン１４に接合される。
そして、上記ゲート絶縁膜２３上に形成された選択トランジスタ３、駆動トランジスタ５及びアノード１１ａ、１２ａ、１３ａ上には、オーバーコート層２４（例えば、ＳｉＮ）が形成されている。なお、オーバーコード層２４は、選択トランジスタ３及び駆動トランジスタ５を保護するとともに、アノード１１ａ、１２ａ、１３ａとカソード１１ｂ、１２ｂ、１３ｂとの間の上記層間絶縁膜となるものである。
【００５１】
そして、上記オーバーコート層２４には、上記駆動トランジスタ５のソース電極５ｂと、第一ＥＬ素子１１のカソード１１ｂとを接合する部分、発光部１１ｃ、１２ｃ、１３ｃとなる有機ＥＬ層がアノード１１ａ、１２ａ、１３ａに接合する部分（発光領域、なお、図９においては、一つのアノード１１ａに発光部１１ｃが接続する部分だけを図示）、アノード１１ａ、１２ａにカソード１２ｂ、１３ｂが接合する部分（図９において図示略）にそれぞれコンタクトホール等となる開口部が形成されている。
【００５２】
また、オーバーコート層２４（層間絶縁膜）の開口部の周縁部は、開口部が上に向かうにつれて広くなるようにテーパ状に形成されている。
そして、上記アノード１１ａ、１２ａ、１３ａ上のオーバーコート層２４（層間絶縁膜）の開口部の部分に開口部より広い範囲に渡って発光部１１ｃ、１２ｃ、１３ｃとなる有機ＥＬ層が形成されている。
そして、この有機ＥＬ層である発光部１１ｃ、１２ｃ、１３ｃ上にそれぞれ発光部１１ｃ、１２ｃ、１３ｃより広い範囲に渡ってカソード１１ｂ、１２ｂ、１３ｂが形成されている。なお、第一ＥＬ素子１１のカソード１１ｂは駆動トランジスタ５のソース電極５ｂに至るように形成されてソース電極５ｂに接続され、第二ＥＬ素子１２のカソード１２ｂは第一ＥＬ素子１１のアノード１１ａに至るように形成されてアノード１１ａに接合され、第三ＥＬ素子１３のカソード１３ｂは第二ＥＬ素子１２のアノード１２ａに至るように形成されてアノード１２ａに接合される。
【００５３】
また、上述のようにオーバーコート層２４（層間絶縁膜）のアノード１１ａ、１２ａ、１３ａ上の開口部の周縁部がテーパとなっているので、この周縁部上に形成された発光部１１ｃ、１２ｃ、１３ｃ及びカソード１１ｂ、１２ｂ、１３ｂは、上記テーパの角度に沿ってアノード１１ａ、１２ａ、１３ａに至り、オーバーコード層２４の開口部で、アノード１１ａ、１２ａ、１３ａに対向するようになっている。
そして、上記開口部の周縁部のテーパの角度、すなわちアノード１１ａ、１２ａ、１３ａが形成された平面と、オーバーコート層２４の開口部の周縁部の内面とがなす角度θは、２０度〜５０度となっている。
【００５４】
従って、オーバーコート層２４が形成された後に形成される上記発光部１１ｃ、１２ｃ、１３ｃ及びカソード１１ｂ、１２ｂ、１３ｂは、上記２０度〜５０度の角度でアノード１１ａ、１２ａ、１３ａに至り、アノード１１ａ、１２ａ、１３ａに対向する部分でアノード１１ａ、１２ａ、１３ａと平行となる。
そして、カソード１１ｂ、１２ｂ、１３ｂ及びオーバーコート層２４上には、パッシベーション層２５が形成され、該パッシベーション層２５が、その下の各層を保護するようになっている。
【００５５】
このような構成を有する第二例の自発光表示装置によれば、第一例の自発光表示装置と同様の作用効果を奏することができるとともに、さらに、直列に繋がれた複数の第一〜第三ＥＬ素子１１、１２、１３のうちの一端側の第一ＥＬ素子のカソード１１ｂが駆動トランジスタ５のソース電極５ｂに接続されることにより、他端側の第三ＥＬ素子１３のアノード１３ａがＥＬ電源ライン１４に接続され、駆動トランジスタ５のドレイン電極５ｇがＧＮＤライン１５に接続されて接地されているので、駆動トランジスタ５のゲート電位が直接ＧＮＤレベルに対して定まるので、コントロール性、応答速度に優れたものとすることができる。
【００５６】
なお、第一例においては、その断面構造を図示しなかったが、第一例の自発光素子の断面構造は、第二例の断面構造において、駆動トランジスタ５のソース電極５ｂに第一ＥＬ素子１１のカソード１１ｂが接続されていたのに対して、カソード１１ｂがソース電極５ｂに接続されず、ソース電極５ｂに第一ＥＬ素子１１のアノード１１ａが接続された状態となった以外は、ほぼ同様の断面構造を有するものである。なお、それ以外にも、図９に図示されない部分においては、上述のように、第一例と第二例とで異なる部分がある。
【００５７】
次ぎに、本発明の実施の形態の第三例の自発光表示装置を図面を参照して説明する。
図１０は第三例の自発光表示装置の一画素の構成を説明するための回路図であり、図１１及び図１１は第三例の自発光表示装置の駆動方法を説明するための複数画素を含む回路図である。
【００５８】
なお、第三例の自発光表示装置は、第一例の自発光表示装置の選択トランジスタ３と駆動トランジスタ５と付加容量１０とに代えて、一つのＤＧメモリＴＦＴ３５を用いたものであり、その他の点については、第一例の自発光表示装置とほぼ同様の構成を有するものである。
また、第三例の自発光表示装置において、第一例の自発光表示装置と同様の構成要素には、同一の符号を付すとともに、第三例の自発光表示装置において第一例と同様の構成については、その説明を一部省略する。
【００５９】
図１０に示すように、第三例の自発光表示装置においては、選択ライン１（Select）に第一ゲート電極３１が接続され、データライン２(Data)に第二ゲート電極３２が接続され、ＥＬ電源ライン１４にドレイン電極３３が接続され、第一ＥＬ素子１１にソース電極３４が接続されたＤＧメモリＴＦＴ３５を備えている。そして、駆動トランジスタ５とＤＧメモリＴＦＴ３５とが異なる以外は、第一例と同様に、三つの第一〜第三ＥＬ素子１１、１２、１３がソース電極３４に直列に接続されている。
すなわち、ソース電極３４に、第一例の図３に示される構造と同様に、第一ＥＬ素子１１のアノード１１ａが接続され、第二ＥＬ素子１２のアノード１２ａが第一ＥＬ素子１１のカソード１１ｂに接続され、第三ＥＬ素子１３のアノード１３ａが第二ＥＬ素子１２のカソード１２ｂに接続され、第三ＥＬ素子１３のカソード１３ｂが接地され、すなわち、ＧＮＤライン１５に接続されている。
【００６０】
上記ＤＧメモリＴＦＴ３５は、ゲートを二つ有するとともに、キャリアをトラップすることにより、メモリ性を有するものとなっている。
そして、ＤＧメモリＴＦＴ３５においては、例えば、可視光が入射されると電子−正孔を内部に発生させるチャネル領域（ｉ−ａ−Ｓｉ）と、該チャネル領域上の左右側部にそれぞれ形成されたソース領域及びドレイン領域（ｎ＋Ｓｉ）と、ソース領域、ドレイン領域の接続されたソース電極３４、ドレイン電極３３と、上記チャネル領域より基板側にチャネル領域との間に下部ゲート絶縁膜を介して設けられた透明な下部ゲート電極（第一ゲート電極３１）と、上記チャネル領域の上方側、すなわち、基板の反対側に、チャネル領域との間に上部ゲート絶縁膜を介して設けられた上部ゲート電極（第二ゲート電極３２）を備えたものである。なお、下部ゲート電極と上下ゲート電極とは、回路図上で上下逆になっている。
【００６１】
そして、上記下部ゲート絶縁膜は、ＳｉＮからなるとともに、その表層部（チャネル領域に接する側）に、ストイオキメトリなＳｉとＮとの比が３：４なのに対して、ＳｉとＮとの比をストイオキメトリからずらして、１：１程度としたＳｉリッチなトラップ領域が形成されている。
そして、このトラップ領域は、キャリア（正孔、電子）をトラップすることができるようになっている。
【００６２】
このようなｎチャネル型ＤＧメモリＴＦＴ３５は、例えば、第二ゲート電極３２のゲート電圧を０Ｖとするとともに、ソース−ドレイン間に電圧を印加した状態で、例えば、第一ゲート電極３１のゲート電圧を上げていった場合のドレイン電流の変化と、次いで、第一ゲート電極３１のゲート電圧を下げっていった場合のドレイン電流の変化とが異なるヒステリシス特性を有するものとなっている。そして、このようなＤＧメモリＴＦＴ３５においては、トラップ領域にトラップされたキャリアの有無やキャリアの極性等により、第一ゲート電極３１のゲート電圧が同じでも、ドレイン電流が流れる場合と流れない場合が生じるようになっている。
【００６３】
例えば、ＤＧメモリＴＦＴ３５をｎチャネルとし、トラップ領域に電子が蓄積している場合には、トラップ領域に蓄積された電子の電界によりチャネル領域に正孔が誘起され、第一ゲート電極３１にゲート電圧を印加した場合に、このゲート電圧がチャネル形成が可能なしきい値電圧より僅かに高くても、トラップ領域に蓄積している電子の電界に相殺されて、チャネル領域にドレイン電流を流すことが可能な連続したチャネルが形成されず、ドレイン電流が流れないことになる。
【００６４】
一方、トラップ領域に正孔が蓄積している場合には、トラップ領域に蓄積した正孔の電界によりチャネル領域に電子が誘起され、第一ゲート電極３１にゲート電圧を印加した場合に、このゲート電圧がチャネル形成が可能なしきい値電圧より僅かに低くくても、トラップ領域に蓄積した正孔との相互作用により、チャネル領域にドレイン電流を流すことが可能な連続したチャネルが形成され、ドレイン電流が流れることになる。
従って、トラップ領域における蓄積されたキャリアの有無及び極性により、第一ゲート電極３１に同じレベルのゲート電圧を印加しても、ドレイン電流が流れてＥＬ素子が発光する場合と、ドレイン電流が流れずにＥＬ素子が発光しない場合とがある。
【００６５】
また、トラップ領域へのキャリアの蓄積方法は、例えば、ソース・ドレイン間に＋１０Ｖの電位差の状態で第一ゲート電極を０Ｖとして、第二ゲート電極に正のゲート電圧を印加した場合に、ｎチャネルが形成され、ソース領域及びドレイン領域を形成するｎ+層からキャリア領域に電子が移動し、該電子がトラップ領域にトラップされる。この場合、可視光の入射にかかわらず、比較的短時間で電子は蓄積される。
また、この状態でキャリア領域に光を照射するとともに、第二ゲート電極に負のゲート電圧を印加した場合に、キャリア領域に光の照射により正孔−電子対が生じるとともに、この正孔−電子対の電子が上記ｎ+層からなるソース領域及びドレイン電極に移動し、正孔がトラップ領域に取り込まれて上述の電子と置換され、さらに、正孔が蓄積する。
また、トラップ領域への電子の蓄積に際しては、キャリア領域に光を照射するものとしても良い。
【００６６】
次ぎに、図１０及び図１１を参照して、自発光表示装置におけるＥＬ素子の駆動方法を説明する。
なお、このＥＬ素子の駆動においては、横（行）方向に一行分選択されたの各画素のＤＧメモリＴＦＴ３５にＥＬ素子の発光、非発光を示すデータを書き込む、すなわち、ＤＧメモリＴＦＴ３５にトラップ領域に正孔もしくは電子を蓄積させる書き込み工程と、全画素において、ＤＧメモリＴＦＴ３５に記憶された発光、非発光のデータに基づいて表示を行う表示工程とを繰り返し行うようになっている。
また、書き込み工程を行う度に、データの書き込みを行う行を一行分ずつずらしていくようになっており、最終的に全行の画素のＤＧメモリＴＦＴ３５にデータを書き込むようになっており、このようにして一フレーム分のデータの書き込みと表示が行われるようになっている。
【００６７】
そして、上記データの書き込み工程においては、選択された横一行の画素に沿って配線された選択ライン１（ここではアドレスｎの選択ライン１）に＋３５Ｖの電圧を印加し、他の行列に沿って配線された選択ライン１（ここではアドレスｎ＋１等のアドレスｎ以外の選択ライン）には、電圧は０Ｖとする。
そして、選択された横一行の画素に対応する選択ライン１にアドレス電圧を印加することにより、横一行の画素の選択ライン１に接続されたＤＧメモリＴＦＴ３５の第一ゲート電極にアドレス電圧が印加される。
【００６８】
また、選択された選択ライン１に印加するアドレス電圧は、トラップ領域にチャネルの形成を阻害するキャリア（ここでは、電子）が蓄積されていても、ドレイン電流を流すことが可能な高い電圧（例えば、ここでは＋３５Ｖ）とする。
また、各画素のＤＧメモリＴＦＴ３５のドレイン電極３３が接続されたＥＬ電源ライン１４には、常時電圧（ここでは、例えば、＋１０Ｖ）が印加されているものとする。
これにより、選択ライン１に接続された第一ゲート電極３１にドレイン電流を流すことが可能な電圧が印加されるので、ＤＧメモリＴＦＴ３５のソース電極３４に接続された第一〜第三ＥＬ素子１１、１２、１３に電流が流れ、選択された横一行の画素において、第一〜第三ＥＬ素子１１、１２、１３がアドレス発光する。
【００６９】
そして、第一〜第三ＥＬ素子１１、１２、１３がアドレス発光することにより、ＤＧメモリＴＦＴ３５のチャネル領域に光が照射され、上述のようにチャネル領域に正孔−電子対が発生することになる。
ここで、各画素の縦の各列毎に配線されたデータライン２に、上記横一行の各画素の発光、非発光のデータに基づいて電圧が印加される。すなわち、アドレスがｎの選択ライン１に接続された横一行の画素の一つの画素（例えばｍ番目の画素）を発光を維持させない場合には、その画素が接続されたデータライン２に正の電圧（ここでは、例えば、＋２０Ｖ）を印加する。
【００７０】
また、逆にアドレスがｎの選択ライン１に接続された横一行の画素のうちの一つの画素（例えば、ｍ＋１番目の画素）を発光を維持させる場合には、その画素が接続されたデータライン２に負の電圧（ここでは、例えば、−２０Ｖ）を印加する。すなわち、横一行の各画素において、その画素を発光させるか否かのデータに基づいて、各画素が接続されたデータライン２に正の電圧もしくは負の電圧を印加する。
【００７１】
そして、データライン２は、ＤＧメモリＴＦＴ３５の第二ゲート電極３２に接続されており、上述のように第一〜第三ＥＬ素子１１、１２、１３が発光してＤＧメモリＴＦＴ３５のチャネル領域に光が照射されて正孔−電子対が生じた状態で、第二ゲート電極３２に電圧が印加された場合には、その電圧が正の場合に、ＤＧメモリＴＦＴ３５のトラップ領域に電子が蓄積し、その電圧が負の場合にＤＧメモリＴＦＴ３５のトラップ領域に正孔が蓄積されることになる。
【００７２】
そして、上述のように選択された一つの選択ライン１に接続された一行の画素の各画素において、それらのＤＧメモリＴＦＴ３５のトラップ領域に電子もしくは正孔が蓄積された段階で書き込み工程を終了し、表示工程となる。
そして、表示工程においては、全ての選択ライン１に、上述のしきい値電圧より低い電圧、すなわち、ＤＧメモリＴＦＴ３５のトラップ領域にトラップされたキャリアの有無やキャリアの極性により、ドレイン電流が流れる場合と流れない場合が生じる電圧（ここでは、例えば、＋１５Ｖ）が印加される。
【００７３】
ＥＬ電源ライン１４には、上述のように常時＋１０Ｖの電圧が印加された状態とされ、また、このとき各データライン２の電圧は０Ｖとなる。
そして、上述の選択された横一行の画素においは、それらの画素のＤＧメモリＴＦＴ３５のトラップ領域に蓄積されたキャリアの極性に基づいて発光もしは非発光の状態となる。
【００７４】
例えば、上述のように電子がトラップ領域に蓄積された選択ライン１のアドレスがｎで、データライン２がｍ番目の画素において、そのＤＧメモリＴＦＴ３５のトラップ領域に電子が蓄積しているので、上述のように選択ライン１から第一ゲート電極３１に低い電圧が印加されても、トラップ領域に蓄積された電子の電界の影響によりチャネル領域に連続したｎチャネルが形成されず、ドレイン電流が流れない状態となり、第一〜第三ＥＬ素子１１、１２、１３は非発光状態となる。
【００７５】
一方、上述のように正孔がトラップ領域に蓄積された選択ライン１のアドレスがｎで、データライン２がｍ＋１番目の画素において、そのＤＧメモリＴＦＴ３５のトラップ領域に正孔が蓄積しているので、上述のように選択ライン１から第一ゲート電極３１に低い電圧が印加された場合に、トラップ領域に蓄積された正孔の電界との相互作用により、チャネル領域に連続したチャネルが形成され、ドレイン電流が流れた状態となり、第一〜第三ＥＬ素子１１、１２、１３は発光を維持することになる。
【００７６】
また、上述の書き込み工程において、データが書き込まれた横一行の画素以外の他の行の画素においては、最後に書き込まれたデータに基づいて、一列の各画素が発光もしくは非発光の状態となる。例えば、アドレスがｎ＋１の選択ライン１に接続された横一行の各画素においては、前のフレームにおいて書き込まれたデータ（トラップするチャージが正孔又は電子）に基づいて発光もしくは非発光の状態となる。
また、アドレスがｎ−１の選択ライン１に接続された横一行の各画素においては、上述の書き込み工程の前の回の書き込み工程においては書き込まれたデータに基づいて発光もしくは非発光の状態となる。
【００７７】
そして、以上のような書き込み工程と表示工程とを繰り返すとともに、書き込み工程毎に書き込みを行う横一行の画素を一行ずつずらした場合には、１フレーム分の表示において、画素の横の行の数だけ表示が行われる。すなわち、点滅した状態で表示が行われることになるが、点滅速度が有る程度の速度以上となれば、人間の目には点滅を認識することができす、連続して画像が表示された状態に見えることになる。また、書き込み工程の度に、横一行の画素が全ての光ることになるが、高デューティー駆動で横一行の画素がアドレス時間が極めて短ければ、やはり人間の目で認識することができず、書き込み工程により表示に大きな影響がでることがない。
【００７８】
従って、上述のようにアクティブ素子としてＤＧメモリＴＦＴ３５を用いても連続した表示が可能となる。
そして、第三例の自発光表示装置においては、第一例の自発光表示装置と比較してその駆動動作が上述のように少し異なってはいるが、第一例の場合と同様の効果、すなわち、アクティブ素子における損失電力の低減による全消費電力の低減や、ＥＬ素子における静電容量の低下に基づく高速応答・正確な輝度制御の実現等の効果を奏することができる。
【００７９】
さらに、第三例の自発光表示装置によれば、従来のようにアクティブ素子として、一画素毎に、選択トランジスタ３と駆動トランジスタ５との二つを用いる必要がなく、一つのＤＧメモリＴＦＴ３５を用いれば良いので、自発光表示装置の構成の簡略化並びに発光領域の面積拡大を図ることができる。すなわち、アクティブ素子の数を１／２にすることが可能となり、自発光表示装置の製造時における歩留まりの向上等を図ることができる。
【００８０】
なお、ＦＥＴ型のトランジスタにおいては、電流の流れる方向とキャリア（チャネル）の種類（正孔もしくは電子）により、ドレインとソースとが決まるので、上述の記載において、ドレインとソースとを入れ替えるものとしても良い。
また、一画素当たりのＥＬ素子の数は、三つに限定されるものではなく、複数ならば、二つでも、四つ以上でも良いが、アクティブ素子における損失電力の低下や、ＥＬ素子の静電容量の低下の面では、一画素当たりのＥＬ素子の数が多い方が良く、製造工程の容易さを考慮した場合には、一画素当たりのＥＬ素子の数があまり多く無い方が好ましい。
【００８１】
【発明の効果】
本発明の請求項１記載の自発光表示装置によれば、複数個の自発光素子を電気的に直列にアクティブ素子に接続するものとすることにより、複数個の自然発光素子を合わせた輝度レベルと同じ輝度レベルの一個の自然発光素子をアクティブ素子に接続した場合に比較して、アクティブ素子を流れる電流の値を低くすることができるので、アクティブ素子における損失電力を低減することができる。従って、上述のような構成とすることにより、アクティブ素子における損失電力を低減して自発光表示装置全体の消費電力の低減を図ることができる。
【００８２】
本発明の請求項２記載の自発光表示装置によれば、自発光素子のカソードがアクティブ素子に接続されことにより、自発光素子のアノードが、例えば、自発光素子用の電源に接続されることになるとともに、アクティブ素子の端子の一つが接地されることになる。
この際には、アクティブ素子をオンオフする信号の電位が、直接グランドレベルに対して定まるので、コントロール性、応答速度に優れる利点がある。
【００８３】
本発明の請求項３記載の自発光表示装置によれば、各画素において、それぞれ一個のアクティブ素子により、自発光素子を制御することができるので、従来のように各画素において二つのトランジスタを用いた場合よりも、自発光表示装置の構成を簡略化することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態の第一例の自発光表示装置の一画素の構成を説明するための回路図である。
【図２】第一例の自発光表示装置の一画素の平面構造を説明するための図面である。
【図３】第一例の自発光表示装置の一画素の平面構造を説明するための図面である。
【図４】第一例の自発光表示装置の駆動トランジスタにおける損失電位と従来例のＥＬ表示装置の駆動トランジスタにおける損失電位との違いを説明するためのグラフである。
【図５】第一例の自発光表示装置のＥＬ素子における電流特性と、従来例のＥＬ表示装置のＥＬ素子における電流特性との違いを説明するためのグラフである。
【図６】本発明の実施の形態の第二例の自発光表示装置の一画素の構成を説明するための回路図である。
【図７】第二例の自発光表示装置の一画素の平面構造を説明するための図面である。
【図８】第二例の自発光表示装置の一画素の平面構造を説明するための図面である。
【図９】第二例の自発光表示装置の一画素の断面構造を説明するための図面である。
【図１０】本発明の実施の形態の第三例の自発光表示装置の一画素の構成を説明するための回路図である。
【図１１】第三例の自発光表示装置における駆動方法を説明するための回路図である。
【図１２】第三例の自発光表示装置における駆動方法を説明するための回路図である。
【図１３】従来例のＥＬ表示装置の一画素の構成を説明するための回路図である。
【図１４】従来例のＥＬ表示装置の駆動トランジスタにおける損失電位を説明するためのグラフである。
【符号の説明】
３ 選択トランジスタ（アクティブ素子）
５ 駆動トランジスタ（アクティブ素子）
１１ 第一ＥＬ素子（自発光素子）
１１ａ アノード
１１ｂ カソード
１２ 第二ＥＬ素子（自発光素子）
１２ａ アノード
１２ｂ カソード
１３ 第三ＥＬ素子（自発光素子）
１３ａ アノード
１３ｂ カソード
３５ ＤＧメモリＴＦＴ（アクティブ素子、メモリ性を有するトランジスタ）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a self-luminous display device including a self-luminous element driven by an active element, and more particularly to a self-luminous display device capable of displaying with low power consumption.
[0002]
[Prior art]
As a display device using a self-light emitting element, an EL display device using an electroluminescence (hereinafter referred to as EL) element, particularly an organic EL element is known.
The organic EL element has a feature that the quantum efficiency is almost constant over a wide current density region. This is almost stable regardless of the change with time (high resistance, increased dark spots) of the organic EL element and the environmental temperature. Taking advantage of this feature, it is known that uniform and high-precision brightness control can be performed by carrying out constant current drive. This method can be used for high-precision display such as image display. desirable.
[0003]
FIG. 13 is an example of a circuit showing one pixel of an active drive type organic EL display device.
In one pixel of the organic EL display device shown in FIG. 13, a selection transistor 3 (FET type) having a gate electrode connected to a gate line (selection line 1) and a drain electrode connected to a drain line (data line 2). TFT), and a drive transistor 5 (FET type TFT) having a gate electrode connected to the source electrode of the selection transistor 3, an EL power source connected to the drain electrode, and an anode of the EL element 4 connected to the source electrode. Is provided. Each pixel is provided with the EL element 4 having the anode connected to the drive transistor 5 and the cathode grounded as described above.
[0004]
In such an organic EL display device, a voltage is applied to the selection line 1, a row of pixels is selected, and a voltage is applied to the data line 2 of the pixels to be emitted from the row of pixels. . Thus, in the pixel to be caused to emit light, a voltage is applied from the data line 2 to the drain electrode of the selection transistor 3 and a voltage is applied from the selection line 1 to the gate electrode of the selection transistor 3. A voltage is applied from the source electrode to the gate electrode of the driving transistor 5.
[0005]
Since the EL power supply is always connected to the drain electrode of the drive transistor 5, a voltage higher than the threshold value is applied to the gate electrode of the drive transistor 5 from the source electrode of the selection transistor 3. Current flows from the source electrode of the drive transistor 5 to the EL element 4, and the EL element 4 emits light. Further, there is an additional capacitor (not shown) between the selection transistor 3 and the driving transistor 5, and no voltage is applied from the selection line 1 and the data line 2, and the source electrode of the selection transistor 3 to the gate electrode of the driving transistor 5. Even after the application of the voltage to is finished, a voltage equal to or higher than the threshold value is applied to the gate electrode of the drive transistor 5 for a predetermined time by the additional capacitor, and a current flows through the EL element 4. Thus, after each pixel is scanned sequentially and the EL element 4 emits light, the light emission of the EL element 4 does not end immediately. The EL element 4 of each pixel can be made to emit light for one frame.
[0006]
[Problems to be solved by the invention]
By the way, when an organic EL element for each pixel is driven using an active element such as a TFT (thin film transistor), for example, a current is limited by the transistor, so that power loss occurs and power consumption increases. Become.
For example, in the circuit shown in FIG. 13 as described above, a large amount of power is consumed by the transistors as follows.
[0007]
For example, in the circuit as shown in FIG. 13, the driving condition for emitting the predetermined luminance of the EL element 4 is the voltage 7 [V] and the current i, and the driving transistor 5 has the characteristics as shown in FIG. Shall. For example, when the driving transistor 5 has the characteristics as shown in FIG. 14, in order to secure a desired drain current i for driving the EL element 4 and obtain constant current characteristics, The gate voltage Vg = 20 [V] is required, and the constant current region at this time is when the drain voltage Vd, which is a voltage between the source and the drain, is 10 [V] or more.
That is, a potential loss of at least 10 [V] is required between the drain and source of the TFT serving as the driving transistor 5.
[0008]
From the above, the loss power in the drive transistor 5 is about 10i because the current i flows and the potential loss is 10 [V] or more.
In addition, the EL element 4 consumes 7i of power.
Then, assuming that the selection transistor 3 only applies a voltage to the gate electrode of the drive transistor 5 and that almost no current flows, ignoring the power loss in the selection transistor 3, the total power consumption is 10i + 7i.
The ratio of the power loss of the drive transistor 5 in the total power consumption is 10i / 17i = 10/17, that is, 58.8%.
Therefore, even if the TFT driving is adopted to realize low power consumption, the power loss due to the driving transistor is large and a sufficient effect cannot be obtained as it is.
[0009]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a self-luminous display device capable of displaying an image with low power consumption by reducing power loss due to an active element.
[0010]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a self-luminous display device including an active element for each pixel, and the self-luminous display device in which the active element is driven by the active element. The self-luminous elements are connected to the organic EL layer, a first electrode connected to the organic EL layer under the organic EL layer, and the organic EL layer above the organic EL layer, respectively. A first electrode of a self-light-emitting element among the plurality of self-light-emitting elements is a portion that does not overlap the organic EL layer of the self-light-emitting element and is adjacent to the self-light-emitting element. By overlapping and connecting to the second electrode of the light emitting element The plurality of self-luminous elements are electrically connected to the active element in series.
[0011]
According to the above configuration, when the self-light-emitting element emits light when a current is passed, by providing a plurality of self-light-emitting elements in one pixel, the value of the current flowing through each self-light-emitting element can be reduced. The same luminance as when a high current is passed through one self-luminous element can be obtained. As a result, when a plurality of self-luminous elements are electrically connected to the active element in series, one spontaneous light-emitting element having the same luminance level as the combined luminance level of the plurality of spontaneous light-emitting elements is activated. Since the value of the current flowing through the active element can be made lower than when connected to the element, the power loss in the active element can be reduced. Therefore, with the above-described configuration, it is possible to reduce power consumption of the active element by reducing power loss in the active element.
[0012]
The self-light-emitting element is basically an organic EL element, but any other light-emitting element can be used as long as it can control light emission by controlling the current flowing through the active element. Also good.
The active element is, for example, a TFT, but the organic EL element emits light only while a current is flowing, and the active element basically receives a current only while a signal serving as data is input from the outside. For example, a mechanism in which a current flows through an EL element for only a short time after a data signal has been input, as in the case of using a selection transistor, a drive transistor, and an additional capacitor in the above-described conventional example. It is necessary to have.
Further, when an element such as a double gate memory thin film transistor (hereinafter referred to as DG memory TFT) having a memory property for storing an input data signal is used as an active element, 1 is determined based on the stored data. The EL element may be illuminated many times during the time corresponding to the frame, so that substantially continuous display for one frame may be performed.
[0013]
The self-luminous display device according to claim 2 of the present invention is the self-luminous display device according to claim 1, characterized in that the cathode of the self-luminous element is connected to the active element.
According to the above configuration, the cathode of the self light emitting element is connected to the active element, the anode of the self light emitting element is connected to the power source for the self light emitting element, for example, and one of the terminals of the active element is grounded. Will be.
In this case, since the potential of the signal for turning on / off the active element is directly determined with respect to the ground level, there is an advantage of excellent controllability and response speed.
For example, when the active element connected to the light emitting element is a transistor (driving transistor), the cathode of the light emitting element is connected to the source (or drain) of the transistor, for example, and the drain (or source) is grounded. In this case, since the gate potential of the transistor is directly determined with respect to the ground level, there is an advantage of excellent controllability and response speed.
[0014]
The self-luminous display device according to claim 3 of the present invention is the self-luminous display device according to claim 1 or 2, characterized in that the active element is a transistor having a memory property.
According to the above configuration, by using a transistor having a memory property, for example, in a transistor having a memory property in which a data signal indicating whether or not the self-light-emitting element is caused to emit light is written, While data is sequentially output to the element, the light emitting element connected to the active element storing data indicating light emission can be caused to emit light many times.
[0015]
That is, when two transistors and an additional capacitor are used, the self-light-emitting element of each pixel that should emit light emits light for a time corresponding to approximately one frame, thereby continuously displaying images. However, in the case where the above-described transistor having the memory property is used, when data is input to each pixel, the self-emission of the pixel to emit light is based on the already input data. The light emitting element emits a large number of times during one frame, and by emitting a large number of times in a short time, it is possible to make it appear that the pixels to be emitted emit light continuously. By this, it is possible to make it appear that images are continuously displayed.
In this way, each pixel can control its own light emitting element by one active element, so that the self-luminous display can be achieved as compared with the conventional case where two transistors are used in each pixel. The configuration of the apparatus can be simplified.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Below, the self-luminous display apparatus of the 1st example of embodiment of this invention is demonstrated with reference to drawings.
FIG. 1 is a circuit diagram for explaining the configuration of one pixel of the self-luminous display device of the first example, and FIG. 2 shows a planar structure excluding the cathode and capacitor electrode 10a of the EL element of the one pixel. FIG. 3 shows the planar structure of one pixel, FIG. 4 is a graph showing the difference in potential loss in the drive transistor between the conventional example and the first example, and FIG. 5 shows the first example and the first example. It is a graph which shows the difference of the current characteristic of the EL element with an example.
[0017]
The self-luminous display device of the first example is an application of the present invention to an organic EL display device, and is arranged in a state where a large number of pixels as shown in FIGS. Thus, the display portion of the display device is configured. Images can be displayed by connecting drivers, power supplies, etc., to output signals to the active elements of each pixel in the display area of the display device, enabling single color light emission display and multicolor light emission color display. An image display device.
[0018]
As shown in FIG. 1, in one pixel of the self-luminous display device of the first example, a selection transistor 3 having a gate electrode connected to a selection line 1 and a drain electrode connected to a data line 2 is And a drive transistor 5 having a gate electrode connected to the source electrode of the selection transistor 3 and an EL power source connected to the drain electrode. An additional capacitor 10 is interposed between the source electrode of the selection transistor 3 and the gate electrode of the drive transistor 5.
[0019]
In the first example, the first EL element 11, the second EL element 12, and the third EL element 13 are connected in series to the source electrode of the drive transistor 5.
The structure of one pixel will be described in more detail with reference to the planar structure of one pixel in FIG. 2 and FIG. 3. For example, the selection line 1 is arranged so as to extend to the left and right for each row next to the pixel. The data line 2 extends in the front-rear direction for each vertical column of pixels. Further, an EL power supply line 14 connected to an EL power supply is extended in the longitudinal direction for each vertical column of pixels, and a grounded GND line 15 is extended in the horizontal direction for each horizontal row of pixels. Are arranged.
[0020]
As described above, the drain electrode of the selection transistor 3 is connected to the data line 2, and the gate electrode of the selection transistor 3 is connected to the selection line 1. The source electrode of the selection transistor 3 is connected to the drive transistor 5 via the connection line 16.
Further, as described above, the drive transistor 5 has its gate electrode connected to the source electrode of the selection transistor 3 via the connection line 16 and its drain electrode connected to the EL power supply line 14.
The anode 11a of the first EL element 11 is connected to the source electrode of the drive transistor 5, the anode 12a of the second EL element 12 is connected to the cathode 11b of the first EL element 11, and the anode of the third EL element 13 13 a is connected to the cathode 12 b of the second EL element 12, and the cathode 13 b of the third EL element 13 is connected to the GND line 15.
[0021]
Each of the above members is provided on a glass substrate (not shown), and on the glass substrate, a portion excluding the light emitting portions 11c, 12c, and 13c of the first to third EL elements 11, 12, and 13, for example, A black mask 21 is formed as an antireflection film made of chromium oxide or the like. The black mask 21 has openings at portions corresponding to the light emitting portions 11c, 12c, and 13c of the EL elements.
[0022]
An interlayer insulating film is basically formed between the anodes 11a, 12a, 13a of the first to third EL elements 11, 12, 13 and the cathodes 11b, 12b, 13b. Are provided with openings in the light emitting portions 11c, 12c, and 13c of the first to third EL elements 11, 12, and 13, and the anode 12a of the second EL element 12 and the cathode 11b of the first EL element 11. Are connected to the anode 13a of the third EL element 13 and the cathode 12b of the second EL element 12 to form an opening as a contact hole.
[0023]
Further, the interlayer insulating film overlaps with the peripheral portions of the light emitting portions 11c, 12c, 13c of the first to third EL elements 11, 12, 13, and surrounds the light emitting portions 11c, 12c, 13c. The range of the light emitting region that emits light by actually contributing to the display of the light emitting portions 11c, 12c, and 13c is regulated by the insulating film.
The selection transistor 3 and the drive transistor 5 are well-known FET type TFTs.
[0024]
The first to third EL elements 11, 12, and 13 have well-known organic EL layers. For example, transparent anodes 11a, 12a, and 13a made of ITO, and elements such as metals having a low work function. Cathodes 11b, 12b, and 13b, and light emitting portions 11c, 12c, and 13c sandwiched between the cathodes 11b, 12b, and 13b, respectively. , A light emitting layer, an electron transport layer, and the like.
[0025]
In addition, the light emitting portions 11c, 12c, and 13c (light emitting regions) of the first to third EL elements 11, 12, and 13 of each pixel basically have one EL element per pixel in a conventional EL display device. It is assumed that the conventional EL display device and the self-luminous display device of the first example are of substantially the same standard so that the same luminance as the luminance in the light emitting portion (light emitting region) of the EL element when provided is provided. In this case, the area of the light emitting portion of the EL element provided in one pixel per one pixel and the three light emitting portions 11c, 12c, 13c of the first to third EL elements 11, 12, 13 of the first example are The combined area is approximately the same. That is, the light emitting portions 11c, 12c, and 13c of the first to third EL elements are in a state where one light emitting portion having a luminance necessary for one pixel is divided into three. Note that this is an example of the present invention, and the present invention basically requires that a plurality of EL elements are arranged in one pixel and each EL element is connected in series to an active element. It is good also as what raises the brightness | luminance of.
[0026]
In addition, the light emitting portions 11c, 12c, and 13c of the first to third EL elements 11, 12, and 13 are arranged so as to be spaced apart from each other in a vertical row, and in the upper and lower pixel columns, The light emitting portions 11c, 12c, and 13c are arranged at equal intervals from each other. In addition, the self-luminous display device performs color display here, and includes three types of pixels for displaying the three primary colors of RGB, and the pixels of the same color are arranged in one vertical row or one horizontal row. In addition, each vertical column or horizontal row is arranged so as to repeat each color of RGB.
Further, as described above, a black mask is arranged around each of the light emitting units 11c, 12c, and 13c, and black is expressed by the black mask (a black level is ensured).
[0027]
Further, an additional capacitor 10 is provided between the source electrode of the selection transistor 3 and the gate electrode of the drive transistor 5 as shown in FIG. The additional capacitor 10 includes a connection line 16 along the EL power supply line 14, a gate insulating film provided thereon, and a capacitor electrode 10a provided on the gate insulating film. The capacitor electrode 10a is connected to the lead line portion 15a of the GND line 15 through a contact hole provided in the gate insulating film. Note that the additional capacitor 10 is not limited to the above-described one, and has an electrostatic capacity in any form, and has a predetermined capacity even after the voltage of the selection line 1 or the data line 2 becomes less than the threshold value. Any voltage can be used as long as the voltage applied to the gate electrode of the driving transistor 5 can be held.
[0028]
As described above, the first to third EL elements 11, 12, 13 are provided in a state where one EL element in one pixel is divided into three, and these first to third EL elements 11, 12, 13 are provided. Are connected to the drive transistor 5 in series, the following effects can be obtained.
First, when the first to third EL elements 11, 12, 13 of the first example have a configuration in which one EL element of the EL display device of the conventional example is divided into three as described above. In addition, the drive voltage of the first to third EL elements 11, 12, and 13 is 7 [V], which is the same as the conventional case described above. And when these 1st-3rd EL elements 11, 12, and 13 are connected in series, the drive voltage of a total of 21 [V] is needed.
[0029]
On the other hand, since the organic EL element emits light due to recombination of electrons and holes, generally the light emission luminance of the organic EL element is substantially proportional to the flowing current. Here, the current required to drive the first to third EL elements 11, 12, and 13 is i when the current required for the EL element of the conventional example to emit light with a predetermined luminance is assumed for each element. In addition, i / 3 of the third is good. As described above, this is because the area of the conventional EL element (light emitting part) and the area of the first to third EL elements 11, 12, 13 (light emitting parts 11c, 12c, 13c) of the first example are combined. The areas of the first to third EL elements 11, 12, 13 (light emitting parts 11c, 12c, 13c) of the first example with respect to the area of the conventional EL element (light emitting part) are set to 1/3. This is because the current flowing per unit area of each light emitting region of the first to third EL elements 11, 12, 13 is equal to that of the conventional one.
[0030]
Further, when the current-voltage characteristics of the drive transistor 5 are set as shown in FIG. 4, conventionally, a current i for flowing from the drive transistor 5 to one EL element is secured to obtain a constant current characteristic. Requires a gate voltage of Vg = 20 [V], and the constant current region at this time has a Vd of 10 [V] or more, and the drive transistor 5 requires a potential loss of at least 10 [V]. Met. On the other hand, in the first example, the gate voltage is Vg = 11 in order to obtain the constant current characteristic by securing the current i / 3 for flowing from the driving transistor 5 to the three EL elements 11, 12, and 13. .5 [V] is required, and in the constant current region at this time, Vd is 5 [V] or more, and the drive transistor 5 requires a potential loss of 5 [V] at least.
That is, in the first example, the potential loss of 10 [V] in the driving transistor 5 can be reduced to 5 [V].
[0031]
Accordingly, the power loss in the driving transistor 5 is (5/3) i = 1.67i, which can be reduced to about 1/6 compared to the conventional 10i.
Further, the ratio of the loss power of the drive transistor 5 in the total power consumption is as follows.
Since only a voltage is applied to the gate electrode of the drive transistor 5 by the selection transistor 3 and a current does not flow as much as other elements, if the power loss in the selection transistor 3 is ignored, the total power consumption in one pixel of the EL element Is the sum of the power consumption of the three EL elements 11, 12 and 13 and the power loss of the drive transistor 5.
[0032]
Therefore, the ratio of the loss power of the drive transistor 5 in the total power consumption is expressed by the loss power (5/3) i in the drive transistor 5, the loss power (5/3) i in the drive transistor, and the three EL elements 11, 12, 13 divided by the sum of power consumption 7 [V] × (i / 3) [A] × 3, that is, ((5 × (i / 3)) / ((5 + 21) / (i / 3) ) = About 19%.
As described above, the three first to third EL elements 11, 12, and 13 of each pixel of the self-luminous display device emit light with the same luminance as that of the conventional EL element provided for only one pixel. In this case, the power loss in the driving transistor 5 can be greatly reduced, and the power consumption in the self-luminous display device can be reduced. In addition, an increase in power consumption can be prevented even when the luminance of each pixel is increased as compared with the conventional case.
[0033]
Further, in the self-luminous display device of the first example, black is expressed (a black level is ensured) by the black mask. Therefore, in order to express black, the self-luminous element of the self-luminous display device is used. Unlike the case where a filter (including a polarizing filter or the like) that absorbs light is disposed in front, a part of the light of the light emitting element is not absorbed by the filter. Since it can be used as display light without being absorbed, the power consumption required to obtain a desired luminance can be reduced as compared with the case where a filter is used.
[0034]
Further, when the black mask is used, if the pixel pitch is long enough and the area ratio of the light emitting region (EL element portion) that emits light excluding the black mask in the area of the entire pixel is small, The width of the black mask between adjacent light emitting areas becomes wider, and this width becomes recognizable by the human eye. For example, when white is displayed by emitting light of each color light emitting part, black and white stripes There is a possibility that the pattern can be seen.
[0035]
However, as described above, if a plurality of EL elements serving as light emitting portions in one pixel are arranged apart from each other, a plurality of light emitting regions are arranged apart from each other in the black mask. The width of the black mask becomes narrow, and it becomes possible to make the width unrecognizable to humans.
Accordingly, even when a black mask is used, it is possible to avoid the appearance of a striped pattern or a lattice pattern due to the black mask, and high-quality display with low power consumption can be achieved.
[0036]
Further, as described above, when three EL elements that are substantially the same as those obtained by dividing a conventional EL element provided only by one pixel into three parts are provided and connected in series, the static electricity in the EL element is reduced. The capacitance component Cel is greatly reduced as follows.
First, conventionally, when a single EL element is provided in a pixel, the capacitance of the EL element is C1, and the combined capacitance of the three EL elements in the first example is C3. The capacitance of one of the three EL elements is C2.
[0037]
The capacitance C2 per EL element is the same as that obtained by dividing the conventional EL element into three parts, that is, the area of the EL element is approximately 1/3 of that of the conventional EL element, so that C2 = C1 / 3. It becomes.
The combined capacitance C3 when the EL element of this first example is combined in three stages in series is:

Thus, the conventional capacitance becomes 1/9.
[0038]
Then, the accumulated charge Q3 in the EL section composed of three EL elements is obtained when the voltage applied to one EL element is V (same as the voltage applied to one conventional EL element as described above).

It becomes 1/3 of the conventional.
[0039]
In general, the effective current that contributes to the light emission of the EL element decreases due to the charging / discharging phenomenon due to the capacitance.
In particular, at the rise / fall, the reduction rate becomes extremely large, and as a result, the light emission response of the EL element is remarkably deteriorated.
In the first example, as described above, for example, the capacitance can be reduced to 1/9 compared to the conventional case, and the response characteristics of the EL element can be greatly improved.
[0040]
That is, when the capacitance is reduced in this way, in the conventional EL element shown in FIG. 5 (A), the current does not immediately reach a peak at the time of rising but rises gently, and the current immediately at the time of falling. In contrast, in the first example of the three-stage series EL element shown in FIG. 5 (B), the current immediately reaches a peak at the rise and falls. It can be in a state where the tail is hardly pulled even at times.
Therefore, the three-stage series EL element of the first example can realize high-speed response and accurate luminance control, and is useful for high-quality display.
[0041]
Next, a second example of the embodiment of the present invention will be described with reference to the drawings.
6 is a circuit diagram for explaining a configuration of one pixel of the self-luminous display device of the second example, and FIG. 7 shows a planar structure excluding the cathode of the EL element of the one pixel. Shows a planar structure of the one pixel, and FIG. 9 shows a partial cross-sectional structure of the one pixel.
[0042]
The self-luminous display device of the second example is obtained by joining the cathode of the EL element to the active element, whereas the self-luminous display device of the first example has connected the anode of the EL element to the active element. In other respects, the light emitting display device of the first example has substantially the same configuration.
In the self-luminous display device of the second example, the same components as those of the self-luminous display device of the first example are denoted by the same reference numerals, and a part of the description is omitted.
[0043]
As shown in FIG. 6, the self-luminous display device of the first example includes a selection transistor 3 and a driving transistor 5 as in the first example.
In the second example, the source electrode of the driving transistor 5 is grounded, the first EL element 11, the second EL element 12, and the third EL element 13 are connected in series to the drain electrode. One EL element 11, a second EL element 12, and a third EL element 13 are connected in series to an EL power source.
Further, the structure of one pixel will be described more specifically with reference to the planar structure of one pixel in FIGS. 7 and 8. For example, as in the first example, the selection line 1, the data line 2, and the EL A power supply line 14 and a GND line 15 are arranged. In the second example, the position of the EL power supply line 14 and the position of the GND line 15 are switched from those in the first example.
[0044]
As described above, the drain electrode 3g (shown in FIG. 9) of the selection transistor 3 is connected to the data line 2, and the gate electrode 3a (shown in FIG. 9) of the selection transistor 3 is connected to the selection line 1.
The source electrode 3 b (shown in FIG. 9) of the selection transistor 3 is connected to one end of the connection line 16 through a contact hole provided in the gate insulating film 23, and the other end of the connection line 16 is connected to the drive transistor 5. It is connected to the gate electrode 5a (shown in FIG. 9).
[0045]
Further, as described above, the drive transistor 5 has the connection line 16 connected to the gate electrode 5a and the GND line 15 connected to the drain electrode 5g (shown in FIG. 9). The cathode 11b of the first EL element 11 is connected to the source electrode 5b (shown in FIG. 9) of the drive transistor 5, the cathode 12b of the second EL element 12 is connected to the anode 11a of the first EL element 11, The cathode 13 b of the third EL element 13 is connected to the anode 12 a of the second EL element 12, and the anode 13 a of the third EL element 13 is connected to the EL power supply line 14. The additional capacitor 10 includes a connection line 16 along the GND line 15, a gate insulating film 23 provided thereon, and a capacitor electrode 10a provided on the gate insulating film 23 and connected to the lead line 14a via a contact hole. And is composed of.
[0046]
Further, as shown in the cross-sectional structure of FIG. 9, each pixel of the self-luminous display device is formed on the glass substrate 20, and the light emitting regions of the light emitting portions 11c, 12c, and 13c are formed on the glass substrate 20. A black mask 21 (for example, chromium oxide as an antireflection film) is formed in a portion excluding (only 11c is shown in FIG. 9). An insulating film 22 is formed on the black mask 21 layer. Then, gate electrodes 3 a and 5 a having an anodic oxide film on the surface are formed on portions of the insulating film 22 to be the selection transistor 3 and the drive transistor 5.
[0047]
A gate insulating film 23 (for example, SiN) is formed on the insulating film 22 on which the gate electrodes 3a and 5a are formed as described above so as to cover the gate electrodes 3a and 5a. Below the gate insulating film 23, a selection line 1 (not shown in FIG. 9) connected to the gate electrode 3a of the selection transistor 3, a source electrode 3b of the selection transistor 3, and a gate electrode 5a of the drive transistor 5 are provided. A connection line 16 (for example, an Al alloy serving as a gate wiring), an EL power supply line 14 and the like are formed. In FIG. 9, the connection line 16 and the gate electrode 5a are separated, but are connected as shown in FIG.
[0048]
Then, on the gate insulating film 23, i-Si layers 3c and 5c (intrinsic semiconductor layers) that are regions where channels of the selection transistor 3 and the drive transistor 5 are formed are formed, and blocking layers 3d and 5d are formed thereon. The drain regions 3e and 5e (n + Si) and the source regions 3f and 5f (n + Si) are formed on the left and right sides of the blocking layers 3d and 5d, respectively. Further, drain electrodes 3g and 5g (for example, Al alloy) are provided on the drain regions 3e and 5e, and source electrodes 3b and 5b are provided on the source regions 3f and 5f.
[0049]
Further, as described above, the drain electrode 3g of the selection transistor 3 is connected to the data line 2 (not shown in FIG. 9), and the source electrode 3b is connected to the connection line 16.
Further, as described above, the drain electrode 5 g of the drive transistor 5 is connected to the GND line 15 (not shown in FIG. 9), and the source electrode 5 b is connected to the cathode 11 b of the first EL element 11.
[0050]
On the gate insulating film 23, anodes 11a, 12a, 13a (for example, ITO, only one anode 11a is shown in FIG. 9) of the first to third EL elements 11, 12, 13 are formed. Has been. The anode 13a of the third EL element 13 is joined to the EL power supply line 14 as shown in FIG.
An overcoat layer 24 (for example, SiN) is formed on the selection transistor 3, the drive transistor 5, and the anodes 11a, 12a, and 13a formed on the gate insulating film 23. The overcode layer 24 protects the selection transistor 3 and the drive transistor 5, and serves as the interlayer insulating film between the anodes 11a, 12a, 13a and the cathodes 11b, 12b, 13b.
[0051]
The overcoat layer 24 includes a portion where the source electrode 5b of the driving transistor 5 and the cathode 11b of the first EL element 11 are joined, and an organic EL layer that becomes the light emitting portions 11c, 12c, and 13c. A portion joined to 12a, 13a (light emitting region, in FIG. 9, only a portion where the light emitting portion 11c is connected to one anode 11a is shown), and a portion where the cathodes 12b, 13b are joined to the anode 11a, 12a (FIG. 9 are not shown), and an opening to be a contact hole or the like is formed.
[0052]
Further, the peripheral edge portion of the opening of the overcoat layer 24 (interlayer insulating film) is formed in a tapered shape so as to become wider as the opening is directed upward.
Then, an organic EL layer to be the light emitting portions 11c, 12c, and 13c is formed in a portion wider than the opening portion in the opening portion of the overcoat layer 24 (interlayer insulating film) on the anodes 11a, 12a, and 13a. Yes.
Cathodes 11b, 12b, and 13b are formed on the light emitting portions 11c, 12c, and 13c, which are organic EL layers, over a wider range than the light emitting portions 11c, 12c, and 13c, respectively. The cathode 11b of the first EL element 11 is formed so as to reach the source electrode 5b of the driving transistor 5 and connected to the source electrode 5b, and the cathode 12b of the second EL element 12 is connected to the anode 11a of the first EL element 11. The cathode 13b of the third EL element 13 is formed so as to reach the anode 12a of the second EL element 12, and is joined to the anode 12a.
[0053]
Moreover, since the peripheral part of the opening part on anode 11a, 12a, 13a of overcoat layer 24 (interlayer insulation film) is taper as mentioned above, light emission part 11c, 12c formed on this peripheral part , 13c and the cathodes 11b, 12b, 13b reach the anodes 11a, 12a, 13a along the taper angle, and face the anodes 11a, 12a, 13a at the openings of the overcord layer 24. .
The taper angle of the peripheral edge of the opening, that is, the angle θ formed by the plane on which the anodes 11a, 12a, and 13a are formed and the inner surface of the peripheral edge of the opening of the overcoat layer 24 is 20 ° to 50 °. It is a degree.
[0054]
Accordingly, the light emitting portions 11c, 12c, and 13c and the cathodes 11b, 12b, and 13b formed after the overcoat layer 24 is formed reach the anodes 11a, 12a, and 13a at the angles of 20 degrees to 50 degrees, and the anodes The portions that face 11a, 12a, and 13a are parallel to the anodes 11a, 12a, and 13a.
A passivation layer 25 is formed on the cathodes 11b, 12b, 13b and the overcoat layer 24, and the passivation layer 25 protects the layers below it.
[0055]
According to the self-luminous display device of the second example having such a configuration, the same effects as the self-luminous display device of the first example can be obtained, and a plurality of first to second serially connected devices are connected in series. The cathode 11b of the first EL element on one end side of the third EL elements 11, 12, 13 is connected to the source electrode 5b of the drive transistor 5, whereby the anode 13a of the third EL element 13 on the other end side is Since the drain electrode 5g of the drive transistor 5 is connected to the GND line 15 and is grounded because it is connected to the EL power supply line 14, the gate potential of the drive transistor 5 is directly determined with respect to the GND level. It can be made excellent.
[0056]
In the first example, the cross-sectional structure is not shown. However, the cross-sectional structure of the self-luminous element of the first example is the same as that of the first EL element in the source electrode 5b of the drive transistor 5 in the cross-sectional structure of the second example. 11 cathode 11b was connected, whereas cathode 11b was not connected to source electrode 5b, except that anode 11a of first EL element 11 was connected to source electrode 5b. The cross-sectional structure is as follows. In addition, in the part which is not illustrated in FIG. 9, there are different parts between the first example and the second example as described above.
[0057]
Next, a self-luminous display device of a third example of an embodiment of the present invention will be described with reference to the drawings.
FIG. 10 is a circuit diagram for explaining a configuration of one pixel of the self-luminous display device of the third example, and FIGS. 11 and 11 are a plurality of pixels for explaining a driving method of the self-luminous display device of the third example. FIG.
[0058]
The self-luminous display device of the third example uses one DG memory TFT 35 instead of the selection transistor 3, the drive transistor 5, and the additional capacitor 10 of the self-luminous display device of the first example. This point has substantially the same configuration as the self-luminous display device of the first example.
Further, in the self-luminous display device of the third example, the same components as those of the self-luminous display device of the first example are denoted by the same reference numerals, and in the self-luminous display device of the third example, the same as the first example. A part of the description of the configuration is omitted.
[0059]
As shown in FIG. 10, in the self-luminous display device of the third example, the first gate electrode 31 is connected to the selection line 1 (Select), the second gate electrode 32 is connected to the data line 2 (Data), A DG memory TFT 35 having a drain electrode 33 connected to the EL power supply line 14 and a source electrode 34 connected to the first EL element 11 is provided. And the three 1st-3rd EL elements 11, 12, and 13 are connected to the source electrode 34 in series similarly to the 1st example except the drive transistor 5 and DG memory TFT35 differing.
That is, the anode 11a of the first EL element 11 is connected to the source electrode 34 as in the structure shown in FIG. 3 of the first example, and the anode 12a of the second EL element 12 is connected to the cathode 11b of the first EL element 11. The anode 13a of the third EL element 13 is connected to the cathode 12b of the second EL element 12, and the cathode 13b of the third EL element 13 is grounded, that is, connected to the GND line 15.
[0060]
The DG memory TFT 35 has two gates and has a memory property by trapping carriers.
In the DG memory TFT 35, for example, a channel region (ia-Si) that generates electrons and holes when visible light is incident is formed on the left and right sides of the channel region. A lower gate insulating film is provided between the source region and drain region (n + Si), the source electrode 34 and the drain electrode 33 to which the source region and drain region are connected, and the channel region closer to the substrate than the channel region. A transparent lower gate electrode (first gate electrode 31) and an upper gate electrode (on the upper side of the channel region, that is, on the opposite side of the substrate, between the channel region and an upper gate insulating film) A second gate electrode 32) is provided. The lower gate electrode and the upper and lower gate electrodes are upside down on the circuit diagram.
[0061]
The lower gate insulating film is made of SiN, and the surface layer portion (side contacting the channel region) has a stoichiometric ratio of Si and N of 3: 4, whereas the ratio of Si and N is stoichiometric. A Si-rich trap region having a ratio of about 1: 1 is formed.
The trap region can trap carriers (holes, electrons).
[0062]
Such an n-channel type DG memory TFT 35 has, for example, the gate voltage of the first gate electrode 31 in a state where the gate voltage of the second gate electrode 32 is set to 0 V and the voltage is applied between the source and the drain. The change in the drain current when it is raised and the change in the drain current when the gate voltage of the first gate electrode 31 is then lowered have different hysteresis characteristics. In such a DG memory TFT 35, the drain current may or may not flow even when the gate voltage of the first gate electrode 31 is the same, depending on the presence / absence of carriers trapped in the trap region and the polarity of the carriers. It is like that.
[0063]
For example, when the DG memory TFT 35 is an n-channel and electrons are accumulated in the trap region, holes are induced in the channel region by the electric field of the electrons accumulated in the trap region, and the gate voltage is applied to the first gate electrode 31. Even if this gate voltage is slightly higher than the threshold voltage at which the channel can be formed, the drain current can flow in the channel region by canceling out the electric field of electrons accumulated in the trap region. A continuous channel is not formed, and no drain current flows.
[0064]
On the other hand, when holes are accumulated in the trap region, electrons are induced in the channel region by the electric field of the holes accumulated in the trap region, and this gate is applied when a gate voltage is applied to the first gate electrode 31. Even if the voltage is slightly lower than the threshold voltage at which channel formation is possible, a continuous channel capable of allowing a drain current to flow in the channel region is formed by the interaction with holes accumulated in the trap region, and the drain Current will flow.
Therefore, even if a gate voltage of the same level is applied to the first gate electrode 31 depending on the presence and polarity of accumulated carriers in the trap region, the drain current flows and the EL element emits light, and the drain current does not flow. In some cases, the EL element does not emit light.
[0065]
Also, the carrier accumulation method in the trap region is, for example, when the first gate electrode is set to 0 V with a potential difference of +10 V between the source and drain, and a positive gate voltage is applied to the second gate electrode, the n channel The electrons move from the n + layer forming the source region and the drain region to the carrier region, and are trapped in the trap region. In this case, electrons are accumulated in a relatively short time regardless of the incidence of visible light.
In addition, when the carrier region is irradiated with light in this state and a negative gate voltage is applied to the second gate electrode, a hole-electron pair is generated by the light irradiation in the carrier region, and this hole-electron is generated. The pair of electrons move to the source region and drain electrode made of the n + layer, holes are taken into the trap region and replaced with the above electrons, and holes are accumulated.
In addition, when electrons are accumulated in the trap region, the carrier region may be irradiated with light.
[0066]
Next, with reference to FIGS. 10 and 11, a method for driving the EL element in the self-luminous display device will be described.
In driving the EL element, data indicating light emission or non-light emission of the EL element is written into the DG memory TFT 35 of each pixel selected for one row in the horizontal (row) direction, that is, the trap region is stored in the DG memory TFT 35. A writing process for accumulating holes or electrons in the pixel and a display process for performing display based on light emission and non-light emission data stored in the DG memory TFT 35 in all pixels are repeatedly performed.
In addition, every time the writing process is performed, the row in which data is written is shifted by one row, and finally data is written into the DG memory TFT 35 of the pixels in all rows. In this way, data for one frame is written and displayed.
[0067]
In the data writing step, a voltage of +35 V is applied to the selection line 1 (here, the selection line 1 of the address n) wired along the selected horizontal row of pixels, and along another matrix. For the wired selection line 1 (here, a selection line other than address n such as address n + 1), the voltage is 0V.
An address voltage is applied to the first gate electrode of the DG memory TFT 35 connected to the selection line 1 of the horizontal line of pixels by applying an address voltage to the selection line 1 corresponding to the selected horizontal line of pixels. The
[0068]
Further, the address voltage applied to the selected selection line 1 is a high voltage (for example, a drain current can flow even if carriers (electrons here) that inhibit channel formation are accumulated in the trap region. Here, + 35V).
In addition, it is assumed that a voltage (here, for example, +10 V) is constantly applied to the EL power supply line 14 to which the drain electrode 33 of the DG memory TFT 35 of each pixel is connected.
As a result, a voltage capable of allowing a drain current to flow is applied to the first gate electrode 31 connected to the selection line 1, so the first to third EL elements 11 connected to the source electrode 34 of the DG memory TFT 35. , 12 and 13, current flows through the first to third EL elements 11, 12 and 13 in the selected horizontal row of pixels.
[0069]
Then, when the first to third EL elements 11, 12, 13 emit address light, the channel region of the DG memory TFT 35 is irradiated with light, and hole-electron pairs are generated in the channel region as described above. Become.
Here, a voltage is applied to the data line 2 wired for each vertical column of each pixel based on the light emission / non-light emission data of each pixel in the horizontal row. That is, when one pixel (for example, the mth pixel) in one horizontal row connected to the selection line 1 whose address is n is not maintained to emit light, a positive voltage is applied to the data line 2 to which the pixel is connected. (Here, for example, + 20V) is applied.
[0070]
On the other hand, when one pixel (for example, the m + 1th pixel) in one horizontal row of pixels connected to the selection line 1 whose address is n is maintained to emit light, the data line to which that pixel is connected. 2 is applied with a negative voltage (in this case, for example, −20 V). That is, in each pixel in one horizontal row, a positive voltage or a negative voltage is applied to the data line 2 to which each pixel is connected based on data indicating whether or not that pixel is caused to emit light.
[0071]
The data line 2 is connected to the second gate electrode 32 of the DG memory TFT 35. As described above, the first to third EL elements 11, 12, and 13 emit light, and light is transmitted to the channel region of the DG memory TFT 35. When a voltage is applied to the second gate electrode 32 in a state where a hole-electron pair is generated by irradiation of electrons, electrons accumulate in the trap region of the DG memory TFT 35 when the voltage is positive, When the voltage is negative, holes are accumulated in the trap region of the DG memory TFT 35.
[0072]
Then, in each pixel of one row of pixels connected to one selection line 1 selected as described above, the writing process is completed when electrons or holes are accumulated in the trap region of the DG memory TFT 35. It becomes a display process.
In the display process, a drain current flows through all the selection lines 1 depending on a voltage lower than the above threshold voltage, that is, the presence or absence of carriers trapped in the trap region of the DG memory TFT 35 and the polarity of the carriers. A voltage (in this case, for example, +15 V) that does not flow is applied.
[0073]
As described above, a voltage of + 10V is constantly applied to the EL power supply line 14, and at this time, the voltage of each data line 2 becomes 0V.
Then, the pixels in the selected horizontal row are in a state of emitting light or not emitting light based on the polarity of carriers accumulated in the trap region of the DG memory TFT 35 of those pixels.
[0074]
For example, as described above, in the pixel where the address of the selection line 1 where electrons are accumulated in the trap region is n and the data line 2 is the mth pixel, electrons are accumulated in the trap region of the DG memory TFT 35. Even when a low voltage is applied from the selection line 1 to the first gate electrode 31 as described above, a continuous n-channel is not formed in the channel region due to the influence of the electric field of electrons accumulated in the trap region, and the drain current does not flow. The first to third EL elements 11, 12, and 13 are in a non-light emitting state.
[0075]
On the other hand, as described above, since the address of the selection line 1 in which holes are accumulated in the trap region is n and the data line 2 is the (m + 1) th pixel, holes are accumulated in the trap region of the DG memory TFT 35. When a low voltage is applied from the selection line 1 to the first gate electrode 31 as described above, a continuous channel is formed in the channel region due to the interaction with the electric field of the holes accumulated in the trap region, The drain current flows, and the first to third EL elements 11, 12, and 13 maintain light emission.
[0076]
Further, in the above writing process, in the pixels in other rows other than the horizontal row of pixels in which the data is written, each column of pixels is in a light emitting state or a non-light emitting state based on the last written data. . For example, in each horizontal row of pixels connected to the selection line 1 whose address is n + 1, light is emitted or not emitted based on the data written in the previous frame (charges to be trapped are holes or electrons). .
Further, in each horizontal row of pixels connected to the selection line 1 whose address is n−1, the light emission state or the non-light emission state is set based on the written data in the writing step before the above writing step. Become.
[0077]
Then, when the writing process and the display process as described above are repeated and the horizontal row of pixels to be written in each writing process is shifted by one row, the number of horizontal rows of pixels in the display for one frame. Only display is done. In other words, display will be performed in a blinking state, but if the blinking speed exceeds a certain speed, blinking can be recognized by human eyes, and images are continuously displayed. Will look like. In addition, every time a writing process is performed, all the pixels in one horizontal row shine. However, if the pixels in one horizontal row are extremely short in addressing with high duty driving, they cannot be recognized by human eyes. The display does not greatly affect the display.
[0078]
Therefore, continuous display is possible even when the DG memory TFT 35 is used as an active element as described above.
And, in the self-luminous display device of the third example, its driving operation is slightly different as described above compared with the self-luminous display device of the first example, but the same effect as in the case of the first example, That is, it is possible to achieve effects such as reduction in total power consumption due to reduction in power loss in the active element and realization of high-speed response and accurate brightness control based on a decrease in capacitance in the EL element.
[0079]
Further, according to the self-luminous display device of the third example, it is not necessary to use two selection transistors 3 and drive transistors 5 for each pixel as active elements as in the conventional case, and one DG memory TFT 35 is provided. Since it may be used, the structure of the self-luminous display device can be simplified and the area of the light-emitting region can be increased. That is, the number of active elements can be halved, and the yield can be improved when manufacturing the self-luminous display device.
[0080]
In the FET type transistor, the drain and the source are determined depending on the direction of current flow and the type of carrier (channel) (hole or electron). Therefore, in the above description, the drain and the source may be interchanged. good.
In addition, the number of EL elements per pixel is not limited to three, and may be two or four or more as long as there are a plurality of EL elements. In terms of reduction in electric capacity, it is better that the number of EL elements per pixel is larger, and considering the ease of the manufacturing process, it is preferable that the number of EL elements per pixel is not so large.
[0081]
【The invention's effect】
According to the self-luminous display device of the first aspect of the present invention, the plurality of self-luminous elements are electrically connected in series to the active element, whereby the luminance level obtained by combining the plurality of spontaneous light-emitting elements. Since the value of the current flowing through the active element can be lowered compared to the case where one spontaneous light emitting element having the same luminance level as that of the active element is connected to the active element, the power loss in the active element can be reduced. Therefore, with the above-described configuration, it is possible to reduce power consumption of the active element by reducing power loss in the active element.
[0082]
According to the self-luminous display device of the second aspect of the present invention, the cathode of the self-luminous element is connected to the power source for the self-luminous element, for example, by connecting the cathode of the self-luminous element to the active element. At the same time, one of the terminals of the active element is grounded.
In this case, since the potential of the signal for turning on / off the active element is directly determined with respect to the ground level, there is an advantage of excellent controllability and response speed.
[0083]
According to the self-luminous display device of the present invention, the self-luminous element can be controlled by one active element in each pixel, so that two transistors are used in each pixel as in the prior art. The configuration of the self-luminous display device can be simplified as compared with the case where the light emitting display device is used.
[Brief description of the drawings]
FIG. 1 is a circuit diagram for explaining a configuration of one pixel of a self-luminous display device of a first example of an embodiment of the present invention.
FIG. 2 is a drawing for explaining a planar structure of one pixel of the self-luminous display device of the first example.
FIG. 3 is a drawing for explaining a planar structure of one pixel of the self-luminous display device of the first example.
FIG. 4 is a graph for explaining a difference between a loss potential in a driving transistor of a self-luminous display device of a first example and a loss potential in a driving transistor of an EL display device of a conventional example.
FIG. 5 is a graph for explaining a difference between current characteristics of an EL element of the self-luminous display device of the first example and current characteristics of an EL element of the EL display device of the conventional example.
FIG. 6 is a circuit diagram for explaining a configuration of one pixel of the self-luminous display device of the second example of the embodiment of the present invention.
FIG. 7 is a view for explaining a planar structure of one pixel of a self-luminous display device of a second example.
FIG. 8 is a drawing for explaining a planar structure of one pixel of a self-luminous display device of a second example.
FIG. 9 is a drawing for explaining a cross-sectional structure of one pixel of a self-luminous display device of a second example.
FIG. 10 is a circuit diagram for explaining a configuration of one pixel of the self-luminous display device of the third example of the embodiment of the present invention.
FIG. 11 is a circuit diagram for explaining a driving method in the self-luminous display device of the third example.
FIG. 12 is a circuit diagram for explaining a driving method in the self-luminous display device of the third example.
FIG. 13 is a circuit diagram for explaining the configuration of one pixel of a conventional EL display device.
FIG. 14 is a graph for explaining a loss potential in a driving transistor of an EL display device of a conventional example.
[Explanation of symbols]
3 Select transistor (active element)
5 Drive transistor (active element)
11 First EL element (self-luminous element)
11a Anode
11b Cathode
12 Second EL element (self-luminous element)
12a anode
12b Cathode
13 Third EL element (Self-emitting element)
13a anode
13b Cathode
35 DG memory TFT (active element, transistor having memory characteristics)

Claims (3)

In a self-luminous display device having an active element for each pixel and driving the self-luminous element by the active element, a plurality of self-luminous elements are provided in one pixel, and each of the self-luminous elements is an organic EL layer. A first electrode connected to the organic EL layer under the organic EL layer, and a second electrode connected to the organic EL layer on the organic EL layer, and a plurality of self-light-emitting elements A first electrode of a self-light-emitting element among the elements is a portion that does not overlap with the organic EL layer of the self-light-emitting element, and is connected to the second electrode of the self-light-emitting element adjacent to the self-light-emitting element. Thus, the plurality of self-luminous elements are electrically connected in series to the active element.   2. The self light emitting display device according to claim 1, wherein a cathode of the self light emitting element is connected to the active element.   3. The self light emitting display device according to claim 1, wherein the active element is a transistor having a memory property.

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