JP3640017B2 - Lead-free solder bump and its formation method - Google Patents

Lead-free solder bump and its formation method Download PDF

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JP3640017B2
JP3640017B2 JP2000221980A JP2000221980A JP3640017B2 JP 3640017 B2 JP3640017 B2 JP 3640017B2 JP 2000221980 A JP2000221980 A JP 2000221980A JP 2000221980 A JP2000221980 A JP 2000221980A JP 3640017 B2 JP3640017 B2 JP 3640017B2
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lead
solder bump
mask
free solder
precursor
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JP2002043348A (en
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隆生 石井
眞二 青山
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Nippon Telegraph and Telephone Corp
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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体デバイス等に使用される鉛フリーはんだバンプ及びその形成法に関する。
【０００２】
【従来の技術】
近年、環境汚染物質の削減やその代替物質への転換が呼ばれている中、電子機器の基板配線に大きな寄与をしてきたはんだの主成分である鉛の毒性がクローズアップされてきた。この発端は地下水を飲料水としているアメリカにおいて許容値を越える鉛が検出され、この原因が廃家電等のプリント基板が酸性雨にさらされることによって溶出したものと判断されたことによる。
【０００３】
本来鉛の使用が最も多いのが自動車用のバッテリであり７０％と圧倒的で、はんだは他の鉛台金と合わせても３％前後の割合でしかない。しかし、バッテリは回収可能であるが、家電製品のプリント基板に使用されているはんだは回収が不可能に近く、廃家電はゴミという形で廃棄され、前述のように一度溶出してしまえば環境に与える影響は大きい。このような背景から鉛を含まないはんだ（鉛フリーはんだ）採用にむけての検討が各国で精力的に行われている。
【０００４】
従来使われている鉛−スズ共晶はんだは融点、濡れ性、強度、価格等いずれにおいても優れた特性を有するが、これを凌駕する鉛フリーはんだを開発することは以下のような問題点があり非常に困難である。
【０００５】
鉛フリーはんだはリフロー温度を反映する融点の観点からベースとなる材料にはスズが用いられ、第二元素としてビスマス、銀、銅、亜鉛、インジウム等が添加されるのが一般的である。しかしインジウムを除いていずれの組み合わせにおいても共晶温度は鉛−スズはんだのそれよりも高く、さらに濡れ性、強度、酸化等の点でも問題が多い。
【０００６】
一方においてマルチメディア社会を支える、高速で広帯域な光通信用モジュールを構成する光デバイスや超高周波用電子デバイスの特性劣化を引き起こすことなく実装するためにはんだバンプとその形成技術は益々重要となってきている。特に携帶電話等の小型移動体通信手段の発展とともにデバイスの集積小型化が進みこのモジュール化に対応できる微小バンプとその形成法が必要とされている。
【０００７】
【発明が解決しようとする課題】
微小バンプを形成するためにははんだ材料を蒸着する手法が一般的である。しかし二元以上の金属からなるはんだ合金を蒸着しても通常は単体金属の蒸気圧が大きく異なるため、もとのはんだ合金と同じ組成の金属薄膜を得ることは非常に困難である。このため従来、鉛−スズ系微小はんだバンプを作製する場合には、所望の組成（例えばＳｎ７４％−Ｐｂ２６％）の薄膜を成膜するために２つの電子ビームを用いてスズと鉛の蒸気圧制御を独立に行なわねばならず、装置大型化と高度な作成技術が要求されるといった問題があった。
【０００８】
本発明はこのような点に鑑みてなされたものであり、スズと鉛以外の金属との組み合わせによる鉛フリーはんだバンプを提供することを目的とする。
また、本発明の他の目的は、スズと鉛以外の金属との組み合わせにおいて、通常の蒸着法によりスズの層膜と鉛以外の金属の層膜とによる多層膜の形成により目的の組成とし、低温アニールとリフローを行なって鉛フリーはんだバンプを形成する鉛フリーはんだバンプ形成法を提供することである。
【０００９】
【課題を解決するための手段】
上記の目的を達成するために本発明は、スズに対して鉛以外の相互拡散係数の大きい金属を選定しこの組み合わせの多層膜形成による蒸着法を採用することを特徴とする。
つまり、請求項１の発明は、基板上にパターニングしたマスクを形成し、その上から、Ｓｎ １−ｘ Ｍ ｘ （Ｍ：Ａｕ，Ｉｎのうち少なくとも一つ以上を含みかつ０＜ｘ≦０．５）の組成になるように設定した膜厚のＳｎおよびＭを交互に２回以上繰り替えして蒸着してＳｎおよびＭの多層膜を形成し、その後マスクを除去して前記多層膜からなるはんだバンプ前駆体を形成し、つぎにアニールを行ってバンプ前駆体の組成の均一化を行い、さらに、前駆体と同一の組成のＳｎとＭとの合金の共晶温度においてリフローさせることを特徴とする鉛フリーはんだバンプの形成法である。
請求項２の発明は、基板上にパターニングしたマスクを形成し、その上から、Ｓｎ １−ｘ Ｍ ｘ （Ｍ：Ａｕ，Ｉｎのうち少なくとも一つ以上を含みかつ０＜ｘ≦０．５）の組成になるように設定した膜厚のＳｎおよびＭを交互に６回繰り替えして蒸着してＳｎおよびＭの多層膜を形成し、その後マスクを除去して前記多層膜からなるはんだバンプ前駆体を形成し、つぎにアニールを行ってバンプ前駆体の組成の均一化を行い、さらに、前駆体と同一の組成のＳｎとＭとの合金の共晶温度においてリフローさせることを特徴とする鉛フリーはんだバンプの形成法である。
請求項３の発明は、請求項１または２に記載の鉛フリーはんだバンプの形成法において、前記はんだバンプ前駆体のアニールを該前駆体と同一の組成のＳｎとＭとの合金の共晶温度より低い温度で行うことを特徴とする。
請求項４の発明は、請求項１または２に記載の鉛フリーはんだバンプの形成法において、パターニングするマスクとして有機レジスト材を用い、リフトオフ法によりマスクを除去することを特徴とする。
請求項５の発明は、請求項１または２に記載の鉛フリーはんだバンプの形成法において、パターニングするマスクとして金属マスクを用いることを特徴とする。
【００１０】
【発明の実施の形態】
上記の課題を解決するために本発明の鉛フリーはんだバンプは、Ｓｎ１−ｘＭｘ（Ｍ：Ａｕ，Ｉｎのうち少なくとも一つ以上を含みかつ０＜ｘ≦０．５）なる組成を有する合金であることに特徴を有している。
【００１１】
また、本発明の鉛フリーはんだバンプの形成法は、基板上にパターニングしたマスクを形成し、その上から、Ｓｎ１−ｘＭｘ（Ｍ：Ａｕ，Ｉｎのうち少なくとも一つ以上を含みかつ０＜ｘ≦０．５）の組成になるように設定したＳｎおよびＭの膜厚を交互に蒸着して多層膜を形成し、その後マスクを除去して前記多層膜からなるはんだバンプ前駆体を形成し、つぎにアニールを行ってバンプ前駆体の組成の均一化を行い、さらに、前駆体の共晶温度においてリフローさせることに特徴を有している。
【００１２】
さらに、本発明の鉛フリーはんだバンプの形成法は、はんだバンプ前駆体のアニールを該前駆体の共晶温度より低い温度で行うことに特徴を有している。
【００１３】
また、本発明の鉛フリーはんだバンプの形成法は、パターニングするマスクとして有機レジスト材を用い、リフトオフ法によりマスクを除去することに特徴を有している。
【００１４】
さらに、本発明の鉛フリーはんだバンプの形成法は、パターニングするマスクとして金属マスクを用いることに特徴を有している。
【００１５】
【実施例】
以下に本発明の作用を本発明をなすに際して得た知見とともに説明する。
一般には合金膜の目的組成に合うように多層に膜を積層しても相互拡散係数が小さいために組成の均一化は生じない。しかし、もし相互拡散係数が大きな金属の組み合わせが見つかれば、蒸着法により多層膜を形成して目的の組成とし、適切な低温アニールを行なえば組成の均一化が起り所望の組成を有するはんだが形成できると考えた。
【００１６】
そこでスズをベースとして第二金属としてビスマス、銀、銅、亜鉛、インジウム、金のうち一つを選び合金とした場合の相互拡散について検討した。この中で金、インジウムの場合については相互拡散が大きく２００℃で合金化が起ることが報告されている[L.Buene,Thin Solid Films vol.47(1877)285,J.Bjontegaard et al.,Thin Solid Films voL.101(1983)253]。
【００１７】
図２はＡｕ−Ｓｎ系の相図（状態図）であり、縦軸は融点温度，横軸はＳｎ−Ａｕの割合を示している。図に示すように、Ｓｎ−Ａｕ系の共晶温度はＳｎ９５％−Ａｕ５％で２１７℃となっており、この組成になるように膜厚を選択し、比較的低温の約２００℃でアニールすれば所望の均一な合金が得られ、さらに温度を共晶温度まで上げればリフローすることが予想される。
【００１８】
このような検討結果のもとに本発明者らは、微小バンプはんだ形成に必要な合金膜の蒸着膜を得るために、幾多の実験を重ねる過程においてＳｎ−Ａｕ系もしくはＳｎ−Ｉｎ系においては所望の合金膜が形成できリフトオフ法によりはんだバンプ前駆体を形成し、約２２０℃以下でリフローして微小はんだバンプが形成することを見い出し本発明をなすに至った。
【００１９】
次に、本発明の実施の形態を図面に基づいて説明する。なお、実施の形態は一つの例示であって、本発明の技術的思想を逸脱しない範囲で、種々の変更あるいは改良を行い得ることはいうまでもない。
【００２０】
（実施例１）
図１は、本発明の一実施例における鉛フリーはんだバンプの形成法を説明する工程図である。
(a) 基板１上に適当な有機レジスト材を塗布してマスク２とし、
(b) マスク２を露光、現像等によりパターンマスク３に形成し、
(c) パターンマスク３上にＳｎ９５％−Ａｕ５％の組成になるように、ＳｎとＡｕの薄膜を電子ビーム蒸着法により作成した。Ｓｎ：９００ｎｍ→Ａｕ：２８ｎｍを６回繰り替えし約５．５μ膜厚の多層膜４にした。
(d)その後、有機溶剤を用いたリフトオフ法によってパターンマスク３を除去し、多層膜４からなる８０μｍφの微小なはんだバンプ前駆体５を形成した。
(e) つぎに、フラックス液（ソルボンドＲ５００３）を塗布し、さらに約２００℃、１０ｍｉｎのアニールにより組成の均一化を行った。さらに、２１８℃に温度を上げてリフローを行い微小な鉛フリーはんだバンプ６を形成した。
【００２１】
（実施例２）
(b) 基板１上に８０μｍφの穴をパターニングした金属のパターンマスク３を用いた。
(c) パターンマスク３上にＳｎ９５％−Ａｕ５％の組成になるように、ＳｎとＡｕの薄膜を電子ビーム蒸着法により作成した。Ｓｎ：９００ｎｍ→Ａｕ：２８ｎｍを６回繰り替えし約５．５μ膜厚の多層膜４にした。
(d)その後、有機溶剤を用いたリフトオフ法によってパターンマスク３を除去し、多層膜４からなる８０μｍφの微小なはんだバンプ前駆体５を形成した。
(e) つぎに、フラックス液（ソルボンドＲ５００３）を塗布し、さらに約２００℃、１０ｍｉｎのアニールにより組成の均一化を行った。さらに、２１８℃に温度を上げてリフローを行い微小な鉛フリーはんだバンプ６を形成した。
【００２２】
（実施例３）
(a) 基板１上に適当な有機レジスト材を塗布してマスク２とし、
(b) マスク２を露光、現像等によりパターンマスク３に形成し、
(c) パターンマスク３上にＳｎ９５％−Ｉｎ５％の組成になるように、ＳｎとＩｎの薄膜を電子ビーム蒸着法により作成した。Ｓｎ：９００ｎｍ→Ｉｎ：２９ｎｍを６回繰り替えし約５．５μ膜厚の多層膜４にした。
(d)その後、有機溶剤を用いたリフトオフ法によってパターンマスク３を除去し、多層膜４からなる８０μｍφの微小なはんだバンプ前駆体５を形成した。
(e) つぎに、フラックス液（ソルボンドＲ５００３）を塗布し、さらに約１９０℃、１０ｍｉｎのアニールにより組成の均一化を行った。さらに、２１０℃に温度を上げてリフローを行い微小な鉛フリーはんだバンプ６を形成した。
【００２３】
（実施例４）
(a) 基板１上に適当な有機レジスト材を塗布してマスク２とし、
(b) マスク２を露光、現像等によりパターンマスク３に形成し、
(c) パターンマスク３上にＳｎ９５％−Ａｕ３％−Ｉｎ２％の組成になるように、Ｓｎ，Ａｕ，Ｉｎの薄膜を電子ビーム蒸着法により作成した。Ｓｎ：９００ｎｍ→Ａｕ：１６ｎｍ→Ｉｎ：１３ｎｍを６回繰り替えし約５．５μ膜厚の多層膜４にした。
(d)その後、有機溶剤を用いたリフトオフ法によってパターンマスク３を除去し、多層膜４からなる８０μｍφの微小なはんだバンプ前駆体５を形成した。
(e) つぎに、フラックス液（ソルボンドＲ５００３）を塗布し、さらに約２００℃、１０ｍｉｎのアニールにより組成の均一化を行った。さらに、２１０℃に温度を上げてリフローを行い微小な鉛フリーはんだバンプ６を形成した。
なお、本実施例１〜４ではＳｎ９５％−Ａｕ５％，Ｓｎ９５％−Ｉｎ５％，Ｓｎ９５％−Ａｕ３％−Ｉｎ２％の組成の合金についてのみその実施例を示したが、Ｓｎ，Ａｕ，Ｉｎの膜厚をＳｎ１−ｘＭｘ（Ｍ：Ａｕ，Ｉｎのうち少なくとも一つ以上を含みかつ０＜ｘ≦０．５）なる組成を有する合金となるよう設定して積層膜を形成し、実施例１〜４の何れかの方法で鉛フリーはんだバンプ６を形成しても良い。
【００２４】
【発明の効果】
以上説明したように本発明では、Ｓｎ−Ａｕ系もしくはＳｎ−Ｉｎ系においては蒸着により多層膜形成により所望の合金膜が形成でき、リフトオフ法により微小はんだバンプ前駆体を形成し、約２２０℃以下でリフローし微小鉛フリーはんだバンプが形成することができる。２２０℃以下という比較的低温でリフローできることは、特に化合物系半導体デバイスのパッケージ化において特に大きな貢献をなすものである。また、適切な低温アニールを行なえば組成の均一化が起り所望の組成を有するはんだが形成できる。
【図面の簡単な説明】
【図１】（ａ）〜（ｅ）は、本発明の一実施例における鉛フリーはんだバンプの形成法を説明する工程図である。
【図２】本発明の基本思想を説明するためのＡｕ−Ｓｎ系の相図である。
【符号の説明】
１ 基板
２ マスク
３ パターンマスク
４ 多層膜
５ バンプ前駆体
６ 鉛フリーはんだバンプ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a lead-free solder bump used for a semiconductor device or the like and a method for forming the same.
[0002]
[Prior art]
In recent years, the toxicity of lead, which is the main component of solder, which has greatly contributed to the substrate wiring of electronic devices, has been highlighted while reducing environmental pollutants and switching to alternatives. The origin of this was due to the fact that lead exceeding the allowable value was detected in the United States where drinking water was used as groundwater, and that the cause was judged to have been eluted by exposing printed circuit boards such as waste home appliances to acid rain.
[0003]
Originally, the most common use of lead is the battery for automobiles, which is overwhelming at 70%, and the solder is only about 3% when combined with other lead base metal. However, the battery can be recovered, but the solder used on the printed circuit board of home appliances is almost impossible to recover, and the discarded home appliances are discarded in the form of garbage and once eluted as described above, the environment The impact on is great. Against this background, various countries are energetically studying how to use lead-free solder (lead-free solder).
[0004]
Conventionally used lead-tin eutectic solder has excellent properties in terms of melting point, wettability, strength, price, etc., but developing lead-free solder that surpasses this has the following problems: It is very difficult.
[0005]
In the lead-free solder, tin is used as a base material from the viewpoint of the melting point reflecting the reflow temperature, and bismuth, silver, copper, zinc, indium and the like are generally added as the second element. However, in any combination except for indium, the eutectic temperature is higher than that of lead-tin solder, and there are many problems in terms of wettability, strength, oxidation, and the like.
[0006]
On the other hand, solder bumps and their formation technology are becoming more and more important for mounting without causing deterioration of the characteristics of optical devices and ultra-high frequency electronic devices that constitute high-speed and broadband optical communication modules that support the multimedia society. ing. In particular, along with the development of small mobile communication means such as mobile phones, the integration and miniaturization of devices have progressed, and micro bumps that can cope with this modularization and the formation method thereof are required.
[0007]
[Problems to be solved by the invention]
In order to form micro bumps, a method of vapor-depositing a solder material is common. However, it is very difficult to obtain a metal thin film having the same composition as that of the original solder alloy because the vapor pressure of a single metal is usually greatly different even when a solder alloy composed of two or more metals is deposited. For this reason, conventionally, when producing a lead-tin micro solder bump, the vapor pressure of tin and lead using two electron beams to form a thin film having a desired composition (for example, Sn74% -Pb26%). There was a problem that the control had to be performed independently, and that the apparatus size was increased and advanced production technology was required.
[0008]
This invention is made | formed in view of such a point, and it aims at providing the lead-free solder bump by the combination of metals other than tin and lead.
Another object of the present invention is to achieve a target composition by forming a multilayer film with a layer film of tin and a layer film of metal other than lead by a normal vapor deposition method in a combination of metals other than tin and lead. To provide a lead-free solder bump forming method in which lead-free solder bumps are formed by performing low-temperature annealing and reflow.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is characterized in that a metal having a large mutual diffusion coefficient other than lead is selected with respect to tin and a vapor deposition method by forming a multilayer film of this combination is adopted.
That is, according to the first aspect of the present invention, a patterned mask is formed on a substrate, from which Sn 1-x M x (M: includes at least one of Au, In, and 0 <x ≦ 0. 5) Sn and M having a film thickness set so as to have the composition are alternately and repeatedly deposited to form a Sn and M multilayer film, and then the mask is removed and the solder composed of the multilayer film A bump precursor is formed, then annealed to make the composition of the bump precursor uniform, and further reflowed at the eutectic temperature of an alloy of Sn and M having the same composition as the precursor. This is a method for forming lead-free solder bumps.
According to a second aspect of the present invention, a patterned mask is formed on a substrate, from which Sn 1-x M x (M: includes at least one of Au and In, and 0 <x ≦ 0.5). Sn and M having a film thickness set so as to have the following composition are alternately deposited six times to form a multilayer film of Sn and M, and then the mask is removed to form a solder bump precursor comprising the multilayer film And then annealing to homogenize the composition of the bump precursor and reflow at the eutectic temperature of an alloy of Sn and M having the same composition as the precursor. This is a method of forming solder bumps.
According to a third aspect of the present invention, in the method for forming a lead-free solder bump according to the first or second aspect, the eutectic temperature of the alloy of Sn and M having the same composition as the precursor is annealed to the solder bump precursor. It is characterized by being performed at a lower temperature.
According to a fourth aspect of the present invention, in the method for forming a lead-free solder bump according to the first or second aspect, an organic resist material is used as a mask for patterning, and the mask is removed by a lift-off method.
According to a fifth aspect of the present invention, in the method for forming a lead-free solder bump according to the first or second aspect, a metal mask is used as a mask for patterning.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
In order to solve the above problems, the lead-free solder bump of the present invention has a composition of Sn 1-x M x (M: includes at least one of Au and In and 0 <x ≦ 0.5). It is characterized by being an alloy.
[0011]
Further, the lead-free solder bump forming method of the present invention forms a patterned mask on a substrate, and includes Sn 1-x M x (M: at least one of Au, In and 0). <X ≦ 0.5) The film thickness of Sn and M set so as to have the composition is alternately deposited to form a multilayer film, and then the mask is removed to form a solder bump precursor composed of the multilayer film. Next, annealing is performed to make the composition of the bump precursor uniform, and the reflow is performed at the eutectic temperature of the precursor.
[0012]
Furthermore, the lead-free solder bump forming method of the present invention is characterized in that the solder bump precursor is annealed at a temperature lower than the eutectic temperature of the precursor.
[0013]
The lead-free solder bump forming method of the present invention is characterized by using an organic resist material as a mask for patterning and removing the mask by a lift-off method.
[0014]
Further, the lead-free solder bump forming method of the present invention is characterized in that a metal mask is used as a mask for patterning.
[0015]
【Example】
The operation of the present invention will be described below together with the knowledge obtained in making the present invention.
In general, even if films are laminated in multiple layers so as to match the target composition of the alloy film, the mutual diffusion coefficient is small, so that the composition is not uniformized. However, if a combination of metals with a large interdiffusion coefficient is found, a multilayer film is formed by vapor deposition to achieve the desired composition, and if appropriate low temperature annealing is performed, the composition becomes uniform and a solder having a desired composition is formed. I thought it was possible.
[0016]
Therefore, interdiffusion in the case of selecting one of bismuth, silver, copper, zinc, indium and gold as the second metal based on tin and examining it as an alloy was studied. Among them, in the case of gold and indium, it is reported that mutual diffusion is large and alloying occurs at 200 ° C. [L. Buene, Thin Solid Films vol. 47 (1877) 285, J. Bjontegaard et al. , Thin Solid Films voL. 101 (1983) 253].
[0017]
FIG. 2 is a phase diagram (state diagram) of the Au—Sn system, where the vertical axis indicates the melting point temperature and the horizontal axis indicates the ratio of Sn—Au. As shown in the figure, the eutectic temperature of Sn—Au system is 217 ° C. with Sn 95% -Au 5%, and the film thickness is selected so that this composition is obtained, and annealing is performed at a relatively low temperature of about 200 ° C. Thus, a desired uniform alloy can be obtained, and reflow is expected if the temperature is further raised to the eutectic temperature.
[0018]
Based on such examination results, the present inventors have obtained a deposition film of an alloy film necessary for forming a fine bump solder, and in the process of repeated experiments, in the Sn-Au system or the Sn-In system, The present inventors have found that a desired alloy film can be formed, a solder bump precursor is formed by a lift-off method, and reflow is performed at about 220 ° C. or less to form a fine solder bump, thereby achieving the present invention.
[0019]
Next, embodiments of the present invention will be described with reference to the drawings. The embodiment is merely an example, and it goes without saying that various changes or improvements can be made without departing from the technical idea of the present invention.
[0020]
Example 1
FIG. 1 is a process diagram illustrating a method for forming lead-free solder bumps in one embodiment of the present invention.
(a) An appropriate organic resist material is applied on the substrate 1 to form a mask 2;
(b) Form the mask 2 on the pattern mask 3 by exposure, development, etc.
(c) A thin film of Sn and Au was formed on the pattern mask 3 by an electron beam vapor deposition method so as to have a composition of Sn95% -Au5%. Sn: 900 nm → Au: 28 nm was repeated 6 times to obtain a multilayer film 4 having a thickness of about 5.5 μm.
(d) Thereafter, the pattern mask 3 was removed by a lift-off method using an organic solvent, and a fine solder bump precursor 5 having a thickness of 80 μm φ composed of the multilayer film 4 was formed.
(e) Next, a flux solution (Solbond R5003) was applied, and the composition was made uniform by annealing at about 200 ° C. for 10 minutes. Further, the temperature was raised to 218 ° C. and reflow was performed to form a fine lead-free solder bump 6.
[0021]
(Example 2)
(b) A metal pattern mask 3 in which holes of 80 μm diameter were patterned on the substrate 1 was used.
(c) A thin film of Sn and Au was formed on the pattern mask 3 by an electron beam vapor deposition method so as to have a composition of Sn95% -Au5%. Sn: 900 nm → Au: 28 nm was repeated 6 times to obtain a multilayer film 4 having a thickness of about 5.5 μm.
(d) Thereafter, the pattern mask 3 was removed by a lift-off method using an organic solvent, and a fine solder bump precursor 5 having a thickness of 80 μm φ composed of the multilayer film 4 was formed.
(e) Next, a flux solution (Solbond R5003) was applied, and the composition was made uniform by annealing at about 200 ° C. for 10 minutes. Further, the temperature was raised to 218 ° C. and reflow was performed to form a fine lead-free solder bump 6.
[0022]
Example 3
(a) An appropriate organic resist material is applied on the substrate 1 to form a mask 2;
(b) Form the mask 2 on the pattern mask 3 by exposure, development, etc.
(c) A thin film of Sn and In was formed on the pattern mask 3 by an electron beam evaporation method so as to have a composition of Sn95% -In5%. Sn: 900 nm → In: 29 nm was repeated 6 times to obtain a multilayer film 4 having a thickness of about 5.5 μm.
(d) Thereafter, the pattern mask 3 was removed by a lift-off method using an organic solvent, and a fine solder bump precursor 5 having a thickness of 80 μm φ composed of the multilayer film 4 was formed.
(e) Next, a flux solution (Solbond R5003) was applied, and the composition was made uniform by annealing at about 190 ° C. for 10 minutes. Further, the temperature was raised to 210 ° C. and reflowing was performed to form a fine lead-free solder bump 6.
[0023]
(Example 4)
(a) An appropriate organic resist material is applied on the substrate 1 to form a mask 2;
(b) Form the mask 2 on the pattern mask 3 by exposure, development, etc.
(c) A thin film of Sn, Au, In was formed on the pattern mask 3 by an electron beam evaporation method so as to have a composition of Sn95% -Au3% -In2%. Sn: 900 nm → Au: 16 nm → In: 13 nm was repeated six times to obtain a multilayer film 4 having a thickness of about 5.5 μm.
(d) Thereafter, the pattern mask 3 was removed by a lift-off method using an organic solvent, and a fine solder bump precursor 5 having a thickness of 80 μm φ composed of the multilayer film 4 was formed.
(e) Next, a flux solution (Solbond R5003) was applied, and the composition was made uniform by annealing at about 200 ° C. for 10 minutes. Further, the temperature was raised to 210 ° C. and reflowing was performed to form a fine lead-free solder bump 6.
In the first to fourth embodiments, only the alloy having the composition of Sn95% -Au5%, Sn95% -In5%, Sn95% -Au3% -In2% was shown, but the film of Sn, Au, In was used. A laminated film is formed by setting the thickness to be an alloy having a composition of Sn 1-x M x (M: including at least one of Au, In and 0 <x ≦ 0.5). The lead-free solder bump 6 may be formed by any one of methods 1 to 4.
[0024]
【The invention's effect】
As described above, in the present invention, in the Sn-Au system or Sn-In system, a desired alloy film can be formed by forming a multilayer film by vapor deposition, and a fine solder bump precursor is formed by a lift-off method, and is about 220 ° C. or less. Can be reflowed to form a fine lead-free solder bump. The ability to reflow at a relatively low temperature of 220 ° C. or less makes a particularly significant contribution especially in the packaging of compound semiconductor devices. Further, if appropriate low-temperature annealing is performed, the composition becomes uniform and a solder having a desired composition can be formed.
[Brief description of the drawings]
FIGS. 1A to 1E are process diagrams illustrating a method for forming a lead-free solder bump in one embodiment of the present invention.
FIG. 2 is an Au—Sn phase diagram for explaining the basic idea of the present invention.
[Explanation of symbols]
1 Substrate 2 Mask 3 Pattern mask 4 Multilayer film 5 Bump precursor 6 Lead-free solder bump

Claims (5)

基板上にパターニングしたマスクを形成し、
その上から、Ｓｎ１−ｘＭｘ（Ｍ：Ａｕ，Ｉｎのうち少なくとも一つ以上を含みかつ０＜ｘ≦０．５）の組成になるように設定した膜厚のＳｎおよびＭを交互に２回以上繰り替えして蒸着してＳｎおよびＭの多層膜を形成し、
その後マスクを除去して前記多層膜からなるはんだバンプ前駆体を形成し、
つぎにアニールを行ってバンプ前駆体の組成の均一化を行い、
さらに、前駆体と同一の組成のＳｎとＭとの合金の共晶温度においてリフローさせることを特徴とする鉛フリーはんだバンプの形成法。Form a patterned mask on the substrate,
Further, Sn 1-x M x (M: including at least one of Au and In and 0 <x ≦ 0.5) , Sn and M having a film thickness set alternately are alternately set. Repeat two or more times to form a multilayer film of Sn and M by vapor deposition ,
Thereafter, the mask is removed to form a solder bump precursor composed of the multilayer film,
Next, anneal to homogenize the composition of the bump precursor,
Furthermore, the lead-free solder bump forming method is characterized by reflowing at an eutectic temperature of an alloy of Sn and M having the same composition as the precursor. 基板上にパターニングしたマスクを形成し、
その上から、Ｓｎ１−ｘＭｘ（Ｍ：Ａｕ，Ｉｎのうち少なくとも一つ以上を含みかつ０＜ｘ≦０．５）の組成になるように設定した膜厚のＳｎおよびＭを交互に６回繰り替えして蒸着してＳｎおよびＭの多層膜を形成し、
その後マスクを除去して前記多層膜からなるはんだバンプ前駆体を形成し、
つぎにアニールを行ってバンプ前駆体の組成の均一化を行い、
さらに、前駆体と同一の組成のＳｎとＭとの合金の共晶温度においてリフローさせることを特徴とする鉛フリーはんだバンプの形成法。Form a patterned mask on the substrate,
Further, Sn 1-x M x (M: including at least one of Au and In and 0 <x ≦ 0.5) , Sn and M having a film thickness set alternately are alternately set. Repeat the deposition 6 times to form a multilayer film of Sn and M ,
Thereafter, the mask is removed to form a solder bump precursor composed of the multilayer film,
Next, anneal to homogenize the composition of the bump precursor,
Furthermore, the lead-free solder bump forming method is characterized by reflowing at an eutectic temperature of an alloy of Sn and M having the same composition as the precursor. 前記はんだバンプ前駆体のアニールを該前駆体と同一の組成のＳｎとＭとの合金の共晶温度より低い温度で行うことを特徴とする請求項１または２に記載の鉛フリーはんだバンプの形成法。The lead-free solder bump formation according to claim 1 or 2 , wherein annealing of the solder bump precursor is performed at a temperature lower than a eutectic temperature of an alloy of Sn and M having the same composition as the precursor. Law. パターニングするマスクとして有機レジスト材を用い、
リフトオフ法によりマスクを除去することを特徴とする請求項１または２に記載の鉛フリーはんだバンプの形成法。Using an organic resist material as a mask for patterning,
3. The method for forming a lead-free solder bump according to claim 1 , wherein the mask is removed by a lift-off method. パターニングするマスクとして金属マスクを用いることを特徴とする請求項１または２に記載の鉛フリーはんだバンプの形成法。 3. The method for forming lead-free solder bumps according to claim 1 , wherein a metal mask is used as a mask for patterning.
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