JP3552989B2 - Bipolar device and method of manufacturing the same - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bipolar junction device such as a junction diode or a junction transistor among semiconductor devices, and a method of manufacturing the same. More specifically, the present invention relates to a bipolar transistor device using a silicon or silicon-germanium thin film as a base and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Recently, a semiconductor field which has been highly developed includes a memory field, a system integrated circuit field represented by an ASIC (Application Specific Integrated Circuit) field, and an integration of a radio frequency (Radio Frequency: RF) essential for wireless communication. It can be broadly divided into the field of circuits and the field of high-speed digital and analog ICs for data processing. The present invention relates to a semiconductor device having a high maximum vibration frequency fmax and a high cutoff frequency fT, which relates to an RFIC and a high-speed digital / analog IC in this field. In recent years when the demand for wireless communication has rapidly increased and the demand has been diversified, the necessity of a high-frequency element has been gradually increased due to improvement in communication quality, commonality of communication frequency, and diversification of communication services. Also, as social demands for ultra-high-speed information communication networks increase, research and development of devices such as high-speed and high-frequency transistors have been actively promoted.
[0003]
Recently, a 10 Gbps optical transmission IC using a 60 GHz class high speed transistor has been developed and put into practical use. The technology of a silicon high-speed device centered on a homojunction bipolar transistor (Homojunction Bipolar Transistor) that forms a base by ion-implanting impurities into silicon has an operation speed with a maximum cutoff frequency fT of 30 GHz.
As a further improvement, a heterojunction bipolar transistor (HBT) technology, in which silicon-germanium is crystal-grown to form a base, has appeared, and the fT of the current technology is 50 to 150 GHz. , Fmax have an operating speed of 50 to 160 GHz.
[0004]
Silicon-germanium (SiGe) has a smaller energy band gap (Eg) than silicon. The energy bandgap difference Eg between the emitter made of silicon and the base made of silicon-germanium causes the current gain to increase exponentially, so that fT and fmax are significantly higher than for homogeneous junction bipolar transistors. improves. Therefore, even if the impurity doping concentration implanted into the base made of SiGe is increased by exp (ΔEg), the current gain value does not decrease. Therefore, not only the base resistance is lower and the noise figure is lower, but also the power consumption can be reduced because SiGe requires a lower bias current to obtain the same fT than Si. Unlike the conventional method in which the base is formed by ion implantation, if the base of SiGe is formed by a crystal thin film growth method, the thickness of the base is ultra-miniaturized to a level of 0.02 μm or less and the bipolar element is cut off. The frequency can be increased. Since the germanium content in the SiGe base layer is distributed so as to increase linearly from the emitter side to the collector side, electrons transmitted to the base layer can be further accelerated.
Accordingly, the cutoff frequency fT and the maximum vibration frequency fmax can be further increased by appropriately adjusting the Ge distribution. SiGeHBT can apply most of existing silicon semiconductor manufacturing processes as they are. Further, fT and fmax of 100 GHz class or more can be realized by a photolithography method (Photo-Lithography) of 0.8 to 1 μm level. This is because SiGeHBT's production facility has an old production capacity of 0.25 µm to 1.0 µm, compared to the memory that requires ultra-fine photolithography technology of 0.18 to 0.25 µm level and the latest production facility for ASIC. Facilities can be reused. And while SiGeHBT process has high productivity, it is very economical.
[0005]
Patented conventional technologies related to heterojunction bipolar transistors have already been filed with IBM in the United States, NEC in Japan, Hitachi, Temic in Germany, and Korea Electronics Research Institute (ERTI) in Korea. Patents issued. The prior art relating to this SiGeHBT has the following structural characteristics and inherent problems.
[0006]
First, the patented technology owned by NEC of Japan relates to a super self-aligned NPN heterojunction bipolar transistor. In the transistor, a base thin film containing silicon-germanium is selectively grown only in a device active region of the device, and a collector-base and an emitter-base are respectively self-aligned.
[0007]
Hereinafter, a method of manufacturing the super self-aligned transistor will be briefly described with reference to FIGS.
As shown in FIG. 16, an n + type buried collector 11 is formed by ion-implanting an n + type impurity (dopant) into the p− type silicon substrate 1. A collector thin film 10 made of n-type silicon is deposited on the entire surface of the substrate 1 on which the embedded collector 11 is formed. As shown in the drawing, n + type impurity ions are implanted into a portion of the collector thin film 10 where a collector semiconductor electrode is to be formed next to form a collector sinker 13 connected to the buried collector 11. The collector thin film 10 and the substrate 1 are etched to form a trench to electrically isolate the transistor from an adjacent transistor.
The isolation trench 71 is formed by filling the trench with an insulating material such as BPSG (Boron Phosphorous Silicon Glass) containing boron and phosphorus. Then, the BPSG is polished by a chemical-mechanical polishing (CMP) method so that a surface portion of the isolation trench 71 is flat to have the same height as a surface portion of the collector thin film 10. A collector insulating film 17 of a silicon oxide film, a base semiconductor electrode film 23 of a p + type polycrystalline silicon thin film (p + poly-Si film), and an emitter of a silicon nitride film on the substrate 1 on which the collector thin film 10 and the isolation trench 71 are formed. The insulating film 37 is formed by continuous evaporation. The emitter insulating film 37 and the base semiconductor electrode film 23 made of p + type polycrystalline silicon are both etched to expose a portion intended for the emitter in the collector insulating film 17 made of a silicon oxide film. Next, an insulating material is deposited and anisotropically etched to form a first sidewall insulating film 73 on the inner sidewalls of the emitter insulating film 37 and the base semiconductor electrode film 23. Using the first sidewall insulating film 73 as a mask, the exposed collector insulating film 17 is removed by a wet etching method to expose the underlying collector thin film 10. After the collector thin film 10 is exposed, wet etching is continued to some extent to form an undercut 27a by a predetermined depth up to a predetermined portion under the base semiconductor electrode film 23. The cutoff frequency of the device is increased by additionally implanting an n-type impurity selectively only in the intrinsic collector region 15 (FIG. 16).
[0008]
Then, as shown in FIG. 17, only on the exposed collector region 10 and on the exposed base semiconductor electrode 23 in the undercut 27a, silicon-germanium to which an impurity is not selectively added and p + silicon Growing a base thin film 20 in which a germanium (p + SiGe) layer and an undoped Si layer which will later become the emitter 35 are stacked in this order. At this time, a polycrystalline layer is selectively formed on the bottom surface of the base semiconductor electrode 23. While the base connecting portion 27b is grown, a single crystalline base thin film 20 is formed on the collector thin film 10. A silicon film is selectively further formed thereon to ensure the connection between the base thin film 20 and the base semiconductor electrode 23. At this time, the growth rate of the single crystal silicon thin film starting from the base thin film 20 is adjusted so as to be slower than the growth speed of the polycrystalline base connecting portion 27b, and the impurity in the uppermost layer of the base thin film 20 is added. Minimize the growth of the thickness of the unprocessed Si layer. Then, an insulating material such as a silicon nitride film is deposited and anisotropically etched to form a first side wall insulating film 73 and a second side wall insulating film 75 which is in contact with a part of the base thin film 20. I do. Then, a part of the collector insulating film 17 is etched to expose the collector sinker 13. An n-type polycrystalline silicon film is deposited on the substrate. Then, the polycrystalline silicon film is etched to form an emitter semiconductor electrode 33 on the base thin film 20 and a collector semiconductor electrode 13a on the collector sinker 13. Impurities existing in the emitter semiconductor electrode 33 are diffused into a silicon layer on the uppermost portion of the base thin film 20 to which the impurities are not added by a heat treatment, thereby forming an n-type emitter 35. The remaining portion of the base thin film 20 becomes the intrinsic base layer 25. As a result, the collector-base portion is self-aligned through the undercut and the emitter-base portion is self-aligned by the first sidewall insulating film 73 and the second sidewall insulating film 75, respectively, without using another mask. A super self-aligned transistor is formed (FIG. 17).
[0009]
Since the undercut 27a is controlled by the progress time of the wet etching, it is very difficult to maintain the uniformity of the collector-base junction parasitic capacitance formed along the length of the undercut 27a. When a base thin film is formed on a collector layer on which an oxide film is formed by a selective crystal growth method, the impurity concentration in the base thin film and the germanium content of the SiGe layer change along the density and size of the exposed portion of the collector thin film. large. Such a phenomenon called a loading effect reduces the stability of a manufacturing process, and may reduce the uniformity of device characteristics on a single wafer. In order to reduce the influence of the loading effect, the crystal growth pressure of the base thin film must be reduced. However, in this case, the growth rate of the base thin film is very slow, and the throughput is reduced. In the conventional technique, the base electrode is formed of p + type polycrystalline silicon. Since the p + -type polycrystalline silicon has a much larger parasitic resistance than that of a metal, it is very difficult to improve the operation speed fmax of the device.
[0010]
Second, a related technology, which is owned by IBM Corporation in the United States, uses a titanium silicide thin film as an ohmic electrode for an emitter, a base, and a collector as shown in FIGS. And a SiGeHBT with reduced parasitic resistance between the base and the collector. Hereinafter, the manufacturing method will be briefly described.
[0011]
As shown in FIG. 18, an n + type impurity is ion-implanted into the p− type silicon substrate 1 to form a buried collector 11. A collector thin film 10 is formed by depositing silicon on the substrate. In order to electrically isolate adjacent elements, the collector thin film 10 and the substrate 1 are etched to form a trench. An inner wall insulating film is formed on the inner wall surface of the trench using an insulating material such as silicon oxide. The inside of the remaining trench is filled with polycrystalline silicon, and the surface is flattened by a chemical-mechanical polishing method. As a result, an isolation trench 71 filled with polycrystalline silicon is formed. The collector insulating film (field oxide film) 17 is formed by a selective oxidation (Received Local Oxidation of Silicon method (recessed LOCOS) method). In the above method, a portion excluding the active region of the collector thin film 10 is etched to a predetermined depth, and the collector thin film remaining in the portion to be etched is thermally oxidized. In other words, the collector insulating film 17 is formed only in the region excluding the collector sinker 13 formed later and the collector 15 formed with the emitter. Using the photosensitive film and the collector insulating film 17 as a mask, n-type impurity ions are implanted into the exposed collector thin film 10 to form an n + type collector sinker 13. In the above state, a p + silicon-germanium (p + SiGe) layer and a silicon layer (i-Si) to which no impurity is added are sequentially stacked, and then an n-type impurity is diffused into the uppermost layer. To grow a base thin film that can be switched to an emitter. At this time, a single-crystal (Single Crystalline) base thin film is grown on the active collector 15 and used as the base 25, and a polycrystalline (Polycrystalline) or non-crystalline is formed on the collector insulating film (field oxide film) 17. An amorphous (Amorphous) base thin film is grown and used as the base semiconductor electrode 23. The portion other than the region of the base semiconductor electrode is removed using the photosensitive film as a mask. An emitter insulating film 37 is formed by depositing a material such as silicon oxide. Using the photosensitive film as a mask, a part of the emitter insulating film 37 corresponding to the active collector 15 and the base 25 is removed to open an emitter region (FIG. 18).
[0012]
As shown in FIG. 19, n + polycrystalline silicon is deposited and patterned to form an emitter semiconductor electrode 33. Silicon oxide is deposited and anisotropically etched to form a sidewall silicon oxide film 77 on the outer wall of the emitter semiconductor electrode 33. Subsequently, the emitter insulating film 37 on the base semiconductor electrode 23 is removed by performing anisotropic etching. By selectively forming titanium silicide only on the silicon surface, a collector ohmic electrode 19, a base ohmic electrode 29, and an emitter ohmic electrode 39 are simultaneously formed. In the above device, metallic silicide ohmic electrodes 19, 29, and 39 are further formed on the semiconductor electrode to reduce the contact resistance and the base parasitic resistance (FIG. 19).
[0013]
In this case, in order to form the emitter metal electrode on the emitter ohmic electrode, the size of the emitter ohmic electrode must be larger than the size of the emitter metal electrode. When the emitter is formed narrow, the fT and fmax of the device become high. Therefore, the emitter boundary must be separated by a certain distance L at the boundary of the base ohmic electrode. In other words, the boundary of the intrinsic base beneath the emitter must be separated by a distance L from the boundary of the base ohmic electrode. Therefore, it is not possible to prevent the parasitic resistance generated by the length L of the non-intrinsic base region. On the other hand, in order to reduce the contact resistance of the emitter, the size of the emitter ohmic electrode must be large. Therefore, it is difficult to manufacture (Scale-down) an element for realizing low power while having high-speed characteristics in a very small size. In order to solve this problem, a method is considered in which the emitter ohmic electrode is extended outside the active region of the device to form an emitter terminal outside the active region. In this case, there is a problem that the parasitic resistance of the emitter is generated in the extended emitter ohmic electrode.
[0014]
Titanium silicide TiSi formed by sputtering a metal material such as titanium Ti on silicon and reacting with silicon underneath. ₂ In the base ohmic electrode, agglomeration of silicide may occur during the formation of silicide. In this case, when the silicide penetrates the base thin film and makes direct electrical contact with the collector, the cutoff frequency fT of the device decreases. In such a case, the operation speed is reduced because the base-collector is not a PN junction but a Schottky junction. For this reason, it is difficult to form the base thin film as thin as possible in order to obtain a high-speed fT. As another method, it is conceivable to form the base ohmic electrode outside the active element region by extending by L. As a result, the base parasitic resistance increases and the characteristics of the device deteriorate.
[0015]
Third, the technology owned by Temic, Germany, as shown in FIGS. 20 and 21, relates to a bipolar transistor that uses a titanium silicide layer 29 as a base ohmic electrode and is self-aligned with an emitter semiconductor electrode 33. Things. Hereinafter, the manufacturing method will be briefly described.
[0016]
As shown in FIG. 20, an n-type impurity is ion-implanted into the p-type silicon substrate 1 to form a buried collector 11. A collector thin film is formed thereon. The collector insulating film 17 is formed using the thermal oxidation process (LOCOS).
The collector insulating film 17 is not formed on the active collector region 15 and the collector sinker 13. A base thin film made of p + type silicon-germanium and an emitter thin film made of n-type silicon are continuously grown thereon. A single crystal thin film is stacked on the active collector region 15 from among the above thin films. On the other hand, a polycrystalline or amorphous thin film is stacked on the collector insulating film (field oxide film) 17. An emitter insulating film 37 is formed by sequentially depositing a silicon oxide film and a silicon nitride film on the substrate. Then, the masking film 91 is formed by patterning the silicon nitride film using the photosensitive film covering the emitter region as a mask. BF ₂ Ions are implanted and heat-treated to form ap ++ type base first semiconductor electrode layer 23a on the n− type silicon emitter film outside the emitter region. The n-type silicon emitter inside the emitter region, ie, the intrinsic emitter layer 35, remains unchanged. At the same time, the p + type SiGe base thin film outside the masking film 91 becomes the p ++ type base second semiconductor electrode layer 23b, while the p + type SiGe base layer below the intrinsic emitter layer 35, that is, the intrinsic base layer 25 is changed. Will remain without. BF ₂ Is implanted and heat-treated to diffuse boron, so that the side surface p ++ region 27 is formed along the periphery of the inside of the active collector region 15 (FIG. 20).
[0017]
As shown in FIG. 21, the base first and second semiconductor electrode layers 23a and 23b are patterned using a mask that defines a base electrode region to form the base first and second semiconductor electrodes 23a and 23b. Complete. A silicon oxide film is deposited and anisotropically etched to form a nitride masking film (emitter masking film) 91 and first sidewall insulating films 73 on the outer sidewalls of the base semiconductor electrodes 23a and 23b. In the emitter insulating film 37, the masking film 91 and a portion not covered with the first sidewall insulating film 73 are removed by an anisotropic etching method. Then, a metal such as titanium is selectively sputtered only on the exposed base first semiconductor electrode 23a and the upper portion of the collector sinker 13 and heat-treated to form the base ohmic electrode 29 and the collector ohmic electrode 19 with titanium silicide. Next, a material such as silicon oxide is deposited on the entire surface of the substrate to form a protective layer 79. The passivation layer 79 is planarized until a surface of the masking layer 91 appears in a chemical-mechanical polishing (CMP) process. Only the exposed nitride masking film 91 is removed by a selective wet etching method.
A second sidewall insulating film 75 is formed on the inner wall of the first sidewall insulating film 73. Therefore, a part of the emitter insulating film 37 is exposed and removed by the etching method, and the n-type silicon emitter layer 35 is opened. An emitter semiconductor electrode 33 is formed by depositing n + type polycrystalline silicon and patterning it on a photosensitive film. A metal such as titanium is selectively sputtered only on the emitter semiconductor electrode 33 and heat-treated to form an emitter ohmic electrode 39 of titanium silicide. The protective film 79 is patterned into a photosensitive film to form a metal contact window exposing the base ohmic electrode 29 and the collector ohmic electrode 19. A metal material is deposited and patterned with a photosensitive film to form a base terminal 81, an emitter terminal 83, and a collector terminal 85 (FIG. 22).
[0018]
In this case, in a heat treatment process for activating boron ions implanted into the base semiconductor electrodes 23a and 23b, boron ions in the p + SiGe intrinsic base layer 25 are combined with the intrinsic emitter layer 35, which is an adjacent silicon layer, and the active collector layer. It is diffused vertically inside the layer 15. Therefore, a phenomenon in which the base layer becomes thicker occurs, and the cutoff frequency decreases.
At the same time, boron ions implanted into the base semiconductor electrodes 23a and 23b are horizontally diffused and may come into contact with n-type impurities diffused from the emitter semiconductor electrode 33 made of n + type polycrystalline silicon. In this case, since the emitter-base junction becomes an n ++ / p ++ junction, a tunneling current, that is, a leakage current is generated therebetween.
[0019]
In the step of flattening the protective film 79 in the CMP step, the speed at which the silicon oxide film is polished is almost similar to the speed at which the silicon nitride film is polished, so that the uppermost surface of the masking film 91 is exposed. It is very difficult to accurately stop the step of polishing the protective film 79 at the same time. Therefore, the first sidewall insulating film 73 may be polished and removed together with the protective film 79 in some cases. Therefore, the base ohmic electrode 29 may come into contact with the emitter semiconductor electrode 33 in some cases. Further, since the protective film 79 having the shape protruding at the same time is easily removed, the protective film 79 may be removed, and the emitter semiconductor electrode 33 formed next may contact the titanium silicide base ohmic electrode 29. In order to solve the above-described problems such as the polishing of the first sidewall insulating film 73 and the protruding protective film 79, a method of forming the masking film 91 thicker is considered. However, depositing a thick silicon nitride film puts excessive stress on the substrate. Therefore, it is very difficult to precisely control the manufacturing process as in the above method.
A fourth related technology is a technology owned by the Korea Institute of Electronics and Communication (ETRI) in Korea, and relates to a bipolar transistor using silicon-germanium as a base as shown in FIGS. Hereinafter, the manufacturing method will be briefly described.
[0020]
As shown in FIG. 23, n-type impurities are ion-implanted into p-type silicon substrate 1 to form n + -type buried collector 11. A collector thin film is formed thereon using n-type silicon. A local thermal oxidation method (LOCOS) is applied to a portion other than the collector 15 and the collector sinker, which are element active regions, to form a collector insulating film 17 for electrically isolating adjacent elements. An n + collector sinker 13 is formed by implanting n-type impurity ions into the collector sinker portion. An impurity-free silicon-germanium (i-SiGe) layer, a p + type silicon-germanium (p + SiGe) layer, and no impurities are added to the entire surface of the substrate 1 on which the collector 15 and the collector sinker 13 are formed. A base thin film 20 in which silicon (i-Si) layers are sequentially stacked from bottom to top is grown. In this step, while a single-crystal thin film is deposited on the active collector 15 and the collector sinker 13, a polycrystalline or amorphous thin film is grown on the collector insulating film (field oxide film) 17. A silicon oxide film is deposited on the base thin film 20 and patterned to form a masking film 91 covering the collector sinker 13 and the intrinsic base 25 region in the active collector 15 region. BF is applied to the exposed base thin film using the masking film 91 as a mask. ₂ Implant ions. A heat treatment is performed to activate the implanted ions and restore the crystallinity of the silicon layer damaged during the ion implantation process. Then, the implanted impurity ions are diffused, and p ++ type base semiconductor electrode film 21 and p ++ region 27 are formed at the edge of collector 15 region. After that, the masking film 91 is removed. An amorphous base ohmic electrode film 29 is deposited on the base thin film by sputtering a composite target such as TiSi 2.6. A silicon oxide film 93 is further deposited on the base ohmic electrode film 29. A portion of the silicon oxide film 93 above the active base 25 is removed with a photosensitive film having a shape that opens the active base region 15. Thereafter, the opening of the base ohmic electrode film 29 is wet-etched with an HF solution. An emitter insulating film 37 is formed thereon by depositing an insulating material such as silicon oxide. The emitter insulating film 37 and the silicon oxide film 93 are etched using the photosensitive film covering the base electrode region as a mask. Thereafter, using the remaining emitter insulating film 37 and the remaining silicon oxide film 93 as a mask, the base ohmic electrode film 29 is wet-etched, and the base thin film 20 on the collector insulating film 17 is dry-etched. A side wall insulating film 77 is formed on the etched side walls of the emitter insulating film 37, the silicon oxide film 93, the base ohmic electrode 29, and the base semiconductor electrode. The emitter insulating film 37 is patterned using a photosensitive mask to open an emitter region and expose the base 25. A polycrystalline silicon thin film is deposited on the substrate, an n-type impurity is implanted into the polycrystalline silicon thin film, and patterned using a photosensitive mask to form an emitter semiconductor electrode 33 on the active base 25 and a collector semiconductor on the collector sinker 13. The electrode 13a is formed at the same time. A protective layer 79 is formed by depositing silicon oxide on the substrate. Thereafter, the substrate is heat-treated to diffuse the n-type impurity in the emitter semiconductor electrode 33 into an adjacent layer, and an impurity-doped silicon layer (i-Si), which is the uppermost layer of the base thin film, is formed as the emitter 35. I do. By patterning the protective film 79 using a photosensitive film, an emitter, a base, and a metal contact window for a collector are formed on each of the emitter semiconductor electrode 33, the base ohmic electrode 29, and the collector semiconductor electrode 13a. Thereafter, a metal material such as TiW and Al-1% Si is deposited, and the metal thin film is patterned using a photosensitive film defining a metal connection. As a result, the base terminal 81, the emitter terminal 83, and the collector terminal 85 are completed (FIG. 24).
[0021]
Also in this case, there are some problems as described below as in the other prior arts described above. First, when an amorphous TiSi 2.6 base ohmic electrode film 29 that opens the active base region 15 is patterned as a photosensitive film by a wet etching method, the wet etching rate is different from that of the silicon oxide film 93. As a result, since the side wall surface of the active base region to be etched cannot be formed uniformly, a void occurs when the emitter insulating film 37 is deposited. When a polycrystalline silicon layer for forming the emitter semiconductor electrode 33 is deposited thereon, polycrystalline silicon may be buried in the void and the emitter semiconductor electrode 33 may be directly connected to the base ohmic electrode. In addition, bubbles generated by reacting with the etchant on the surface of the amorphous TiSi 2.6 base ohmic electrode film 29 during the etching process obstruct the reaction of the wet etchant for etching the amorphous TiSi 2.6. Sometimes. As a result, a part of the amorphous TiSi 2.6 film covered with the bubble is incompletely etched, and the remaining amorphous TiSi 2.6 electrically connects the emitter semiconductor electrode 33 and the base ohmic electrode 29 to each other. In some cases.
[0022]
Second, when the base ohmic electrode film 29 outside the base electrode region is wet-etched using the emitter insulating film 37 and the silicon oxide film 93 as a mask, the etching ratio between the silicon oxide film and the amorphous TiSi 2.6 film is increased. It is difficult to form the etching side surface uniformly due to the difference between the two. When the surface to be etched is cleaned with HF as a cleaning solution, the emitter insulating film 37, the silicon oxide film 93, and the base ohmic electrode 29 are etched again, and the boundary between the base electrodes becomes rough. That is, the step of forming the base electrode is not stable, and the base electrode cannot be electrically stabilized.
[0023]
[Problems to be solved by the invention]
The conventional silicon-germanium heterojunction bipolar transistor as described above has various problems. In order to obtain a silicon-germanium heterojunction device having a high cutoff frequency, it is desirable that the base thin film be formed as thin as possible. When a bipolar transistor having a base of an ultrafine thin film is formed so as to include a base ohmic electrode made of titanium, titanium silicide often aggregates, so that it is directly connected to the collector layer through the thin base thin film. Tend to In order to solve the above-mentioned problem, in the conventional method, as shown in FIGS. 18 and 19, a titanium-based ohmic electrode is formed on the base layer shifted by a length of about L outside the active collector region. I have. As another method tried to solve such a problem, there is a conventional method described with reference to FIGS. However, in this method, when wet etching the base electrode made of amorphous TiSi 2.6, it is difficult to ensure the uniformity of the manufacturing process, and the remaining amorphous portion not etched in the active base region. A short phenomenon appears between the base and the emitter due to the quality TiSi 2.6.
[0024]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a bipolar transistor in which a silicon or silicon-germanium thin film is crystal-grown and used as a base and metal silicide is adopted as a base ohmic layer to reduce the resistance of a base electrode and a method of manufacturing the same. It is in.
[0025]
[Means for Solving the Problems]
A homojunction or heterojunction bipolar transistor according to the present invention includes a semiconductor substrate including a buried collector, an active collector and a collector sinker separated by a collector insulating film, an active base layer formed on the active collector, and the collector insulation. It comprises a first base semiconductor electrode film formed on the film. A base, a second base semiconductor electrode selectively grown only on the first base semiconductor electrode film by a masking film, and a metallic silicide selectively formed only on the second base semiconductor electrode A base ohmic electrode film, an emitter insulating film for electrically separating the emitter, an emitter formed on the active base, an emitter semiconductor electrode formed on the emitter, and a protective film covering the entire surface of the substrate; An emitter electrode formed on the emitter semiconductor electrode, the base ohmic electrode, and the collector sinker, a base electrode, and a collector electrode, respectively.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method of manufacturing the bipolar transistor according to the first embodiment of the present invention will be described in detail with reference to FIGS.
As shown in FIG. 1, an n-type impurity such as arsenic or phosphorous is ion-implanted into a p- type silicon substrate 101 and diffused to form an n + type buried collector 111, on which an n + type buried collector 111 is formed. A collector thin film 110 is formed.
[0027]
A collector insulating film (field oxide film) 117 is formed in a portion other than the portion serving as the collector active region 115 and the portion serving as the collector sinker 113 by a thermal oxidation method such as a LOCOS process. The doping concentration of the collector sinker 113 is increased by implanting an n-type impurity such as arsenic or phosphorus using a photoresist mask having an opening corresponding to the collector sinker 113. Then, the photosensitive film is removed, and heat treatment is performed to diffuse the implanted impurities. An n-type impurity such as arsenic or phosphorus is ion-implanted into the intrinsic collector 115 region using a photoresist mask. Next, the photosensitive film is removed, and heat treatment is performed to diffuse the implanted impurities, thereby forming a structure as shown in FIG.
[0028]
A base thin film 120 is deposited on the entire surface of the substrate. To form a homojunction bipolar transistor, a base thin film 120 made of silicon doped with boron is formed. When a heterojunction bipolar transistor (HBT) is formed, a seed layer made of undoped silicon, an undoped silicon-germanium (i-SiGe) layer, and ap + silicon A base thin film 120 is formed in which a germanium (p + SiGe) layer and a silicon (i-Si) layer to which an impurity is not added are stacked from below to above.
The silicon seed layer helps the silicon-germanium film to be uniformly grown on the collector insulating film, and makes the thickness of the base thin film 120 and the germanium content distribution in the base thin film 120 uniform. In other words, the so-called loading effect, in which the thickness of the base thin film, the doping concentration, and the germanium content in the base thin film change depending on the area of the Si to be opened and the density of the Si pattern to be opened, does not occur. First, a silicon seed thin film is formed. Also, when there is no Si seed thin film, the pressure of the atmosphere for growing the base thin film must be low to avoid the loading effect. Then, there arises a problem that the deposition rate is reduced and the production yield is reduced. That is, when the Si seed layer is used, the pressure for growing the base thin film can be increased, and the production yield can be maximized. The topmost Si layer to which the impurity is not added is a portion that will be replaced by the emitter next. Using the photosensitive film covering the base electrode region as a mask, the base thin film 120 is patterned and formed as shown in FIG.
[0029]
An insulating material is deposited and patterned as a mask on the photosensitive film to form a masking film 191 covering the base active region 125 and the collector sinker 113 as shown in FIG. The masking film 191 includes at least one of silicon oxide and silicon nitride. The masking film 191 divides the base thin film 120 into two parts, one serving as a base active region 125 and the other serving as a base semiconductor electrode 123a. BF using the masking film 191 as a mask ₂ Ions are implanted to form a first base semiconductor electrode 123a having a high boron doping concentration on the base thin film 120 exposed to the outside of the masking film 191 as shown in FIG. Then, heat treatment is performed to diffuse boron implanted into the first base semiconductor electrode 123a to the edge portion 127 of the active collector 115.
[0030]
As shown in FIG. 5, a second base semiconductor electrode 123b is grown on only the first base semiconductor electrode 123a, selectively doped with boron in-situ. The second base semiconductor electrode 123b includes at least one of silicon, silicon-germanium, and germanium. Next, TiN and Ti are sequentially sputtered, heat-treated, and then wet-etched to form titanium silicide (TiSiSi) only on the second base semiconductor electrode 123b. ₂ ) And titanium nitride (TiN) to selectively form a base ohmic electrode 129. The base ohmic electrode 129 is made of TiSi ₂ , TiN, CoSi ₂ , PtSi ₂ , NiSi ₂ , FeSi ₂ , CuSi ₂ , WSi, and a metal silicide containing at least one of W and Cu. The second base semiconductor electrode 123b is made of TiSi ₂ This prevents electrical contact between the base ohmic electrode 129 made of metallic silicide and the active collector 115. If the ultrafine base thin film is aggregated with the metallic silicide base ohmic electrode, the phenomenon of the above-mentioned electrical direct contact occurs. That is, the agglomerated silicide passes through the ultrafine base thin film and comes into contact with the collector 115, so that a Shottky contact is formed between the base and the collector. In this case, the base-collector junction and the emitter-base junction become asymmetric, and the voltage between the collector and the emitter is abnormally cut off, thereby deteriorating the characteristics of the device.
On the other hand, since the base ohmic electrode 129 and the second base semiconductor electrode 123b are not formed on the base active region 125, there is no limit on the thickness for preventing aggregation, and thus the thickness of the active base 125 is desired. It can be formed thin enough to realize a cutoff frequency.
[0031]
As shown in FIG. 6, an emitter insulating film 137 is formed on the entire surface of the substrate. Next, the emitter insulating film 137 and the base masking film thereunder are etched using the photosensitive film defining the emitter region as a mask to open the emitter region. Polycrystalline n + type silicon is formed and patterned using a photosensitive film defining an emitter semiconductor electrode 133 as a mask. After that, heat treatment is performed. Thereby, the n-type impurity contained in the emitter semiconductor electrode 133 is diffused into the active base 125 contacting therebelow, that is, the intrinsic base region, and the impurity at the top of the base thin film 125 is not added. The silicon (i-Si) layer is switched to the emitter 135.
[0032]
As shown in FIG. 7, a protective layer 179 is deposited on the entire surface of the substrate using an insulating material such as silicon oxide or silicon nitride. Thereafter, a base contact window is opened on the base ohmic electrode 129, an emitter contact window is opened on the emitter semiconductor electrode 133, and a collector contact window is opened on the collector sinker 113, using the photosensitive film as a mask. When opening the contact window, the masking film 191 covering the protective film 179, the emitter insulating film 137, and the collector sinker 113 is formed by etching. Next, after cleaning the surface using an HF solution, a metal electrode layer is deposited and patterned using a photosensitive film as a mask to form a base terminal 181, an emitter terminal 183, and a collector terminal 185.
[0033]
In this case, the base ohmic electrode 129 made of metallic silicide may react with the HF solution and be etched while the base ohmic electrode 129 is washed with HF. In such a case, the electrical contact between the base ohmic electrode 129 and the base terminal 181 may not be normal. To prevent this, before depositing the metal layer for the metal terminal, an additional metallic silicide layer can be selectively reformed only on the second base semiconductor electrode exposed through the base contact window. .
[0034]
A second embodiment according to the present invention is shown in FIG. As shown in FIG. 8, the masking film 191 covering the active base 125 and the collector sinker 113 includes two layers, that is, a lower film 191a containing silicon oxide and an upper film containing silicon nitride. 191b. This is to prevent the base 125 from being damaged in the step of opening the emitter region by etching the emitter insulating film 137 and the masking films 191a and 191b. The RIE process of the emitter insulating film 137 is stopped when the silicon nitride film 191b is exposed using the difference in the ratio of the ion reactive etching RIE between the silicon oxide and the silicon nitride, and then the exposed silicon nitride film is exposed. An RIE process for etching 191b is performed until the lower layer 191a made of silicon oxide is exposed. When the exposed silicon oxide film 191a is removed by the chemical wet etching method, the underlying active base layer 125 is not damaged.
[0035]
In the above embodiment of the present invention, the n-type impurity is ²¹ cm ^-3 Impurities in the highly doped emitter semiconductor electrode are diffused into the undoped silicon (i-Si) layer at the top of the base thin film to switch to an n + type emitter. At the same time, p-type impurities ¹⁹ cm ^-3 The impurities in the heavily doped p + silicon-germanium base or the undoped silicon (i-Si) layer are diffused. As a result, an n + p junction having a very high junction capacitance is formed, and the cutoff frequency decreases with a low collector current.
[0036]
The third embodiment provides a method of forming an emitter layer having a low junction capacitance at an emitter-base junction and having a high cutoff frequency even at a low collector current. Hereinafter, the manufacturing method according to the third embodiment will be described with reference to FIGS.
[0037]
As shown in FIG. 9, the base 125 includes a Si seed layer to which an impurity is not added, a SiGe layer to which an impurity is not added, and a p + SiGe layer, which are sequentially stacked from bottom to top. In this embodiment, the uppermost layer of the SiGe base layer to which the impurity is not added is not included. The emitter insulating film 137 and the masking film 191 are patterned to open the emitter region and expose the base 125 as shown in FIG. 5 and thereafter of the first embodiment.
[0038]
As shown in FIG. 10, impurities such as arsenic or phosphorus ¹⁸ cm ^-3 The emitter 135a is selectively grown only on the base 125 exposed in the emitter region using lightly doped single crystal silicon.
[0039]
As shown in FIG. 11, the emitter semiconductor electrode 133 may be formed by depositing and patterning polycrystalline silicon doped with an impurity such as arsenic or phosphorus over the entire surface.
[0040]
According to the present embodiment, the emitter 135a and the emitter semiconductor electrode 133 can be formed by another method as described below. After opening the emitter region, instead of selectively growing only emitter 135a, impurities ¹⁸ cm ^-3 A lightly doped n-type silicon emitter 135a and impurities ²¹ cm ^-3 An emitter semiconductor electrode 133 containing n-type silicon doped to a high degree is subsequently deposited. After that, the emitter 135a and the polycrystalline emitter semiconductor electrode 133 are simultaneously patterned and formed. In this case, a bipolar transistor having a structure as shown in FIG. 12 is formed.
[0041]
In the fourth embodiment, in forming an active collector, one manufacturing method for a method of defining a collector active region different from the so-called LOCOS method described in the first embodiment is shown in FIGS. It will be described with reference to FIG.
[0042]
As shown in FIG. 13, a collector insulating film 117 is deposited on the entire surface of the substrate on which the embedded collector 111 is formed. The collector insulating film 117 is patterned using the photosensitive film defining the collector active region and the collector sinker portion as a mask to define and expose the collector region 115a and the collector sinker region 113a.
[0043]
As shown in FIG. 14, single crystal silicon films 115b and 113b are grown only on the exposed silicon in the collector region and the collector sinker region by the selective crystal growth method. Normally, the grown single-crystal silicon films 115b and 113b completely fill the openings and grow to be higher than the thickness of the collector insulating film 117.
[0044]
As shown in FIG. 15, the grown and protruded silicon layers 115b and 113b are planarized by performing a CMP process. As a result, the collector insulating film 117, the active collector 115, and the collector sinker 113 are completed. Thereafter, the bipolar device is completed by the same method as in the first embodiment.
[0045]
【The invention's effect】
The present invention provides a homo-junction or hetero-junction bipolar transistor using in-situ doped and ultra-fine crystal grown silicon or silicon-germanium thin film as a base. Therefore, the base layer of the bipolar transistor according to the present invention can reduce the base thickness of the bipolar transistor formed by ion implantation. Therefore, the cutoff frequency fT and the maximum vibration frequency fmax can be increased. Generally, the SiGe layer does not aggregate very much when grown on a field oxide film. Therefore, the silicon-germanium base film tends to selectively grow only on the active collector on the substrate on which the field oxide film is patterned. As a result, the base layer is formed thicker than the critical thickness, that is, the critical thickness at which the SiGe layer grows on the silicon layer without defects even if the germanium content is different. Therefore, a defect due to lattice matching occurs in the SiGe thin film, and a SiGeHBT may not be formed. To prevent this, first, a seed thin film made of silicon is grown on a substrate on which an oxide film is patterned by a predetermined thickness, and then silicon-germanium is grown thereon. Thereby, the SiGe base layer has a more uniform thickness and the Ge content is evenly distributed. Further, the method according to the present invention has a very low growth rate and a complicated process, and the production yield is lower than that of a conventional manufacturing method in which a SiGe-based thin film is grown by a selective epitaxial growth (SEG). The rate is improved.
[0046]
In particular, TiSi is formed on the SiGe base exposed in the active collector region and the first base semiconductor electrode on the field oxide film. ₂ When forming a base ohmic electrode containing ₂ Are in direct contact with the collector through the base film by agglomeration. In this case, the performance of the element decreases. To prevent this, first, a second base semiconductor electrode doped with impurities in-situ is selectively grown only in a region where a base ohmic electrode is formed. And the stability and reproducibility of the manufacturing process are realized. Then, in order to lower the heat treatment temperature in the manufacturing process, an emitter thin film doped with a high impurity is formed in situ.
As a result, diffusion of impurities in the SiGe base thin film to the adjacent silicon collector and silicon emitter is minimized. Therefore, the base layer can be formed as thin as possible, the parasitic capacitance between the junction between the emitter and the base is reduced, and low noise and high cutoff frequency of the device can be obtained.
[0047]
Although the manufacturing steps according to some embodiments have been described above for a specific bipolar transistor, the present invention is not limited to only the above-described several embodiments. This is because those skilled in the art can easily understand that various modifications and changes can be made and various bipolar transistors can be manufactured without departing from the spirit of the present invention.
[Brief description of the drawings]
FIG. 1 is a view showing a method of manufacturing a homojunction or heterojunction bipolar transistor using a metal silicide as a base ohmic electrode and using a silicon or silicon-germanium vapor deposited thin film as a base according to the first embodiment of the present invention; It is one sectional drawing in the inside.
FIG. 2 is a cross-sectional view of the bipolar transistor shown in FIG. 1 during a manufacturing step;
FIG. 3 is a cross-sectional view of the bipolar transistor shown in FIG. 1 during a manufacturing step;
FIG. 4 is a cross-sectional view of the bipolar transistor shown in FIG. 1 during a manufacturing step;
FIG. 5 is a sectional view of the bipolar transistor shown in FIG. 1 during a manufacturing step;
FIG. 6 is a cross-sectional view of the bipolar transistor shown in FIG. 1 during a manufacturing step;
FIG. 7 is a sectional view showing a completed stage of the bipolar transistor shown in FIG. 1;
FIG. 8 is a cross-sectional view showing a similar or different type bipolar transistor using silicon or silicon-germanium as a base thin film according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view during a process showing a method of manufacturing a same or different type bipolar transistor using silicon or silicon-germanium as a base thin film according to a third embodiment of the present invention.
FIG. 10 is a sectional view of the bipolar transistor shown in FIG. 9 during a manufacturing step;
FIG. 11 is a cross-sectional view showing a completed stage of the bipolar transistor shown in FIG. 9;
FIG. 12 is a cross-sectional view showing a similar or different type bipolar transistor using silicon or silicon-germanium as a base thin film according to a modification of the third embodiment of the present invention.
FIG. 13 is a cross-sectional view during a process showing a method of manufacturing a same or different type bipolar transistor using silicon or silicon-germanium as a base thin film according to a fourth embodiment of the present invention;
FIG. 14 is a sectional view of the bipolar transistor shown in FIG. 13 during a manufacturing step;
15 is a cross-sectional view of the bipolar transistor shown in FIG. 13 during a manufacturing step thereof.
FIG. 16 is a cross-sectional view illustrating a heterojunction bipolar transistor (HBT) that is super self-aligned by selectively growing silicon-germanium only on an exposed silicon collector surface to form a base thin film according to the related art. And shows a cross section during the process.
FIG. 17 is a cross-sectional view showing the overall configuration of the heterojunction bipolar transistor of FIG.
FIG. 18 is a cross-sectional view showing a heterojunction bipolar transistor (HBT) using titanium silicide as a base ohmic electrode and using silicon-germanium as a base thin film according to a conventional technique, showing one cross section in the process. .
FIG. 19 is a cross-sectional view showing the overall configuration of the heterojunction bipolar transistor shown in FIG.
FIG. 20 is a cross-sectional view illustrating a self-aligned silicon-germanium heterojunction bipolar transistor (HBT) using metal silicide as a base ohmic electrode according to the prior art, showing a cross section during the process.
21 is a view showing one cross section of the heterojunction bipolar transistor shown in FIG. 20 in a process;
FIG. 22 is a cross-sectional view showing the overall structure of the heterojunction bipolar transistor shown in FIG.
FIG. 23 is a cross-sectional view showing a heterojunction bipolar transistor (HBT) using titanium silicide as a base ohmic electrode and silicon-germanium as a base thin film according to a conventional technique.
FIG. 24 is a cross-sectional view showing the overall structure of the heterojunction bipolar transistor shown in FIG.
[Explanation of symbols]
101 silicon substrate
110 Collector thin film
111 n + embedded collector
113 Collector sinker
115 Collector active area
117 Collector insulating film (field oxide film)
120 base thin film
123a first base semiconductor electrode
123b Second base semiconductor electrode
125 base semiconductor electrode
127 edge part
129 base ohmic electrode
179 Protective film
181 Base terminal
183 Emitter terminal
185 Collector terminal
191 Masking film
HBT heterojunction bipolar transistor

Claims (13)

Forming a collector thin film from the first conductive type semiconductor material;
Forming a base thin film of the second conductive semiconductor material on the collector thin film;
Forming a masking film of the base thin film that exposes a first base semiconductor electrode and covers a base active region;
Forming a second base semiconductor electrode on said first base semiconductor electrode by a selective crystal growth method;
By sputtering a metal on the second base semiconductor electrode, a base ohmic electrode containing silicide is overlapped with the collector thin film with the second base semiconductor electrode and the first base semiconductor electrode interposed therebetween. Forming on the second base semiconductor electrode;
A method for manufacturing a bipolar element, comprising: 2. The bipolar device according to claim 1, further comprising, after forming the masking film, implanting impurity ions into the exposed first base semiconductor electrode using the masking film as a mask. Manufacturing method. Forming a base thin film on the collector,
Forming a semiconductor layer containing second conductivity type silicon;
Forming a preliminary emitter layer containing silicon containing no impurities on the semiconductor layer;
The method for manufacturing a bipolar element according to claim 1, further comprising: Forming a base thin film on the collector,
Forming a seed layer comprising silicon;
Forming an intrinsic layer containing impurity-free silicon-germanium on the seed layer;
Forming an impurity semiconductor layer containing a second conductivity type silicon-germanium doped with a large amount of impurities on the intrinsic layer;
Forming a preliminary emitter layer containing silicon containing no impurities on the impurity semiconductor layer;
The method for manufacturing a bipolar element according to claim 1, further comprising: The masking film is formed by stacking a first masking film containing silicon oxide and a second masking film containing silicon nitride,
2. The method according to claim 1, wherein the first masking film is removed after continuously removing the protective film and the second masking film. Forming an emitter insulating film on the entire surface of the substrate on which the base ohmic electrode is formed, and patterning the emitter insulating film and the masking film to define an emitter region;
Forming an emitter in a semiconductor masking film in which only the emitter region selectively contains a first conductivity type impurity;
2. The method of claim 1, further comprising forming an emitter semiconductor electrode on the emitter as a semiconductor masking film containing a large amount of the first conductivity type impurity. . Forming an emitter insulating film on the entire surface of the substrate on which the base ohmic electrode is formed, and patterning the emitter insulating film and the masking film to define an emitter region;
An emitter layer is deposited as a semiconductor masking film containing a first conductivity type impurity on the entire surface of the substrate on which the emitter region is defined, and a semiconductor masking film containing a large amount of the first conductivity type impurity Continuously depositing an emitter semiconductor layer as
Patterning the emitter layer and the emitter semiconductor layer to form an emitter semiconductor electrode;
The method for manufacturing a bipolar device according to claim 1, further comprising: A collector comprising a semiconductor material of the first conductivity type;
An active base including a second conductivity type semiconductor material in contact with the collector;
A first base semiconductor electrode extended to a side surface of the active base and including a second conductive semiconductor material into which impurities are implanted;
A masking film that covers the active base, partitions the first base semiconductor electrode, and defines an emitter region;
A second base semiconductor electrode selectively formed only on the first base semiconductor electrode;
A silicide-based ohmic electrode containing a metal formed on the second base semiconductor electrode so as to overlap the collector thin film with the second base semiconductor electrode and the first base semiconductor electrode interposed therebetween ;
An emitter including a first conductive semiconductor material in contact with a base from an emitter region formed by opening a part of an emitter insulating film and a masking film formed on an entire surface of the substrate on which the base ohmic electrode is formed; ,
An emitter semiconductor electrode made of a first conductivity type semiconductor containing an impurity that contacts the emitter through the emitter region;
A bipolar element comprising: The base is
A semiconductor layer containing silicon of the second conductivity type;
A preliminary emitter layer containing silicon containing no impurities on the semiconductor layer;
9. The bipolar device according to claim 8, comprising: The base is
A seed layer containing silicon;
An intrinsic layer containing silicon-germanium containing no impurities formed on the seed layer;
An impurity layer formed on the intrinsic layer and containing silicon-germanium containing impurities,
A preliminary emitter layer containing silicon not doped with an impurity on the impurity layer,
Characterized in that it comprises a bipolar element according to claim 8. The masking film,
A first masking film containing silicon nitride;
A second masking film containing silicon oxide;
9. The bipolar element according to claim 8, wherein are stacked. The first conductive type semiconductor layer containing an impurity in contact with the base is selectively formed in the emitter region, and is in contact with the first conductive type emitter semiconductor electrode. Item 10. The bipolar device according to item 8, The emitter semiconductor electrode,
A first conductivity type semiconductor layer containing an impurity in contact with the base in the emitter region;
A first conductivity type semiconductor layer containing a large amount of impurities,
9. The bipolar element according to claim 8, wherein the bipolar element is constituted by:

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