JP3546634B2 - Selective etching method for nitride-based compound semiconductor and method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nitride compound semiconductor selective etching method and a semiconductor device.Manufacturing methodParticularly, the present invention is suitably applied to a semiconductor device using a nitride III-V compound semiconductor such as GaN.
[0002]
[Prior art]
A GaN-based semiconductor is a direct transition semiconductor, and its forbidden band width ranges from 1.9 eV to 6.2 eV. Since it is theoretically possible to realize a light-emitting element capable of emitting light in the visible region to the ultraviolet region, In recent years, it has attracted attention and its development is being actively promoted. GaN-based semiconductors also have great potential as materials for electron transit devices. That is, the saturated electron velocity of GaN is about 2.5 × 10⁷cm / s, which is larger than Si, GaAs and SiC, and the breakdown electric field is about 5 × 10⁶V / cm, second only to diamond. For these reasons, GaN-based semiconductors have been expected to have great potential as materials for high-frequency, high-power semiconductor devices.
[0003]
However, when an electron transit device is manufactured using a GaN-based semiconductor, a conventional method of forming a conductive layer by ion implantation of impurities cannot be applied. different. That is, since impurities implanted in the GaN-based semiconductor are not activated by thermal annealing, for example, in a FET using a GaN-based semiconductor, a source region and a drain region having a carrier concentration sufficiently high for practical use are formed. Therefore, the source electrode and the drain electrode cannot be in ohmic contact with the source region and the drain region, respectively, with low contact resistance.
[0004]
For this reason, as an FET using a GaN-based semiconductor, an FET having a structure as shown in FIG. 13 without using a method of forming a conductive layer by ion implantation of impurities has been experimentally manufactured (Appl. Phys. Lett., 62 (15), 1786 (1993)). As shown in FIG. 13, in this FET, an undoped GaN layer 102 and an n-type GaN layer 103 as a channel layer are sequentially laminated on a c-plane sapphire substrate 101, and a gate electrode 104 and a source are formed on the n-type GaN layer 103. An electrode 105 and a drain electrode 106 are provided. Here, the gate electrode 104 is in Schottky contact with the n-type GaN layer 103, and the source electrode 105 and the drain electrode 106 are in ohmic contact with the n-type GaN layer 103.
[0005]
Further, when a GaN-based semiconductor is used, in addition to the above-described difficulty that a method of forming a conductive layer by ion implantation of impurities cannot be applied, an effective wet etching solution for GaN-based semiconductors is not yet available. It has not been developed, and there is also a difficulty that etching cannot be performed at all with a wet etching technique using an ordinary acid or alkali. For this reason, in a FET using a GaN-based semiconductor, it has been difficult to satisfactorily form a so-called recess gate structure used for reducing a source resistance in an FET using a GaAs-based semiconductor. Here, if the reactive ion etching (RIE) method under the condition of a large physical mode is used, it is possible to form a recess gate structure. However, this RIE method causes damage to a layer to be etched and a base. In addition, since selective etching is difficult, there is a problem in that a layer to be etched has to be etched down to its base, which is practically difficult to apply.
[0006]
On the other hand, as a high electron mobility transistor (HEMT) using a GaN-based semiconductor, an AlGaN / GaN HEMT having a structure as shown in FIG. 14 has been prototyped (Appl. Phys. Lett., 68 (Appl. 4), 22 (1996)). As shown in FIG. 14, in this AlGaN / GaN HEMT, an undoped GaN layer 202, an undoped GaN layer 203 as an electron transit layer, and an n-type AlGaN layer 204 as an electron supply layer are sequentially laminated on a c-plane sapphire substrate 201. A gate electrode 205, a source electrode 206, and a drain electrode 207 are provided on the n-type AlGaN layer 204. Here, the gate electrode 205 is in Schottky contact with the n-type AlGaN layer 204.
[0007]
However, in the AlGaN / GaN HEMT shown in FIG. 14, the source electrode 206 and the drain electrode 207 are formed on the n-type AlGaN layer 204 having a low electron concentration, and the source electrode 206 and the drain electrode 207 as in the AlGaAs / GaAs HEMT. Due to the difficulty in forming an ohmic contact alloy layer below the drain electrode, the contact resistance between the source electrode 206 and the drain electrode 207 is extremely high. For this reason, the performance of this AlGaN / GaN HEMT was low.
[0008]
An FET using an AlGaN / GaN junction having a structure as shown in FIG. 15 has also been trial manufactured (Appl. Phys. Lett., 69 (6), 794 (1996)). As shown in FIG. 15, in this FET, an undoped GaN layer 302, an n-type GaN layer 303 as an electron transit layer, an undoped AlGaN layer 304 as a spacer layer, and an n as an electron supply layer are formed on a c-plane sapphire substrate 301. AlGaN layers 305 are sequentially stacked, and a gate electrode 306, a source electrode 307, and a drain electrode 308 are provided on the n-type AlGaN layer 305. Here, the gate electrode 306 is in Schottky contact with the n-type AlGaN layer 305, and the source electrode 307 and the drain electrode 308 are in ohmic contact with the n-type AlGaN layer 305. This FET has a structure similar to that of the HEMT, but differs from a normal HEMT in that a doped n-type GaN layer 303 is used for an electron transit layer.
[0009]
However, in the FET shown in FIG. 15, since the source electrode 307 and the drain electrode 308 are formed on the n-type AlGaN layer 305, the contact resistance is not sufficiently low. Not.
[0010]
As an FET using a GaN-based semiconductor, a FET as shown in FIG. 16 has been experimentally manufactured (Appl. Phys. Lett., 65 (9), 1121 (1994)). As shown in FIG. 16, in this FET, an n-type GaN layer 402 as an electron transit layer and an n-type AlGaN layer 403 as an electron supply layer are sequentially laminated on a c-plane sapphire substrate 401. The n-type AlGaN layer 403 is patterned into a predetermined shape. A gate electrode 404 is provided on the n-type AlGaN layer 403, and a source electrode 405 and a drain electrode 406 are formed on the n-type GaN layer 402 so as to be in contact with both side walls of the n-type AlGaN layer 403. Is provided. Here, the gate electrode 404 is in Schottky contact with the n-type AlGaN layer 403, and the source electrode 405 and the drain electrode 406 are in ohmic contact with the n-type GaN layer 402 and the n-type AlGaN layer 403. This FET has a structure similar to that of a HEMT, but differs from a normal HEMT in that an n-type GaN layer 402, which is a doped layer, is used for an electron transit layer.
[0011]
However, in the FET shown in FIG. 16, since the physical etching method such as the RIE method must be used for patterning the n-type AlGaN layer 403, the n-type AlGaN layer 403 and the underlying n-type GaN layer There is a problem that the element 402 is damaged and the element characteristics are deteriorated.
[0012]
On the other hand, in a semiconductor laser using a GaN-based semiconductor, a semiconductor laser using a GaAs-based semiconductor, which is used to reduce a threshold current, that is, a so-called rigid structure is preferably formed by using a GaN-based semiconductor. It has been difficult for the same reason that it is difficult to form a recess gate structure well in an FET.
[0013]
[Problems to be solved by the invention]
As described above, in the manufacture of an electron transit element or a semiconductor laser using a GaN-based semiconductor, a problem inherent to the GaN-based semiconductor, that is, it is difficult to perform selective etching and difficult to form a conductive layer by ion implantation of impurities. Therefore, there are many problems caused by the above, and the solution has been desired.
[0014]
The present invention solves these problems at once. That is, an object of the present invention is to provide a nitride-based compound semiconductor that does not contain aluminum and that can be almost completely selectively etched with respect to an underlayer and that is not damaged during etching. Using a selective etching method and such a selective etching methodSemiconductor device manufacturing methodIs to provide.
[0015]
[Means for Solving the Problems]
The present inventor has conducted intensive studies to solve the above-mentioned problems of the prior art, and as a result, has almost completely selectively etched a nitride-based compound semiconductor containing no aluminum such as GaN or GaInN with respect to a base. Focusing on the fact that if a selective etching method for a nitride-based compound semiconductor that does not cause damage during etching can be obtained, the above-mentioned problems can be solved at once, and through various experiments, The present inventors have found a specific method and have come up with the present invention.
[0016]
That is, in order to achieve the above object, the method for selectively etching a nitride-based compound semiconductor according to the present invention comprises:
A nitride gas containing aluminum is used by using an etching gas composed of a mixed gas of a first gas composed of at least one of a halogen gas and a halogen compound gas and a second gas composed of at least one of a hydrogen gas and an inert gas. Nitride-based compound semiconductor containing no aluminum as an etch stop layerThermochemically in the gas phase,Selective etching
It is characterized by the following.
[0017]
Here, the halogen gas or the halogen compound gas used as the first gas may be basically any gas as long as it separates halogen at the etching temperature. Specifically, the halogen gas is X₂(X = F, Cl, Br). The halogen compound gas is a gas of a compound of halogen and hydrogen (a kind of hydride gas), specifically, HX (X = F, Cl, Br), or a compound of halogen and carbon, specifically, for example, CX₄(X = F, Cl, Br) or a gas of a compound of halogen, hydrogen, and carbon, specifically, for example, CH₃X (X = F, Cl, Br) and the like. The inert gas used as the second gas is specifically N 2₂, Ar, Xe, He and the like. Further, in order to prevent surface roughness of the nitride-based compound semiconductor during etching, a compound gas that releases active nitrogen is preferably included in addition to these gases. The compound that releases active nitrogen is, for example, ammonia or an amine compound. Specific examples of the amine compound include trimethylamine, dimethylamine, and diethylamine.
[0018]
In addition, the etching is performed within a range where a required etching rate is obtained and the crystal of the nitride-based compound semiconductor serving as the etching stop layer and the nitride-based compound semiconductor is broken, crystallinity is deteriorated, and the surface is roughened, that is, the damage is not caused. Perform at temperature. In particular, when the object to be etched and the etching stop layer are nitride-based III-V compound semiconductors, the etching is typically performed at a temperature of 550 ° C to 900 ° C. Here, when the etching is performed at a temperature lower than 550 ° C., the etching rate is too low. When the etching is performed at a temperature higher than 900 ° C., the nitride-based III-V compound semiconductor, which is an etching target and an etching stop layer, is formed. Damage will occur. In order to obtain a sufficient etching rate and effectively suppress damage to the object to be etched and the nitride III-V compound semiconductor as the etching stop layer, this etching is preferably performed at 600 ° C. or more and 800 ° C. or less. Perform at temperature.
[0020]
Also, a semiconductor device according to the present inventionThe manufacturing method of
A nitride gas containing aluminum is used by using an etching gas composed of a mixed gas of a first gas composed of at least one of a halogen gas and a halogen compound gas and a second gas composed of at least one of a hydrogen gas and an inert gas. A step of thermochemically and selectively etching a nitride-based compound semiconductor containing no aluminum as a gaseous compound semiconductor as an etching stop layer,
Forming a sidewall spacer on the side wall of the selectively etched portion of the nitride-based compound semiconductor not containing aluminum;
Forming a gate electrode on a nitride-based compound semiconductor containing aluminum in a portion between the sidewall spacers;
Which is characterized by having
[0021]
In the present invention, the nitride-based compound semiconductor containing aluminum is typically Al_xGa_1-xN (however, 0.02 ≦ x ≦ 1), and the nitride-based compound semiconductor not containing aluminum is Ga_1-yIn_yN (where 0 ≦ y ≦ 1).
[0022]
In the present invention configured as described above, the nitride-based compound semiconductor containing no aluminum is etched thermochemically in the gas phase by the action of the halogen contained in the etching gas. On the other hand, the nitride-based compound semiconductor containing aluminum is not substantially etched by the action of aluminum contained therein. That is, the nitride-based compound semiconductor containing no aluminum can be almost completely selectively etched with respect to the nitride-based compound semiconductor containing aluminum as a base. Further, at the time of this etching, it is possible to prevent the nitride-based compound semiconductor containing no aluminum and the nitride-based compound semiconductor containing aluminum from being damaged. Further, since the etching rate is mainly controlled by the temperature, the controllability of the etching is good.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0024]
In the following embodiments, a structure is used in which a layer made of a nitride III-V compound semiconductor such as GaN, AlGaN, or GaInN is laminated on a c-plane sapphire substrate. A general method for growing a group III compound semiconductor by metal organic chemical vapor deposition (MOCVD) will be described.
[0025]
In growing these nitride III-V compound semiconductors, the source gases are trimethylgallium (TMG) as a Ga source, trimethylaluminum (TMA) as an Al source, trimethylindium (TMIn) as an In source, and an N source. As ammonia (MH₃), Silane (SiH₄), Cyclopentadienyl magnesium (Cp₂Mg). Then, as is well known, first, a buffer layer made of AlN or GaN is grown on a c-plane sapphire substrate at low temperature, and then NH 3₃The growth temperature is raised to about 1000 ° C. while flowing gas to grow GaN, AlGaN, and the like on the buffer layer. Here, when growing a nitride III-V compound semiconductor containing In such as GaInN, the growth temperature is lowered to 700 to 800 ° C., and the atmosphere gas is nitrogen (N₂) Is also well known.
[0026]
Next, the measurement results of the etching rate of GaN will be described. A sample for measuring the etching rate was prepared as follows. First, after growing a buffer layer made of AlN or GaN at a low temperature on a c-plane sapphire substrate, a GaN layer having a thickness of 5 μm is grown on the buffer layer. Next, a SiO having a stripe shape is formed on the GaN layer.₂A mask made of a film is formed. Next, the c-plane sapphire substrate is introduced into a reaction furnace. Next, N₂An etching gas in which a gas was mixed with HCl gas at a predetermined ratio was flowed into the reaction furnace at a flow rate of 100 to 200 cc / min, and the sample was exposed to the etching gas at a temperature of 600 to 800 ° C. for 5 to 60 minutes.
[0027]
FIG. 1 shows the relationship between the etching time and the etching depth when the GaN layer is etched at 700 ° C. while flowing an etching gas containing 10% HCl at a flow rate of 100 cc / min. FIG. 2 shows the relationship between the etching temperature (T) and the etching rate under the same conditions.
[0028]
As shown in FIG. 2, the etching of GaN by HCl is based on a chemical reaction, the activation energy of the reaction is 1.43 eV, and the etching rate varies from 1 nm / min (600 ° C.) to 20 nm / min (800 ° C) or more. In addition, FIG. 1 shows that there is no time delay in the etching, and the etching depth can be precisely controlled by time.
[0029]
Next, the measurement results of the etching rate of AlGaN will be described. A sample for measuring the etching rate was prepared as follows. First, after growing a buffer layer made of AlN or GaN by low-temperature growth on a c-plane sapphire substrate, a GaN layer is grown on the buffer layer, and then a 0.5 μm thick AlGaN layer is formed on the GaN layer. Grow. Next, a SiO having a stripe shape is formed on the AlGaN layer.₂A mask made of a film is formed. Next, the c-plane sapphire substrate is introduced into a reaction furnace. Next, N₂An etching gas in which a gas was mixed with HCl gas at a predetermined ratio was flowed into the reaction furnace at a flow rate of 100 to 200 cc / min, and the sample was exposed to the etching gas at a temperature of 600 to 800 ° C. for 5 to 60 minutes. The Al composition ratio of the AlGaN layers of these samples was changed to three levels of 7%, 15% and 50%. On the other hand, for comparison, a sample in which a GaN layer was grown on a c-plane sapphire substrate via a buffer layer was separately prepared, and this sample was simultaneously exposed to an etching gas.
[0030]
First, an attempt was made to etch the AlGaN layer at 700 ° C. for 10 minutes while flowing an etching gas containing 5% HCl at a flow rate of 100 cc / min. As a result, none of the three samples was etched at all. On the other hand, when the height of the step on the surface of the GaN layer of another sample simultaneously exposed to the etching gas was measured, it was about 55 nm. That is, the GaN layer was etched by about 55 nm.
[0031]
Next, when the AlGaN layer was etched at 800 ° C. for 30 minutes while flowing an etching gas containing HCl at 10% at a flow rate of 100 cc / min, the AlGaN layer was hardly etched in any of the three samples. Was. On the other hand, the GaN layer of another sample simultaneously exposed to the etching gas was etched by about 1.6 μm.
[0032]
Observation of the surface of the AlGaN layer, which was attempted to be etched as described above, with a scanning electron microscope (SEM) revealed₂Masked area and SiO₂An area not covered with the film mask was barely distinguishable as a contrast, and no clear step was observed.
[0033]
As described above, in this experiment, even if the GaN layer was etched by about 1.6 μm, the AlGaN layer having an Al composition ratio of 7%,_0.07Ga_0.93The N layer is not etched. The reason for the etching resistance of the AlGaN layer is considered to be derived from the strength of the Al-N bond. However, the reason why the addition of a very small amount of Al exhibits a large etching resistance has not yet been elucidated.
[0034]
Next, a method of manufacturing the AlGaN / GaN HEMT according to the first embodiment of the present invention will be described.
[0035]
In the first embodiment, first, as shown in FIG. 3, an undoped GaN layer 2 and an undoped AlGaN layer are formed on a c-plane sapphire substrate 1 via a buffer layer (not shown) made of AlN or GaN. 3. n doped with, for example, Si as an n-type impurity⁺-Type AlGaN layer 4, undoped GaN layer 5, n-type AlGaN layer 6 doped with, for example, Si as n-type impurity, and n-type impurity doped with Si as n-type impurity⁺Type GaN layers 7 are sequentially grown. Here, the undoped GaN layer 5 is an electron transit layer, n⁺The AlGaN layer 4 and the n-type AlGaN layer 6 are electron supply layers. The thickness of the undoped AlGaN layer 3 is, for example, 300 nm, n⁺The thickness of the type AlGaN layer 4 is, for example, 5 nm, the thickness of the undoped GaN layer 5 is, for example, 15 nm, the thickness of the n-type AlGaN layer 6 is, for example, 15 nm, n⁺The thickness of the type GaN layer 7 is, for example, 150 nm.
[0036]
Next, as shown in FIG.⁺For example, a 0.4 μm thick SiO₂After forming the film 8, this SiO₂The film 8 is patterned into a predetermined stripe shape by lithography and etching. This SiO₂The portion not covered by the film 8 is an element isolation region. This SiO₂The film 8 is etched by, for example, a wet etching method using a hydrofluoric acid-based etching solution or an RIE method using a fluorine-based etching gas.
[0037]
Next, SiO 2₂Using the film 8 as an etching mask, etching is performed, for example, by RIE until the undoped AlGaN layer 3 is reached. The etching depth at this time is, for example, 0.35 μm.
[0038]
Next, as shown in FIG. 5, after a resist pattern (not shown) having a predetermined shape for forming a source electrode and a drain electrode is formed by lithography, the resist pattern is used as an etching mask to form SiO 2.₂The openings 8a and 8b are formed by etching the film 8. Next, for example, a Ti / Al / Au film (not shown) is formed on the entire surface by, for example, a vacuum evaporation method. Next, this resist pattern is removed together with the Ti / Al / Au film formed thereon (lift-off). Thereby, n in the portions of the openings 8a and 8b⁺Source electrode 9 and drain electrode 10 are formed on type GaN layer 7, respectively. Thereafter, in order to reduce the contact resistance between the source electrode 9 and the drain electrode 10, for example, N₂Annealing is performed in an atmosphere at 800 ° C. for 10 minutes.
[0039]
Next, as shown in FIG. 6, by lithography and etching, SiO 2 in the gate electrode formation region is formed.₂After removing the film 8, HCl and N₂Thermochemical etching is performed at 700 ° C. for 50 minutes using an etching gas containing a mixed gas of HCl and 10%. N at this time⁺The etching depth of the type GaN layer 7 is about 0.15 μm. In this case, this n⁺When the n-type AlGaN layer 7 is etched and the underlying n-type AlGaN layer 6 is exposed, the etching is completely stopped, so that the n-type AlGaN layer 6 is not etched at all.
[0040]
Next, for example, a 0.3 μm thick SiO₂After forming the film, the film is etched back by the RIE method. Thereby, n in the gate electrode formation region⁺-Type GaN layer 6 and SiO₂SiO on the side wall of the film 8₂Is formed.
[0041]
Next, after a resist pattern (not shown) having a predetermined shape for forming a gate electrode is formed by lithography, for example, a Ti / Au film is formed on the entire surface by, for example, a vacuum evaporation method. Next, the resist pattern is removed together with the Ti / Au film formed thereon. Thereby, as shown in FIG. 7, a gate electrode 12 in Schottky contact with n-type AlGaN layer 6 is formed.
[0042]
Thus, the target AlGaN / GaN HEMT is manufactured.
[0043]
In this AlGaN / GaN HEMT, the undoped GaN layer 5 which is an electron transit layer and the n⁺A two-dimensional electron gas (not shown) exists in the undoped GaN layer 5 near the interface with the n-type AlGaN layer 4 and the n-type AlGaN layer 6.
[0044]
According to the first embodiment, the following various advantages can be obtained. That is, n in the gate electrode formation region⁺During the etching of the n-type AlGaN layer 7, that is, the recess etching, the etching is completely stopped when the underlying n-type AlGaN layer 6 is exposed, so that the thickness of the n-type AlGaN layer 6 in the gate electrode formation region is reduced. There is no decrease, so that the distance between the undoped GaN layer 5 as the electron transit layer and the gate electrode 12 can be accurately defined by the thickness of the n-type AlGaN layer 6. Further, as described above, n in the gate electrode formation region⁺Since the recess etching of the type GaN layer 7 is possible, the source resistance can be significantly reduced. In the recess etching, n⁺Damage to the n-type AlGaN layer 6 and the n-type GaN layer 7 can be prevented. Further, the source electrode 9 and the drain electrode 10 have a high carrier concentration of n.⁺Since it is formed on the type GaN layer 7, the contact resistance between the source electrode 9 and the drain electrode 10 can be significantly reduced. Further, n in the gate electrode formation region⁺The gate electrode 12 is formed in a self-aligned manner after the sidewall spacer 11 is formed on the side wall of the removed portion after the type GaN layer 7 is selectively removed. The gate length can be reduced to a dimension twice as small as the thickness of the gate 11. On the other hand, the size of the upper portion of the gate electrode 12 can be made sufficiently large, so that the gate resistance can be significantly reduced. As described above, a high-performance, high-speed, high-power AlGaN / GaN HEMT can be obtained.
[0045]
Next, a method of manufacturing the ridge-type AlGaN / GaInN semiconductor laser according to the second embodiment of the present invention will be described.
[0046]
In the second embodiment, as shown in FIG. 8, first, for example, Si is doped as an n-type impurity on a c-plane sapphire substrate 21 via a buffer layer (not shown) made of AlN or GaN. N-type GaN layer 22, n-type AlGaN cladding layer 23 similarly doped with Si as an n-type impurity, GaInN active layer 24 undoped, p-type AlGaN cladding layer 25 doped with, for example, Mg as a p-type impurity, and Similarly, a p-type GaN layer 26 doped with Mg as a p-type impurity is sequentially grown. Here, the n-type GaN layer 22 becomes a contact layer of the n-side electrode, and the p-type GaN layer 26 becomes a contact layer of the p-side electrode. The Al composition ratio of the n-type AlGaN cladding layer 23 and the p-type AlGaN cladding layer 25 is, for example, 0.15, and the In composition ratio of the GaInN active layer 24 is, for example, 0.05. The thickness of these layers is, for example, 4 μm for the n-type GaN layer 22, 0.5 μm for the n-type AlGaN cladding layer 23, 0.05 μm for the GaInN active layer 24, and 0.5 μm for the p-type AlGaN cladding layer 25. , P-type GaN layer 26 is 1 μm.
[0047]
Next, for example, a 0.3 μm-thick SiO 2₂After forming a film (not shown), the SiO₂The film is patterned into a predetermined stripe shape having a width of, for example, 7 μm by lithography and etching. Next, this SiO₂Using the film as an etching mask, HCl and N₂The p-type GaN layer 26 is subjected to thermochemical etching at 750 ° C. for 1 hour using an etching gas containing a mixed gas of 10% HCl. Thereby, as shown in FIG. 9, the p-type GaN layer 26 is patterned into a predetermined stripe shape. In this case, when the p-type GaN layer 26 is etched and the underlying p-type AlGaN cladding layer 25 is exposed, the etching is completely stopped, so that the p-type AlGaN cladding layer 25 is not etched at all. Therefore, the upper surface of the p-type AlGaN cladding layer 25 in the portion covered by the p-type GaN layer 26 and the upper surface of the p-type AlGaN cladding layer 25 in the portion not covered by the p-type GaN layer 26 are continuously connected. Are on the same plane. At the time of this etching, annealing of the p-type AlGaN cladding layer 25 and the p-type GaN layer 26 is performed at the same time, and Mg doped therein is activated.
[0048]
Next, the above-mentioned SiO used as an etching mask was used.₂After the film is etched away, as shown in FIG. 10, for example, a 0.3 μm thick SiO₂A film 27 is formed. Next, this SiO₂After a resist pattern (not shown) having a predetermined shape for forming a p-side electrode is formed on the film 27 by lithography, the resist pattern is used as an etching mask to form SiO 2.₂An opening 27a is formed by etching the film 27. The width of the opening 27a is, for example, 5 μm. Next, after forming, for example, a Ti / Pt / Au film on the entire surface by, for example, a vacuum evaporation method, the resist pattern is removed together with the Ti / Pt / Au film formed thereon. Thus, a p-side electrode 28 is formed on the p-type GaN layer 26 at the portion of the opening 27a.
[0049]
Next, SiO 2₂After a resist pattern (not shown) having a predetermined shape of, for example, 3 μm in thickness is formed on the film 27 by lithography, the resist pattern is used as an etching mask by, for example, RIE.₂The film 27, the p-type AlGaN cladding layer 25, the GaInN active layer 24, and the n-type AlGaN cladding layer 23 are sequentially etched. Next, after a resist pattern (not shown) having a predetermined shape for forming an n-side electrode is formed by lithography, for example, a Ti / Al / Pt / Au film is formed on the entire surface by, for example, a vacuum evaporation method. Next, the resist pattern is removed together with the Ti / Al / Pt / Au film formed thereon. Thus, an n-side electrode 29 is formed on the n-type GaN layer 22. Thereafter, in order to lower the contact resistance of the n-side electrode 29, for example, N₂Annealing is performed in an atmosphere at 800 ° C. for 10 minutes.
[0050]
Thus, the intended ridge type AlGaN / GaInN semiconductor laser is manufactured.
[0051]
According to the second embodiment, the p-type GaN layer 26 is patterned into a stripe shape by thermochemical etching, so that the ridge portion formed of the p-type GaN layer 26 having the stripe shape is removed from the p-type GaN layer 26. 26 and the p-type AlGaN cladding layer 25 can be formed without causing any damage. By forming the ridge structure in this manner, the threshold current of the semiconductor laser can be reduced. Further, the annealing for activating Mg doped in the p-type AlGaN cladding layer 25 and the p-type GaN layer 26 can be shared by the thermochemical etching for patterning the p-type GaN layer 26, so that this Therefore, it is not necessary to perform annealing for forming the semiconductor laser independently. Therefore, the manufacturing process of the semiconductor laser can be simplified accordingly.
[0052]
Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical idea of the present invention are possible.
[0053]
For example, the numerical values, structures, materials, raw materials, growth methods, and the like described in the first and second embodiments are merely examples, and different numerical values, structures, materials, raw materials, and growth methods may be used as necessary. Or the like may be used.
[0054]
Specifically, in the first embodiment described above, n⁺The source electrode 9 and the drain electrode 10 are in contact with the n-type GaN layer 7.⁺N instead of n-type GaN layer 7⁺N-type GaInN layer.⁺The source electrode 9 and the drain electrode 10 may be brought into contact with the GaInN type layer. In this case, the contact resistance between the source electrode 9 and the drain electrode 10 can be further reduced. The AlGaN / GaN HEMT according to the first embodiment described above has an n-type AlGaN layer 6 as an electron supply layer and an n-type AlGaN layer 6 above and below an undoped GaN layer 5 as an electron transit layer.⁺Although the present invention is a so-called double-doped HEMT provided with a p-type AlGaN layer 4, the present invention is directed to a so-called forward type in which an n-type AlGaN layer 6 as an electron supply layer is laminated on an undoped GaN layer 5 as an electron transit layer. A HEMT or a so-called reverse HEMT in which an undoped GaN layer 5 serving as an electron transit layer is stacked on an n-type AlGaN layer 6 serving as an electron supply layer may be used. Further, as the electron transit layer, for example, an undoped GaInN layer may be used instead of the undoped GaN layer 5.
[0055]
【The invention's effect】
As described above, according to the present invention, since the etching is performed thermochemically in the gas phase, the nitride-based compound semiconductor containing no aluminum can be almost completely selectively etched with respect to the base. It is possible to prevent damage during etching.
[Brief description of the drawings]
FIG. 1 is a schematic diagram illustrating a relationship between an etching time and an etching depth of a GaN layer.
FIG. 2 is a schematic diagram illustrating a relationship between an etching temperature and an etching rate of a GaN layer.
FIG. 3 is a cross-sectional view for explaining the method for manufacturing the AlGaN / GaN HEMT according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view for explaining the method for manufacturing the AlGaN / GaN HEMT according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view for explaining the method for manufacturing the AlGaN / GaN HEMT according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view for explaining the method for manufacturing the AlGaN / GaN HEMT according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view for explaining the method for manufacturing the AlGaN / GaN HEMT according to the first embodiment of the present invention.
FIG. 8 is a sectional view for explaining a method for manufacturing a ridge-type AlGaN / GaInN semiconductor laser according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the ridge-type AlGaN / GaInN semiconductor laser according to the second embodiment of the present invention.
FIG. 10 is a cross-sectional view for explaining the method for manufacturing the ridge-type AlGaN / GaInN semiconductor laser according to the second embodiment of the present invention.
FIG. 11 is a cross-sectional view for explaining the method for manufacturing the ridge-type AlGaN / GaInN semiconductor laser according to the second embodiment of the present invention.
FIG. 12 is a cross-sectional view for explaining the method for manufacturing the ridge-type AlGaN / GaInN semiconductor laser according to the second embodiment of the present invention.
FIG. 13 is a sectional view showing an FET using a GaN-based semiconductor according to a first conventional example.
FIG. 14 is a cross-sectional view showing an FET using a GaN-based semiconductor according to a second conventional example.
FIG. 15 is a sectional view showing an FET using a GaN-based semiconductor according to a third conventional example.
FIG. 16 is a sectional view showing an FET using a GaN-based semiconductor according to a fourth conventional example.
[Explanation of symbols]
1, 21 ... c-plane sapphire substrate, 2, 5 ... undoped GaN layer, 3 ... undoped AlGaN layer, 4 ... n⁺-Type AlGaN layer, 6 ... n-type AlGaN layer, 7 ... n⁺-Type GaN layer, 8, 27 ... SiO₂Film 9 source electrode 10 drain electrode 12 gate electrode 22 n-type GaN layer 23 n-type AlGaN clad layer 24 GaInN active layer 25 ... p-type AlGaN cladding layer, 26 ... p-type GaN layer, 28 ... p-side electrode, 29 ... n-side electrode

Claims (8)

A nitride gas containing aluminum is used by using an etching gas composed of a mixed gas of a first gas composed of at least one of a halogen gas and a halogen compound gas and a second gas composed of at least one of a hydrogen gas and an inert gas. A nitride-based compound semiconductor that does not contain aluminum is selectively etched in a gas phase thermochemically using a nitride-based compound semiconductor as an etching stop layer. A nitride gas containing aluminum is used by using an etching gas composed of a mixed gas of a first gas composed of at least one of a halogen gas and a halogen compound gas and a second gas composed of at least one of a hydrogen gas and an inert gas. A step of thermochemically and selectively etching a nitride-based compound semiconductor containing no aluminum as a gaseous compound semiconductor as an etching stop layer,
Forming a sidewall spacer on the side wall of the selectively etched portion of the nitride-based compound semiconductor not containing aluminum;
Forming a gate electrode on the nitride-based compound semiconductor containing aluminum in a portion between the sidewall spacers;
A method for manufacturing a semiconductor device, comprising: 3. The method according to claim 2, wherein the halogen compound gas is a gas of a compound of halogen and hydrogen. 3. The method according to claim 2, wherein the halogen compound gas is a gas of a compound of halogen and carbon. 3. The method according to claim 2, wherein the halogen compound gas is a gas of a compound of halogen, hydrogen and carbon. The method according to claim 2, wherein the etching gas further includes a compound gas that releases active nitrogen. 7. The method according to claim 6, wherein the compound that releases active nitrogen is ammonia. 7. The method according to claim 6, wherein the compound that releases active nitrogen is an amine compound.

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